SQUASH: poly,asahi: Move the output mask to poly_vertex_state

It makes more sense here along with the output buffer.  I think this
should be squashed with the previous commit (and not sure it works
without).

Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Mary Guillemard <mary@mary.zone>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38404>

src/asahi/libagx/tessellation.cl

@@ -52,6 +52,7 @@ libagx_tess_setup_indirect(
    p->nr_patches = unrolled_patches;
 
    vp->output_buffer = (uintptr_t)(blob + vb_offs);
+   vp->outputs = vertex_outputs;
    p->counts = (global uint32_t *)(blob + count_offs);
 
    if (vp) {

src/asahi/vulkan/hk_cmd_draw.c

@@ -1041,13 +1041,13 @@ hk_index_buffer(uint64_t index_buffer, uint size_el, uint offset_el,
 }
 
 static uint64_t
-hk_upload_vertex_params(struct hk_cmd_buffer *cmd,
-                        uint64_t vertex_output_buffer,
-                        struct agx_draw draw)
+hk_upload_vertex_params(struct hk_cmd_buffer *cmd, struct agx_draw draw)
 {
+   struct hk_graphics_state *gfx = &cmd->state.gfx;
+   struct hk_descriptor_state *desc = &cmd->state.gfx.descriptors;
+
    struct poly_vertex_params params = {
       .verts_per_instance = draw.b.count[0],
-      .output_buffer = vertex_output_buffer,
    };
 
    if (draw.indexed) {
@@ -1060,6 +1060,33 @@ hk_upload_vertex_params(struct hk_cmd_buffer *cmd,
       params.index_buffer_range_el = range_el;
    }
 
+   if (gfx->shaders[MESA_SHADER_TESS_EVAL] ||
+       gfx->shaders[MESA_SHADER_GEOMETRY]) {
+
+      struct hk_shader *vs = hk_bound_sw_vs(gfx);
+      params.outputs = vs->b.info.outputs;
+
+      /* XXX: We should deduplicate this logic */
+      bool indirect = agx_is_indirect(draw.b) || draw.restart;
+
+      if (!indirect) {
+         uint32_t verts = draw.b.count[0], instances = draw.b.count[1];
+         unsigned vb_size =
+            poly_tcs_in_size(verts * instances, vs->b.info.outputs);
+
+         /* Allocate if there are any outputs, or use the null sink to trap
+          * reads if there aren't. Those reads are undefined but should not
+          * fault. Affects:
+          *
+          *    dEQP-VK.pipeline.monolithic.no_position.explicit_declarations.basic.single_view.v0_g1
+          */
+         params.output_buffer = vb_size ? hk_pool_alloc(cmd, vb_size, 4).gpu
+                                        : AGX_SCRATCH_PAGE_ADDRESS;
+      }
+   }
+
+   desc->root.draw.vertex_outputs = params.outputs;
+
    return hk_pool_upload(cmd, &params, sizeof(params), 8);
 }
 
@@ -1121,11 +1148,6 @@ hk_upload_geometry_params(struct hk_cmd_buffer *cmd, struct agx_draw draw)
    struct poly_geometry_params params = {
       .flat_outputs = fs->info.fs.interp.flat,
       .input_topology = mode,
-
-      /* Overriden by the indirect setup kernel. As tess->GS is always indirect,
-       * we can assume here that we're VS->GS.
-       */
-      .input_mask = desc->root.draw.vertex_outputs,
    };
 
    if (gfx->xfb_enabled) {
@@ -3046,36 +3068,9 @@ hk_flush_dynamic_state(struct hk_cmd_buffer *cmd, struct hk_cs *cs,
       gfx->dirty |= HK_DIRTY_VARYINGS;
    }
 
-   uint64_t vertex_output_buffer = 0;
-   if (gfx->shaders[MESA_SHADER_TESS_EVAL] ||
-       gfx->shaders[MESA_SHADER_GEOMETRY]) {
-
-      struct hk_shader *vs = hk_bound_sw_vs(gfx);
-      desc->root.draw.vertex_outputs = vs->b.info.outputs;
-
-      /* XXX: We should deduplicate this logic */
-      bool indirect = agx_is_indirect(draw.b) || draw.restart;
-
-      if (!indirect) {
-         uint32_t verts = draw.b.count[0], instances = draw.b.count[1];
-         unsigned vb_size =
-            poly_tcs_in_size(verts * instances, vs->b.info.outputs);
-
-         /* Allocate if there are any outputs, or use the null sink to trap
-          * reads if there aren't. Those reads are undefined but should not
-          * fault. Affects:
-          *
-          *    dEQP-VK.pipeline.monolithic.no_position.explicit_declarations.basic.single_view.v0_g1
-          */
-         vertex_output_buffer = vb_size ? hk_pool_alloc(cmd, vb_size, 4).gpu
-                                        : AGX_SCRATCH_PAGE_ADDRESS;
-      }
-   }
-
    if (gfx->shaders[MESA_SHADER_TESS_EVAL] ||
        gfx->shaders[MESA_SHADER_GEOMETRY] || linked_vs->sw_indexing) {
-      desc->root.draw.vertex_params =
-         hk_upload_vertex_params(cmd, vertex_output_buffer, draw);
+      desc->root.draw.vertex_params = hk_upload_vertex_params(cmd, draw);
       desc->root_dirty = true;
    }
 

src/gallium/drivers/asahi/agx_state.c

@@ -3987,7 +3987,7 @@ agx_batch_geometry_params(struct agx_batch *batch, uint64_t input_index_buffer,
     * & count buffers. GPU calculates and allocates for indirect draws.
     */
    batch->uniforms.vertex_outputs = batch->ctx->vs->b.info.outputs;
-   params.input_mask = batch->uniforms.vertex_outputs;
+   vp.outputs = batch->uniforms.vertex_outputs;
    params.count_buffer_stride = batch->ctx->gs->gs.count_words * 4;
 
    bool prefix_sum = batch->ctx->gs->gs.prefix_sum;
@@ -4557,6 +4557,7 @@ agx_draw_patches(struct agx_context *ctx, const struct pipe_draw_info *info,
       .index_buffer = ib,
       .index_buffer_range_el = ib_extent,
       .verts_per_instance = draws ? draws->count : 0,
+      .outputs = ctx->vs->b.info.outputs,
    };
 
    agx_upload_draw_params(batch, indirect, draws, info);

src/poly/cl/geometry.cl

@@ -363,6 +363,12 @@ poly_vertex_output_buffer(constant struct poly_vertex_params *p)
    return p->output_buffer;
 }
 
+uint64_t
+poly_vertex_outputs(constant struct poly_vertex_params *p)
+{
+   return p->outputs;
+}
+
 uintptr_t
 poly_vertex_output_address(constant struct poly_vertex_params *p,
                            uint64_t mask, uint vtx, gl_varying_slot location)
@@ -372,12 +378,6 @@ poly_vertex_output_address(constant struct poly_vertex_params *p,
       ((uintptr_t)poly_tcs_in_offs_el(vtx, location, mask)) * 16;
 }
 
-uint64_t
-poly_geometry_input_mask(constant struct poly_geometry_params *p)
-{
-   return p->input_mask;
-}
-
 unsigned
 poly_input_vertices(constant struct poly_vertex_params *p)
 {

src/poly/geometry.h

@@ -192,8 +192,11 @@ struct poly_vertex_params {
 
    /* Output buffer for vertex data */
    uint64_t output_buffer;
+
+   /* Mask of outputs present in the output buffer */
+   uint64_t outputs;
 } PACKED;
-static_assert(sizeof(struct poly_vertex_params) == 6 * 4);
+static_assert(sizeof(struct poly_vertex_params) == 8 * 4);
 
 static inline uint
 poly_index_buffer_range_el(uint size_el, uint offset_el)
@@ -230,12 +233,6 @@ struct poly_geometry_params {
     */
    DEVICE(uchar) xfb_base[POLY_MAX_SO_BUFFERS];
 
-   /* Address and present mask for the input to the geometry shader. These will
-    * reflect the vertex shader for VS->GS or instead the tessellation
-    * evaluation shader for TES->GS.
-    */
-   uint64_t input_mask;
-
    /* Location-indexed mask of flat outputs, used for lowering GL edge flags. */
    uint64_t flat_outputs;
 
@@ -277,7 +274,7 @@ struct poly_geometry_params {
     */
    uint32_t input_topology;
 } PACKED;
-static_assert(sizeof(struct poly_geometry_params) == 84 * 4);
+static_assert(sizeof(struct poly_geometry_params) == 82 * 4);
 
 /* TCS shared memory layout:
  *
@@ -578,7 +575,7 @@ poly_gs_setup_indirect(uint64_t index_buffer, constant uint *draw,
    vp->output_buffer =
       (uintptr_t)poly_heap_alloc_nonatomic(heap, vertex_buffer_size);
 
-   p->input_mask = vs_outputs;
+   vp->outputs = vs_outputs;
 
    /* Allocate the index buffer and write the draw consuming it */
    global VkDrawIndexedIndirectCommand *cmd = (global void *)p->indirect_desc;

src/poly/nir/poly_nir_lower_gs.c

@@ -285,11 +285,12 @@ poly_load_per_vertex_input(nir_builder *b, nir_intrinsic_instr *intr,
    nir_def *location = nir_iadd_imm(b, intr->src[1].ssa, sem.location);
    nir_def *addr;
 
+   nir_def *vp = nir_load_vertex_param_buffer_poly(b);
+
    nir_def *input_mask;
    if (b->shader->info.stage == MESA_SHADER_GEOMETRY) {
       /* GS may be preceded by VS or TES so specified as param */
-      input_mask = poly_geometry_input_mask(
-         b, nir_load_geometry_param_buffer_poly(b));
+      input_mask = poly_vertex_outputs(b, vp);
    } else {
       assert(b->shader->info.stage == MESA_SHADER_TESS_CTRL);
 
@@ -297,7 +298,6 @@ poly_load_per_vertex_input(nir_builder *b, nir_intrinsic_instr *intr,
       input_mask = nir_load_vs_outputs_poly(b);
    }
 
-   nir_def *vp = nir_load_vertex_param_buffer_poly(b);
    addr = poly_vertex_output_address(b, vp, input_mask, vertex, location);
 
    addr = nir_iadd_imm(b, addr, 4 * nir_intrinsic_component(intr));