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freedreno/ir3: sync disasm changes from envytools
Signed-off-by: Rob Clark <robdclark@chromium.org>
This commit is contained in:
Rob Clark
Rob Clark
parent
f3980a8ef7
commit
5f45818673
2 changed files with 95 additions and 25 deletions
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@ -36,6 +36,7 @@
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enum debug_t {
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PRINT_RAW = 0x1, /* dump raw hexdump */
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PRINT_VERBOSE = 0x2,
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EXPAND_REPEAT = 0x4,
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};
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static enum debug_t debug;
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@ -81,6 +82,8 @@ struct disasm_ctx {
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/* current instruction repeat flag: */
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unsigned repeat;
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/* current instruction repeat indx/offset (for --expand): */
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unsigned repeatidx;
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};
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static void print_reg(struct disasm_ctx *ctx, reg_t reg, bool full, bool r,
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@ -122,15 +125,31 @@ static void print_reg(struct disasm_ctx *ctx, reg_t reg, bool full, bool r,
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}
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}
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static unsigned regidx(reg_t reg)
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{
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return (4 * reg.num) + reg.comp;
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}
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static reg_t idxreg(unsigned idx)
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{
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return (reg_t){
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.comp = idx & 0x3,
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.num = idx >> 2,
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};
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}
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static void print_reg_dst(struct disasm_ctx *ctx, reg_t reg, bool full, bool addr_rel)
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{
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reg = idxreg(regidx(reg) + ctx->repeatidx);
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print_reg(ctx, reg, full, false, false, false, false, false, addr_rel);
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}
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static void print_reg_src(struct disasm_ctx *ctx, reg_t reg, bool full, bool r,
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bool c, bool im, bool neg, bool abs, bool addr_rel)
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{
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if (r)
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reg = idxreg(regidx(reg) + ctx->repeatidx);
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print_reg(ctx, reg, full, r, c, im, neg, abs, addr_rel);
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}
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@ -770,14 +789,13 @@ static void print_instr_cat6_a3xx(struct disasm_ctx *ctx, instr_t *instr)
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/* note: dst might actually be a src (ie. address to store to) */
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print_src(ctx, &dst);
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if (cat6->dst_off && cat6->g) {
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struct reginfo dstoff_reg = {};
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struct reginfo dstoff_reg = {0};
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dstoff_reg.reg = (reg_t) cat6->c.off;
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dstoff_reg.full = true;
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dstoff_reg.full = true;
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fprintf(ctx->out, "+");
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print_src(ctx, &dstoff_reg);
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} else if (dstoff) {
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} else if (dstoff)
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fprintf(ctx->out, "%+d", dstoff);
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}
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if (sd)
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fprintf(ctx->out, "]");
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fprintf(ctx->out, ", ");
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@ -989,6 +1007,9 @@ static const struct opc_info {
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OPC(4, OPC_SIN, sin),
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OPC(4, OPC_COS, cos),
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OPC(4, OPC_SQRT, sqrt),
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OPC(4, OPC_HRSQ, hrsq),
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OPC(4, OPC_HLOG2, hlog2),
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OPC(4, OPC_HEXP2, hexp2),
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/* category 5: */
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OPC(5, OPC_ISAM, isam),
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@ -1069,11 +1090,35 @@ const char *ir3_instr_name(struct ir3_instruction *instr)
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return opcs[instr->opc].name;
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}
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static void print_single_instr(struct disasm_ctx *ctx, instr_t *instr)
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{
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const char *name = GETINFO(instr)->name;
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uint32_t opc = instr_opc(instr, ctx->gpu_id);
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if (name) {
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fprintf(ctx->out, "%s", name);
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GETINFO(instr)->print(ctx, instr);
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} else {
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fprintf(ctx->out, "unknown(%d,%d)", instr->opc_cat, opc);
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switch (instr->opc_cat) {
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case 0: print_instr_cat0(ctx, instr); break;
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case 1: print_instr_cat1(ctx, instr); break;
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case 2: print_instr_cat2(ctx, instr); break;
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case 3: print_instr_cat3(ctx, instr); break;
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case 4: print_instr_cat4(ctx, instr); break;
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case 5: print_instr_cat5(ctx, instr); break;
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case 6: print_instr_cat6(ctx, instr); break;
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case 7: print_instr_cat7(ctx, instr); break;
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}
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}
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}
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static bool print_instr(struct disasm_ctx *ctx, uint32_t *dwords, int n)
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{
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instr_t *instr = (instr_t *)dwords;
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uint32_t opc = instr_opc(instr, ctx->gpu_id);
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const char *name;
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unsigned nop = 0;
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if (debug & PRINT_VERBOSE)
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fprintf(ctx->out, "%s%04d[%08xx_%08xx] ", levels[ctx->level], n, dwords[1], dwords[0]);
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@ -1085,37 +1130,47 @@ static bool print_instr(struct disasm_ctx *ctx, uint32_t *dwords, int n)
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ctx->repeat = instr_repeat(instr);
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if (instr->sync)
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if (instr->sync) {
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fprintf(ctx->out, "(sy)");
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if (instr->ss && ((instr->opc_cat <= 4) || (instr->opc_cat == 7)))
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}
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if (instr->ss && ((instr->opc_cat <= 4) || (instr->opc_cat == 7))) {
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fprintf(ctx->out, "(ss)");
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}
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if (instr->jmp_tgt)
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fprintf(ctx->out, "(jp)");
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if (instr_sat(instr))
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fprintf(ctx->out, "(sat)");
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if (ctx->repeat) {
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if (ctx->repeat)
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fprintf(ctx->out, "(rpt%d)", ctx->repeat);
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} else if ((instr->opc_cat == 2) && (instr->cat2.src1_r || instr->cat2.src2_r)) {
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unsigned nop = (instr->cat2.src2_r * 2) + instr->cat2.src1_r;
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else if ((instr->opc_cat == 2) && (instr->cat2.src1_r || instr->cat2.src2_r))
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nop = (instr->cat2.src2_r * 2) + instr->cat2.src1_r;
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else if ((instr->opc_cat == 3) && (instr->cat3.src1_r || instr->cat3.src2_r))
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nop = (instr->cat3.src2_r * 2) + instr->cat3.src1_r;
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if (nop)
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fprintf(ctx->out, "(nop%d)", nop);
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} else if ((instr->opc_cat == 3) && (instr->cat3.src1_r || instr->cat3.src2_r)) {
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unsigned nop = (instr->cat3.src2_r * 2) + instr->cat3.src1_r;
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fprintf(ctx->out, "(nop%d)", nop);
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}
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if (instr->ul && ((2 <= instr->opc_cat) && (instr->opc_cat <= 4)))
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fprintf(ctx->out, "(ul)");
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name = GETINFO(instr)->name;
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if (name) {
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fprintf(ctx->out, "%s", name);
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GETINFO(instr)->print(ctx, instr);
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} else {
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fprintf(ctx->out, "unknown(%d,%d)", instr->opc_cat, opc);
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}
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print_single_instr(ctx, instr);
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fprintf(ctx->out, "\n");
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if ((instr->opc_cat <= 4) && (debug & EXPAND_REPEAT)) {
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int i;
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for (i = 0; i < nop; i++) {
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fprintf(ctx->out, "%s%04d[ ] ", levels[ctx->level], n);
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fprintf(ctx->out, "nop\n");
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}
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for (i = 0; i < ctx->repeat; i++) {
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ctx->repeatidx = i + 1;
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fprintf(ctx->out, "%s%04d[ ] ", levels[ctx->level], n);
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print_single_instr(ctx, instr);
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fprintf(ctx->out, "\n");
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}
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ctx->repeatidx = 0;
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}
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return (instr->opc_cat == 0) && (opc == OPC_END);
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}
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@ -1123,6 +1178,7 @@ int disasm_a3xx(uint32_t *dwords, int sizedwords, int level, FILE *out, unsigned
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{
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struct disasm_ctx ctx;
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int i;
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int nop_count = 0;
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assert((sizedwords % 2) == 0);
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@ -1131,8 +1187,15 @@ int disasm_a3xx(uint32_t *dwords, int sizedwords, int level, FILE *out, unsigned
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ctx.level = level;
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ctx.gpu_id = gpu_id;
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for (i = 0; i < sizedwords; i += 2)
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for (i = 0; i < sizedwords; i += 2) {
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print_instr(&ctx, &dwords[i], i/2);
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if (dwords[i] == 0 && dwords[i + 1] == 0)
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nop_count++;
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else
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nop_count = 0;
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if (nop_count > 3)
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break;
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}
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return 0;
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}
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@ -136,7 +136,14 @@ typedef enum {
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OPC_SIN = _OPC(4, 4),
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OPC_COS = _OPC(4, 5),
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OPC_SQRT = _OPC(4, 6),
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// 7-63 - invalid
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/* NOTE that these are 8+opc from their highp equivs, so it's possible
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* that the high order bit in the opc field has been repurposed for
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* half-precision use? But note that other ops (rcp/lsin/cos/sqrt)
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* still use the same opc as highp
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*/
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OPC_HRSQ = _OPC(4, 9),
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OPC_HLOG2 = _OPC(4, 10),
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OPC_HEXP2 = _OPC(4, 11),
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/* category 5: */
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OPC_ISAM = _OPC(5, 0),
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