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i965: Delete brw_state_flags::cache and related code.

Browse source 
It's been merged into brw_state_flags::brw for simplicity and
efficiency.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
This commit is contained in:
Kenneth Graunke 2014-11-25 00:35:31 -08:00
parent 4f24c168c8
commit 5f34a18f96
34 changed files with 4 additions and 82 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/mesa/drivers/dri/i965/brw_binding_tables.c
View file

@ -195,7 +195,6 @@ const struct brw_tracked_state brw_binding_table_pointers = {
BRW_NEW_PS_BINDING_TABLE |
BRW_NEW_STATE_BASE_ADDRESS |
BRW_NEW_VS_BINDING_TABLE,
.cache = 0,
},
.emit = gen4_upload_binding_table_pointers,
};
@ -232,7 +231,6 @@ const struct brw_tracked_state gen6_binding_table_pointers = {
BRW_NEW_PS_BINDING_TABLE |
BRW_NEW_STATE_BASE_ADDRESS |
BRW_NEW_VS_BINDING_TABLE,
.cache = 0,
},
.emit = gen6_upload_binding_table_pointers,
};

1
src/mesa/drivers/dri/i965/brw_blorp.cpp
View file

@ -277,7 +277,6 @@ retry:
* rendering tracks for GL.
*/
brw->state.dirty.brw = ~0ull;
brw->state.dirty.cache = ~0;
brw->no_depth_or_stencil = false;
brw->ib.type = -1;

3
src/mesa/drivers/dri/i965/brw_cc.c
View file

@ -77,7 +77,6 @@ const struct brw_tracked_state brw_cc_vp = {
.mesa = _NEW_TRANSFORM |
_NEW_VIEWPORT,
.brw = BRW_NEW_BATCH,
.cache = 0
},
.emit = brw_upload_cc_vp
};
@ -250,7 +249,6 @@ const struct brw_tracked_state brw_cc_unit = {
.brw = BRW_NEW_BATCH |
BRW_NEW_CC_VP |
BRW_NEW_STATS_WM,
.cache = 0
},
.emit = upload_cc_unit,
};
@ -272,7 +270,6 @@ const struct brw_tracked_state brw_blend_constant_color = {
.dirty = {
.mesa = _NEW_COLOR,
.brw = BRW_NEW_CONTEXT,
.cache = 0
},
.emit = upload_blend_constant_color
};

12
src/mesa/drivers/dri/i965/brw_context.h
View file

@ -287,15 +287,6 @@ struct brw_state_flags {
* State update flags signalled as the result of brw_tracked_state updates
*/
uint64_t brw;
/**
* State update flags that used to be signalled by brw_state_cache.c
* searches.
*
* Now almost all of that state is just streamed out on demand, but the
* flags for those state blobs updating have stayed in the same bitfield.
* brw_state_cache.c still flags BRW_NEW_*_PROG_DATA.
*/
GLuint cache;
};
/** Subclass of Mesa vertex program */
@ -740,8 +731,7 @@ struct brw_gs_prog_data
struct brw_cache_item {
/**
* Effectively part of the key, cache_id identifies what kind of state
* buffer is involved, and also which brw->state.dirty.cache flag should
* be set when this cache item is chosen.
* buffer is involved, and also which dirty flag should set.
*/
enum brw_cache_id cache_id;
/** 32-bit hash of the key data */

2
src/mesa/drivers/dri/i965/brw_draw_upload.c
View file

@ -952,7 +952,6 @@ const struct brw_tracked_state brw_indices = {
.dirty = {
.mesa = 0,
.brw = BRW_NEW_INDICES,
.cache = 0,
},
.emit = brw_upload_indices,
};
@ -990,7 +989,6 @@ const struct brw_tracked_state brw_index_buffer = {
.mesa = 0,
.brw = BRW_NEW_BATCH |
BRW_NEW_INDEX_BUFFER,
.cache = 0,
},
.emit = brw_emit_index_buffer,
};

8
src/mesa/drivers/dri/i965/brw_misc_state.c
View file

@ -64,7 +64,6 @@ const struct brw_tracked_state brw_drawing_rect = {
.dirty = {
.mesa = _NEW_BUFFERS,
.brw = BRW_NEW_CONTEXT,
.cache = 0
},
.emit = upload_drawing_rect
};
@ -702,7 +701,6 @@ const struct brw_tracked_state brw_depthbuffer = {
.dirty = {
.mesa = _NEW_BUFFERS,
.brw = BRW_NEW_BATCH,
.cache = 0,
},
.emit = brw_emit_depthbuffer,
};
@ -751,7 +749,6 @@ const struct brw_tracked_state brw_polygon_stipple = {
.mesa = _NEW_POLYGON |
_NEW_POLYGONSTIPPLE,
.brw = BRW_NEW_CONTEXT,
.cache = 0
},
.emit = upload_polygon_stipple
};
@ -795,7 +792,6 @@ const struct brw_tracked_state brw_polygon_stipple_offset = {
.mesa = _NEW_BUFFERS |
_NEW_POLYGON,
.brw = BRW_NEW_CONTEXT,
.cache = 0
},
.emit = upload_polygon_stipple_offset
};
@ -829,7 +825,6 @@ const struct brw_tracked_state brw_aa_line_parameters = {
.dirty = {
.mesa = _NEW_LINE,
.brw = BRW_NEW_CONTEXT,
.cache = 0
},
.emit = upload_aa_line_parameters
};
@ -874,7 +869,6 @@ const struct brw_tracked_state brw_line_stipple = {
.dirty = {
.mesa = _NEW_LINE,
.brw = BRW_NEW_CONTEXT,
.cache = 0
},
.emit = upload_line_stipple
};
@ -932,7 +926,6 @@ const struct brw_tracked_state brw_invariant_state = {
.dirty = {
.mesa = 0,
.brw = BRW_NEW_CONTEXT,
.cache = 0
},
.emit = brw_upload_invariant_state
};
@ -1056,7 +1049,6 @@ const struct brw_tracked_state brw_state_base_address = {
.mesa = 0,
.brw = BRW_NEW_BATCH |
BRW_NEW_PROGRAM_CACHE,
.cache = 0,
},
.emit = upload_state_base_address
};

1
src/mesa/drivers/dri/i965/brw_primitive_restart.c
View file

@ -211,7 +211,6 @@ const struct brw_tracked_state haswell_cut_index = {
.dirty = {
.mesa = _NEW_TRANSFORM,
.brw = BRW_NEW_INDEX_BUFFER,
.cache = 0,
},
.emit = haswell_upload_cut_index,
};

3
src/mesa/drivers/dri/i965/brw_sampler_state.c
View file

@ -529,7 +529,6 @@ const struct brw_tracked_state brw_fs_samplers = {
.mesa = _NEW_TEXTURE,
.brw = BRW_NEW_BATCH |
BRW_NEW_FRAGMENT_PROGRAM,
.cache = 0
},
.emit = brw_upload_fs_samplers,
};
@ -548,7 +547,6 @@ const struct brw_tracked_state brw_vs_samplers = {
.mesa = _NEW_TEXTURE,
.brw = BRW_NEW_BATCH |
BRW_NEW_VERTEX_PROGRAM,
.cache = 0
},
.emit = brw_upload_vs_samplers,
};
@ -571,7 +569,6 @@ const struct brw_tracked_state brw_gs_samplers = {
.mesa = _NEW_TEXTURE,
.brw = BRW_NEW_BATCH |
BRW_NEW_GEOMETRY_PROGRAM,
.cache = 0
},
.emit = brw_upload_gs_samplers,
};

1
src/mesa/drivers/dri/i965/brw_sf_state.c
View file

@ -118,7 +118,6 @@ const struct brw_tracked_state brw_sf_vp = {
_NEW_SCISSOR |
_NEW_VIEWPORT,
.brw = BRW_NEW_BATCH,
.cache = 0
},
.emit = upload_sf_vp
};

1
src/mesa/drivers/dri/i965/brw_state_cache.c
View file

@ -401,7 +401,6 @@ brw_clear_cache(struct brw_context *brw, struct brw_cache *cache)
*/
brw->state.dirty.mesa |= ~0;
brw->state.dirty.brw |= ~0ull;
brw->state.dirty.cache |= ~0;
intel_batchbuffer_flush(brw);
}

20
src/mesa/drivers/dri/i965/brw_state_upload.c
View file

@ -377,9 +377,7 @@ void brw_init_state( struct brw_context *brw )
brw->num_atoms = num_atoms;
while (num_atoms--) {
assert((*atoms)->dirty.mesa |
(*atoms)->dirty.brw |
(*atoms)->dirty.cache);
assert((*atoms)->dirty.mesa | (*atoms)->dirty.brw);
assert((*atoms)->emit);
atoms++;
}
@ -419,9 +417,7 @@ void brw_destroy_state( struct brw_context *brw )
static bool
check_state(const struct brw_state_flags *a, const struct brw_state_flags *b)
{
return ((a->mesa & b->mesa) |
(a->brw & b->brw) |
(a->cache & b->cache)) != 0;
return ((a->mesa & b->mesa) | (a->brw & b->brw)) != 0;
}
static void accumulate_state( struct brw_state_flags *a,
@ -429,7 +425,6 @@ static void accumulate_state( struct brw_state_flags *a,
{
a->mesa |= b->mesa;
a->brw |= b->brw;
a->cache |= b->cache;
}
@ -439,7 +434,6 @@ static void xor_states( struct brw_state_flags *result,
{
result->mesa = a->mesa ^ b->mesa;
result->brw = a->brw ^ b->brw;
result->cache = a->cache ^ b->cache;
}
struct dirty_bit_map {
@ -534,11 +528,6 @@ static struct dirty_bit_map brw_bits[] = {
{0, 0, 0}
};
static struct dirty_bit_map cache_bits[] = {
{0, 0, 0}
};
static void
brw_update_dirty_count(struct dirty_bit_map *bit_map, uint64_t bits)
{
@ -577,7 +566,6 @@ void brw_upload_state(struct brw_context *brw)
/* Always re-emit all state. */
state->mesa |= ~0;
state->brw |= ~0ull;
state->cache |= ~0;
}
if (brw->fragment_program != ctx->FragmentProgram._Current) {
@ -605,7 +593,7 @@ void brw_upload_state(struct brw_context *brw)
brw->state.dirty.brw |= BRW_NEW_NUM_SAMPLES;
}
if ((state->mesa | state->cache | state->brw) == 0)
if ((state->mesa | state->brw) == 0)
return;
if (unlikely(INTEL_DEBUG)) {
@ -651,11 +639,9 @@ void brw_upload_state(struct brw_context *brw)
brw_update_dirty_count(mesa_bits, state->mesa);
brw_update_dirty_count(brw_bits, state->brw);
brw_update_dirty_count(cache_bits, state->cache);
if (dirty_count++ % 1000 == 0) {
brw_print_dirty_count(mesa_bits);
brw_print_dirty_count(brw_bits);
brw_print_dirty_count(cache_bits);
fprintf(stderr, "\n");
}
}

1
src/mesa/drivers/dri/i965/brw_vs.c
View file

@ -520,7 +520,6 @@ const struct brw_tracked_state brw_vs_prog = {
_NEW_TRANSFORM,
.brw = BRW_NEW_VERTEX_PROGRAM |
BRW_NEW_VERTICES,
.cache = 0
},
.emit = brw_upload_vs_prog
};

3
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
View file

@ -738,7 +738,6 @@ const struct brw_tracked_state brw_renderbuffer_surfaces = {
.mesa = _NEW_BUFFERS |
_NEW_COLOR,
.brw = BRW_NEW_BATCH,
.cache = 0
},
.emit = brw_update_renderbuffer_surfaces,
};
@ -747,7 +746,6 @@ const struct brw_tracked_state gen6_renderbuffer_surfaces = {
.dirty = {
.mesa = _NEW_BUFFERS,
.brw = BRW_NEW_BATCH,
.cache = 0
},
.emit = brw_update_renderbuffer_surfaces,
};
@ -829,7 +827,6 @@ const struct brw_tracked_state brw_texture_surfaces = {
BRW_NEW_GEOMETRY_PROGRAM |
BRW_NEW_TEXTURE_BUFFER |
BRW_NEW_VERTEX_PROGRAM,
.cache = 0
},
.emit = brw_update_texture_surfaces,
};

2
src/mesa/drivers/dri/i965/gen6_cc.c
View file

@ -246,7 +246,6 @@ const struct brw_tracked_state gen6_blend_state = {
_NEW_MULTISAMPLE,
.brw = BRW_NEW_BATCH |
BRW_NEW_STATE_BASE_ADDRESS,
.cache = 0,
},
.emit = gen6_upload_blend_state,
};
@ -300,7 +299,6 @@ const struct brw_tracked_state gen6_color_calc_state = {
_NEW_STENCIL,
.brw = BRW_NEW_BATCH |
BRW_NEW_STATE_BASE_ADDRESS,
.cache = 0,
},
.emit = gen6_upload_color_calc_state,
};

1
src/mesa/drivers/dri/i965/gen6_depthstencil.c
View file

@ -109,7 +109,6 @@ const struct brw_tracked_state gen6_depth_stencil_state = {
_NEW_STENCIL,
.brw = BRW_NEW_BATCH |
BRW_NEW_STATE_BASE_ADDRESS,
.cache = 0,
},
.emit = gen6_upload_depth_stencil_state,
};

1
src/mesa/drivers/dri/i965/gen6_multisample_state.c
View file

@ -205,7 +205,6 @@ const struct brw_tracked_state gen6_multisample_state = {
.mesa = _NEW_MULTISAMPLE,
.brw = BRW_NEW_CONTEXT |
BRW_NEW_NUM_SAMPLES,
.cache = 0
},
.emit = upload_multisample_state
};

1
src/mesa/drivers/dri/i965/gen6_sampler_state.c
View file

@ -51,7 +51,6 @@ const struct brw_tracked_state gen6_sampler_state = {
.brw = BRW_NEW_BATCH |
BRW_NEW_SAMPLER_STATE_TABLE |
BRW_NEW_STATE_BASE_ADDRESS,
.cache = 0,
},
.emit = upload_sampler_state_pointers,
};

1
src/mesa/drivers/dri/i965/gen6_scissor_state.c
View file

@ -96,7 +96,6 @@ const struct brw_tracked_state gen6_scissor_state = {
_NEW_SCISSOR |
_NEW_VIEWPORT,
.brw = BRW_NEW_BATCH,
.cache = 0,
},
.emit = gen6_upload_scissor_state,
};

2
src/mesa/drivers/dri/i965/gen6_sol.c
View file

@ -95,7 +95,6 @@ const struct brw_tracked_state gen6_sol_surface = {
BRW_NEW_GEOMETRY_PROGRAM |
BRW_NEW_VERTEX_PROGRAM |
BRW_NEW_TRANSFORM_FEEDBACK,
.cache = 0
},
.emit = gen6_update_sol_surfaces,
};
@ -190,7 +189,6 @@ const struct brw_tracked_state gen6_gs_binding_table = {
BRW_NEW_GEOMETRY_PROGRAM |
BRW_NEW_VERTEX_PROGRAM |
BRW_NEW_SURFACES,
.cache = 0
},
.emit = brw_gs_upload_binding_table,
};

3
src/mesa/drivers/dri/i965/gen6_viewport_state.c
View file

@ -70,7 +70,6 @@ const struct brw_tracked_state gen6_clip_vp = {
.dirty = {
.mesa = _NEW_VIEWPORT,
.brw = BRW_NEW_BATCH,
.cache = 0,
},
.emit = gen6_upload_clip_vp,
};
@ -114,7 +113,6 @@ const struct brw_tracked_state gen6_sf_vp = {
.mesa = _NEW_BUFFERS |
_NEW_VIEWPORT,
.brw = BRW_NEW_BATCH,
.cache = 0,
},
.emit = gen6_upload_sf_vp,
};
@ -140,7 +138,6 @@ const struct brw_tracked_state gen6_viewport_state = {
BRW_NEW_CLIP_VP |
BRW_NEW_SF_VP |
BRW_NEW_STATE_BASE_ADDRESS,
.cache = 0,
},
.emit = upload_viewport_state_pointers,
};

1
src/mesa/drivers/dri/i965/gen7_disable.c
View file

@ -93,7 +93,6 @@ const struct brw_tracked_state gen7_disable_stages = {
.dirty = {
.mesa = 0,
.brw = BRW_NEW_CONTEXT,
.cache = 0,
},
.emit = disable_stages,
};

1
src/mesa/drivers/dri/i965/gen7_misc_state.c
View file

@ -205,7 +205,6 @@ const struct brw_tracked_state gen7_depthbuffer = {
_NEW_DEPTH |
_NEW_STENCIL,
.brw = BRW_NEW_BATCH,
.cache = 0,
},
.emit = brw_emit_depthbuffer,
};

1
src/mesa/drivers/dri/i965/gen7_sf_state.c
View file

@ -257,7 +257,6 @@ const struct brw_tracked_state gen7_sf_state = {
_NEW_PROGRAM |
_NEW_SCISSOR,
.brw = BRW_NEW_CONTEXT,
.cache = 0,
},
.emit = upload_sf_state,
};

1
src/mesa/drivers/dri/i965/gen7_urb.c
View file

@ -131,7 +131,6 @@ const struct brw_tracked_state gen7_push_constant_space = {
.dirty = {
.mesa = 0,
.brw = BRW_NEW_CONTEXT | BRW_NEW_GEOMETRY_PROGRAM,
.cache = 0,
},
.emit = gen7_allocate_push_constants,
};

1
src/mesa/drivers/dri/i965/gen7_viewport_state.c
View file

@ -95,7 +95,6 @@ const struct brw_tracked_state gen7_sf_clip_viewport = {
.mesa = _NEW_BUFFERS |
_NEW_VIEWPORT,
.brw = BRW_NEW_BATCH,
.cache = 0,
},
.emit = gen7_upload_sf_clip_viewport,
};

2
src/mesa/drivers/dri/i965/gen8_blend_state.c
View file

@ -204,7 +204,6 @@ const struct brw_tracked_state gen8_blend_state = {
_NEW_MULTISAMPLE,
.brw = BRW_NEW_BATCH |
BRW_NEW_STATE_BASE_ADDRESS,
.cache = 0,
},
.emit = gen8_upload_blend_state,
};
@ -297,7 +296,6 @@ const struct brw_tracked_state gen8_ps_blend = {
_NEW_MULTISAMPLE,
.brw = BRW_NEW_CONTEXT |
BRW_NEW_FRAGMENT_PROGRAM,
.cache = 0,
},
.emit = gen8_upload_ps_blend
};

1
src/mesa/drivers/dri/i965/gen8_disable.c
View file

@ -114,7 +114,6 @@ const struct brw_tracked_state gen8_disable_stages = {
.dirty = {
.mesa = 0,
.brw = BRW_NEW_CONTEXT,
.cache = 0,
},
.emit = disable_stages,
};

2
src/mesa/drivers/dri/i965/gen8_draw_upload.c
View file

@ -262,7 +262,6 @@ const struct brw_tracked_state gen8_index_buffer = {
.mesa = 0,
.brw = BRW_NEW_BATCH |
BRW_NEW_INDEX_BUFFER,
.cache = 0,
},
.emit = gen8_emit_index_buffer,
};
@ -280,7 +279,6 @@ const struct brw_tracked_state gen8_vf_topology = {
.dirty = {
.mesa = 0,
.brw = BRW_NEW_PRIMITIVE,
.cache = 0,
},
.emit = gen8_emit_vf_topology,
};

1
src/mesa/drivers/dri/i965/gen8_misc_state.c
View file

@ -80,7 +80,6 @@ const struct brw_tracked_state gen8_state_base_address = {
.mesa = 0,
.brw = BRW_NEW_BATCH |
BRW_NEW_PROGRAM_CACHE,
.cache = 0,
},
.emit = upload_state_base_address
};

1
src/mesa/drivers/dri/i965/gen8_multisample_state.c
View file

@ -85,7 +85,6 @@ const struct brw_tracked_state gen8_multisample_state = {
.mesa = _NEW_MULTISAMPLE,
.brw = BRW_NEW_CONTEXT |
BRW_NEW_NUM_SAMPLES,
.cache = 0
},
.emit = upload_multisample_state
};

2
src/mesa/drivers/dri/i965/gen8_sf_state.c
View file

@ -209,7 +209,6 @@ const struct brw_tracked_state gen8_sf_state = {
_NEW_MULTISAMPLE |
_NEW_POINT,
.brw = BRW_NEW_CONTEXT,
.cache = 0,
},
.emit = upload_sf,
};
@ -327,7 +326,6 @@ const struct brw_tracked_state gen8_raster_state = {
_NEW_SCISSOR |
_NEW_TRANSFORM,
.brw = BRW_NEW_CONTEXT,
.cache = 0,
},
.emit = upload_raster,
};

1
src/mesa/drivers/dri/i965/gen8_sol_state.c
View file

@ -170,7 +170,6 @@ const struct brw_tracked_state gen8_sol_state = {
.brw = BRW_NEW_BATCH |
BRW_NEW_TRANSFORM_FEEDBACK |
BRW_NEW_VUE_MAP_GEOM_OUT,
.cache = 0,
},
.emit = upload_sol_state,
};

1
src/mesa/drivers/dri/i965/gen8_viewport_state.c
View file

@ -133,7 +133,6 @@ const struct brw_tracked_state gen8_sf_clip_viewport = {
.mesa = _NEW_BUFFERS |
_NEW_VIEWPORT,
.brw = BRW_NEW_BATCH,
.cache = 0,
},
.emit = gen8_upload_sf_clip_viewport,
};

1
src/mesa/drivers/dri/i965/gen8_wm_depth_stencil.c
View file

@ -112,7 +112,6 @@ const struct brw_tracked_state gen8_wm_depth_stencil = {
_NEW_DEPTH |
_NEW_STENCIL,
.brw = BRW_NEW_CONTEXT,
.cache = 0,
},
.emit = gen8_upload_wm_depth_stencil,
};