From 5ebe75fab1f963fbe8c37f4b9892028f3bc76b36 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Sat, 27 Apr 2024 07:25:46 -0400 Subject: [PATCH] radeonsi: remove GDS tests They were useful in the past. Not anymore. Reviewed-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/gallium/drivers/radeonsi/si_cp_dma.c | 47 ----------------------- src/gallium/drivers/radeonsi/si_pipe.c | 49 ------------------------ src/gallium/drivers/radeonsi/si_pipe.h | 4 -- 3 files changed, 100 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_cp_dma.c b/src/gallium/drivers/radeonsi/si_cp_dma.c index 6459b89c4fd..ba5f30e4c1c 100644 --- a/src/gallium/drivers/radeonsi/si_cp_dma.c +++ b/src/gallium/drivers/radeonsi/si_cp_dma.c @@ -434,53 +434,6 @@ void si_cp_dma_copy_buffer(struct si_context *sctx, struct pipe_resource *dst, sctx->num_cp_dma_calls++; } -void si_test_gds(struct si_context *sctx) -{ - struct pipe_context *ctx = &sctx->b; - struct pipe_resource *src, *dst; - unsigned r[4] = {}; - unsigned offset = debug_get_num_option("OFFSET", 16); - - src = pipe_buffer_create(ctx->screen, 0, PIPE_USAGE_DEFAULT, 16); - dst = pipe_buffer_create(ctx->screen, 0, PIPE_USAGE_DEFAULT, 16); - si_cp_dma_clear_buffer(sctx, &sctx->gfx_cs, src, 0, 4, 0xabcdef01, SI_OP_SYNC_BEFORE_AFTER, - SI_COHERENCY_SHADER, L2_BYPASS); - si_cp_dma_clear_buffer(sctx, &sctx->gfx_cs, src, 4, 4, 0x23456789, SI_OP_SYNC_BEFORE_AFTER, - SI_COHERENCY_SHADER, L2_BYPASS); - si_cp_dma_clear_buffer(sctx, &sctx->gfx_cs, src, 8, 4, 0x87654321, SI_OP_SYNC_BEFORE_AFTER, - SI_COHERENCY_SHADER, L2_BYPASS); - si_cp_dma_clear_buffer(sctx, &sctx->gfx_cs, src, 12, 4, 0xfedcba98, SI_OP_SYNC_BEFORE_AFTER, - SI_COHERENCY_SHADER, L2_BYPASS); - si_cp_dma_clear_buffer(sctx, &sctx->gfx_cs, dst, 0, 16, 0xdeadbeef, SI_OP_SYNC_BEFORE_AFTER, - SI_COHERENCY_SHADER, L2_BYPASS); - - si_cp_dma_copy_buffer(sctx, NULL, src, offset, 0, 16, SI_OP_SYNC_BEFORE_AFTER, - SI_COHERENCY_NONE, L2_BYPASS); - si_cp_dma_copy_buffer(sctx, dst, NULL, 0, offset, 16, SI_OP_SYNC_BEFORE_AFTER, - SI_COHERENCY_NONE, L2_BYPASS); - - pipe_buffer_read(ctx, dst, 0, sizeof(r), r); - printf("GDS copy = %08x %08x %08x %08x -> %s\n", r[0], r[1], r[2], r[3], - r[0] == 0xabcdef01 && r[1] == 0x23456789 && r[2] == 0x87654321 && r[3] == 0xfedcba98 - ? "pass" - : "fail"); - - si_cp_dma_clear_buffer(sctx, &sctx->gfx_cs, NULL, offset, 16, 0xc1ea4146, - SI_OP_SYNC_BEFORE_AFTER, SI_COHERENCY_NONE, L2_BYPASS); - si_cp_dma_copy_buffer(sctx, dst, NULL, 0, offset, 16, SI_OP_SYNC_BEFORE_AFTER, - SI_COHERENCY_NONE, L2_BYPASS); - - pipe_buffer_read(ctx, dst, 0, sizeof(r), r); - printf("GDS clear = %08x %08x %08x %08x -> %s\n", r[0], r[1], r[2], r[3], - r[0] == 0xc1ea4146 && r[1] == 0xc1ea4146 && r[2] == 0xc1ea4146 && r[3] == 0xc1ea4146 - ? "pass" - : "fail"); - - pipe_resource_reference(&src, NULL); - pipe_resource_reference(&dst, NULL); - exit(0); -} - void si_cp_write_data(struct si_context *sctx, struct si_resource *buf, unsigned offset, unsigned size, unsigned dst_sel, unsigned engine, const void *data) { diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index d07a84de238..f383dc25536 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -126,9 +126,6 @@ static const struct debug_named_value test_options[] = { {"testvmfaultcp", DBG(TEST_VMFAULT_CP), "Invoke a CP VM fault test and exit."}, {"testvmfaultshader", DBG(TEST_VMFAULT_SHADER), "Invoke a shader VM fault test and exit."}, {"testdmaperf", DBG(TEST_DMA_PERF), "Test DMA performance"}, - {"testgds", DBG(TEST_GDS), "Test GDS."}, - {"testgdsmm", DBG(TEST_GDS_MM), "Test GDS memory management."}, - {"testgdsoamm", DBG(TEST_GDS_OA_MM), "Test GDS OA memory management."}, DEBUG_NAMED_VALUE_END /* must be last */ }; @@ -1089,38 +1086,6 @@ static void si_test_vmfault(struct si_screen *sscreen, uint64_t test_flags) exit(0); } -static void si_test_gds_memory_management(struct si_context *sctx, unsigned alloc_size, - unsigned alignment, enum radeon_bo_domain domain) -{ - struct radeon_winsys *ws = sctx->ws; - struct radeon_cmdbuf cs[8]; - struct pb_buffer_lean *gds_bo[ARRAY_SIZE(cs)]; - - for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) { - ws->cs_create(&cs[i], sctx->ctx, AMD_IP_COMPUTE, NULL, NULL); - gds_bo[i] = ws->buffer_create(ws, alloc_size, alignment, domain, 0); - assert(gds_bo[i]); - } - - for (unsigned iterations = 0; iterations < 20000; iterations++) { - for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) { - /* This clears GDS with CP DMA. - * - * We don't care if GDS is present. Just add some packet - * to make the GPU busy for a moment. - */ - si_cp_dma_clear_buffer( - sctx, &cs[i], NULL, 0, alloc_size, 0, - SI_OP_CPDMA_SKIP_CHECK_CS_SPACE, 0, - 0); - - ws->cs_add_buffer(&cs[i], gds_bo[i], RADEON_USAGE_READWRITE, domain); - ws->cs_flush(&cs[i], PIPE_FLUSH_ASYNC, NULL); - } - } - exit(0); -} - static void si_disk_cache_create(struct si_screen *sscreen) { /* Don't use the cache if shader dumping is enabled. */ @@ -1540,20 +1505,6 @@ static struct pipe_screen *radeonsi_screen_create_impl(struct radeon_winsys *ws, if (test_flags & (DBG(TEST_VMFAULT_CP) | DBG(TEST_VMFAULT_SHADER))) si_test_vmfault(sscreen, test_flags); - if (sscreen->info.gfx_level < GFX12) { - if (test_flags & DBG(TEST_GDS)) - si_test_gds((struct si_context *)sscreen->aux_context.general.ctx); - - if (test_flags & DBG(TEST_GDS_MM)) { - si_test_gds_memory_management((struct si_context *)sscreen->aux_context.general.ctx, - 32 * 1024, 4, RADEON_DOMAIN_GDS); - } - if (test_flags & DBG(TEST_GDS_OA_MM)) { - si_test_gds_memory_management((struct si_context *)sscreen->aux_context.general.ctx, - 4, 1, RADEON_DOMAIN_OA); - } - } - ac_print_nonshadowed_regs(sscreen->info.gfx_level, sscreen->info.family); return &sscreen->b; diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index 1b54fbab4b8..bbe7ae1005f 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -269,9 +269,6 @@ enum DBG_TEST_VMFAULT_CP, DBG_TEST_VMFAULT_SHADER, DBG_TEST_DMA_PERF, - DBG_TEST_GDS, - DBG_TEST_GDS_MM, - DBG_TEST_GDS_OA_MM, }; #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1)) @@ -1595,7 +1592,6 @@ void si_cp_dma_copy_buffer(struct si_context *sctx, struct pipe_resource *dst, struct pipe_resource *src, uint64_t dst_offset, uint64_t src_offset, unsigned size, unsigned user_flags, enum si_coherency coher, enum si_cache_policy cache_policy); -void si_test_gds(struct si_context *sctx); void si_cp_write_data(struct si_context *sctx, struct si_resource *buf, unsigned offset, unsigned size, unsigned dst_sel, unsigned engine, const void *data); void si_cp_copy_data(struct si_context *sctx, struct radeon_cmdbuf *cs, unsigned dst_sel,