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panfrost: Prepare things for the common/JM cmdstream split
In order to be able to split the code into separate files, we need to share some common definitions. Create a pan_cmdstream.h file containing some structs and helpers. This file is meant to be included from per-gen source files. Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26249>
This commit is contained in:
Boris Brezillon
Marge Bot
parent
635385a807
commit
5e5a766a81
2 changed files with 321 additions and 274 deletions
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@ -46,6 +46,7 @@
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#include "pan_blend.h"
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#include "pan_blitter.h"
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#include "pan_bo.h"
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#include "pan_cmdstream.h"
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#include "pan_context.h"
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#include "pan_indirect_dispatch.h"
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#include "pan_job.h"
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@ -54,43 +55,6 @@
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#include "pan_texture.h"
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#include "pan_util.h"
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#define PAN_GPU_INDIRECTS (PAN_ARCH == 7)
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struct panfrost_rasterizer {
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struct pipe_rasterizer_state base;
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#if PAN_ARCH <= 7
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/* Partially packed RSD words */
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struct mali_multisample_misc_packed multisample;
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struct mali_stencil_mask_misc_packed stencil_misc;
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#endif
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};
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struct panfrost_zsa_state {
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struct pipe_depth_stencil_alpha_state base;
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/* Is any depth, stencil, or alpha testing enabled? */
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bool enabled;
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/* Does the depth and stencil tests always pass? This ignores write
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* masks, we are only interested in whether pixels may be killed.
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*/
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bool zs_always_passes;
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/* Are depth or stencil writes possible? */
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bool writes_zs;
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#if PAN_ARCH <= 7
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/* Prepacked words from the RSD */
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struct mali_multisample_misc_packed rsd_depth;
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struct mali_stencil_mask_misc_packed rsd_stencil;
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struct mali_stencil_packed stencil_front, stencil_back;
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#else
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/* Depth/stencil descriptor template */
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struct mali_depth_stencil_packed desc;
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#endif
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};
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struct panfrost_sampler_state {
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struct pipe_sampler_state base;
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struct mali_sampler_packed hw;
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@ -112,25 +76,6 @@ struct panfrost_sampler_view {
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struct panfrost_pool *pool;
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};
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struct panfrost_vertex_state {
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unsigned num_elements;
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struct pipe_vertex_element pipe[PIPE_MAX_ATTRIBS];
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uint16_t strides[PIPE_MAX_ATTRIBS];
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#if PAN_ARCH >= 9
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/* Packed attribute descriptors */
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struct mali_attribute_packed attributes[PIPE_MAX_ATTRIBS];
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#else
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/* buffers corresponds to attribute buffer, element_buffers corresponds
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* to an index in buffers for each vertex element */
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struct pan_vertex_buffer buffers[PIPE_MAX_ATTRIBS];
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unsigned element_buffer[PIPE_MAX_ATTRIBS];
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unsigned nr_bufs;
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unsigned formats[PIPE_MAX_ATTRIBS];
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#endif
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};
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/* Statically assert that PIPE_* enums match the hardware enums.
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* (As long as they match, we don't need to translate them.)
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*/
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@ -291,35 +236,6 @@ panfrost_create_sampler_state(struct pipe_context *pctx,
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return so;
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}
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static bool
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panfrost_fs_required(struct panfrost_compiled_shader *fs,
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struct panfrost_blend_state *blend,
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struct pipe_framebuffer_state *state,
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const struct panfrost_zsa_state *zsa)
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{
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/* If we generally have side effects. This inclues use of discard,
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* which can affect the results of an occlusion query. */
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if (fs->info.fs.sidefx)
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return true;
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/* Using an empty FS requires early-z to be enabled, but alpha test
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* needs it disabled. Alpha test is only native on Midgard, so only
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* check there.
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*/
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if (PAN_ARCH <= 5 && zsa->base.alpha_func != PIPE_FUNC_ALWAYS)
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return true;
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/* If colour is written we need to execute */
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for (unsigned i = 0; i < state->nr_cbufs; ++i) {
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if (state->cbufs[i] && blend->info[i].enabled)
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return true;
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}
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/* If depth is written and not implied we need to execute.
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* TODO: Predicate on Z/S writes being enabled */
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return (fs->info.fs.writes_depth || fs->info.fs.writes_stencil);
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}
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/* Get pointers to the blend shaders bound to each active render target. Used
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* to emit the blend descriptors, as well as the fragment renderer state
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* descriptor.
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@ -358,34 +274,6 @@ pack_blend_constant(enum pipe_format format, float cons)
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return unorm << (16 - chan_size);
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}
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/*
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* Determine whether to set the respective overdraw alpha flag.
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*
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* The overdraw alpha=1 flag should be set when alpha=1 implies full overdraw,
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* equivalently, all enabled render targets have alpha_one_store set. Likewise,
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* overdraw alpha=0 should be set when alpha=0 implies no overdraw,
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* equivalently, all enabled render targets have alpha_zero_nop set.
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*/
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#if PAN_ARCH >= 6
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static bool
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panfrost_overdraw_alpha(const struct panfrost_context *ctx, bool zero)
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{
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const struct panfrost_blend_state *so = ctx->blend;
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for (unsigned i = 0; i < ctx->pipe_framebuffer.nr_cbufs; ++i) {
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const struct pan_blend_info info = so->info[i];
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bool enabled = ctx->pipe_framebuffer.cbufs[i] && !info.enabled;
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bool flag = zero ? info.alpha_zero_nop : info.alpha_one_store;
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if (enabled && !flag)
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return false;
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}
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return true;
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}
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#endif
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static void
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panfrost_emit_blend(struct panfrost_batch *batch, void *rts,
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mali_ptr *blend_shaders)
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@ -499,23 +387,6 @@ panfrost_emit_blend(struct panfrost_batch *batch, void *rts,
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}
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#endif
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static inline bool
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pan_allow_forward_pixel_to_kill(struct panfrost_context *ctx,
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struct panfrost_compiled_shader *fs)
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{
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/* Track if any colour buffer is reused across draws, either
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* from reading it directly, or from failing to write it
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*/
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unsigned rt_mask = ctx->fb_rt_mask;
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uint64_t rt_written = (fs->info.outputs_written >> FRAG_RESULT_DATA0) &
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ctx->blend->enabled_mask;
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bool blend_reads_dest = (ctx->blend->load_dest_mask & rt_mask);
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bool alpha_to_coverage = ctx->blend->base.alpha_to_coverage;
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return fs->info.fs.can_fpk && !(rt_mask & ~rt_written) &&
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!alpha_to_coverage && !blend_reads_dest;
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}
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static mali_ptr
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panfrost_emit_compute_shader_meta(struct panfrost_batch *batch,
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enum pipe_shader_type stage)
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@ -2688,34 +2559,6 @@ emit_fragment_job(struct panfrost_batch *batch, const struct pan_fb_info *pfb)
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jm_emit_fragment_job(batch, pfb);
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}
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#define DEFINE_CASE(c) \
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case MESA_PRIM_##c: \
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return MALI_DRAW_MODE_##c;
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static uint8_t
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pan_draw_mode(enum mesa_prim mode)
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{
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switch (mode) {
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DEFINE_CASE(POINTS);
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DEFINE_CASE(LINES);
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DEFINE_CASE(LINE_LOOP);
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DEFINE_CASE(LINE_STRIP);
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DEFINE_CASE(TRIANGLES);
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DEFINE_CASE(TRIANGLE_STRIP);
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DEFINE_CASE(TRIANGLE_FAN);
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DEFINE_CASE(QUADS);
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DEFINE_CASE(POLYGON);
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#if PAN_ARCH <= 6
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DEFINE_CASE(QUAD_STRIP);
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#endif
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default:
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unreachable("Invalid draw mode");
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}
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}
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#undef DEFINE_CASE
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/* Count generated primitives (when there is no geom/tess shaders) for
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* transform feedback */
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@ -2751,16 +2594,6 @@ panfrost_update_streamout_offsets(struct panfrost_context *ctx)
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}
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}
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static inline enum mali_index_type
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panfrost_translate_index_size(unsigned size)
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{
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STATIC_ASSERT(MALI_INDEX_TYPE_NONE == 0);
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STATIC_ASSERT(MALI_INDEX_TYPE_UINT8 == 1);
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STATIC_ASSERT(MALI_INDEX_TYPE_UINT16 == 2);
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return (size == 4) ? MALI_INDEX_TYPE_UINT32 : size;
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}
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#if PAN_ARCH <= 7
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static inline void
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jm_emit_draw_descs(struct panfrost_batch *batch, struct MALI_DRAW *d,
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@ -2807,30 +2640,6 @@ jm_emit_vertex_job(struct panfrost_batch *batch,
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}
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#endif
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static void
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panfrost_emit_primitive_size(struct panfrost_context *ctx, bool points,
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mali_ptr size_array, void *prim_size)
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{
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struct panfrost_rasterizer *rast = ctx->rasterizer;
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pan_pack(prim_size, PRIMITIVE_SIZE, cfg) {
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if (panfrost_writes_point_size(ctx)) {
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cfg.size_array = size_array;
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} else {
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cfg.constant = points ? rast->base.point_size : rast->base.line_width;
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}
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}
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}
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static bool
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panfrost_is_implicit_prim_restart(const struct pipe_draw_info *info)
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{
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/* As a reminder primitive_restart should always be checked before any
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access to restart_index. */
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return info->primitive_restart &&
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info->restart_index == (unsigned)BITFIELD_MASK(info->index_size * 8);
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}
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/* On Bifrost and older, the Renderer State Descriptor aggregates many pieces of
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* 3D state. In particular, it groups the fragment shader descriptor with
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* depth/stencil, blend, polygon offset, and multisampling state. These pieces
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@ -3002,14 +2811,6 @@ jm_emit_tiler_desc(struct panfrost_batch *batch)
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}
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#endif
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static bool
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allow_rotating_primitives(const struct panfrost_compiled_shader *fs,
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const struct pipe_draw_info *info)
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{
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return u_reduced_prim(info->mode) != MESA_PRIM_LINES &&
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!fs->info.bifrost.uses_flat_shading;
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}
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/* Packs a primitive descriptor, mostly common between Midgard/Bifrost tiler
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* jobs and Valhall IDVS jobs
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*/
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@ -3086,47 +2887,6 @@ jm_emit_primitive(struct panfrost_batch *batch,
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}
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#if PAN_ARCH >= 9
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static mali_ptr
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panfrost_emit_resources(struct panfrost_batch *batch,
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enum pipe_shader_type stage)
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{
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struct panfrost_context *ctx = batch->ctx;
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struct panfrost_ptr T;
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unsigned nr_tables = 12;
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/* Although individual resources need only 16 byte alignment, the
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* resource table as a whole must be 64-byte aligned.
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*/
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T = pan_pool_alloc_aligned(&batch->pool.base, nr_tables * pan_size(RESOURCE),
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64);
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memset(T.cpu, 0, nr_tables * pan_size(RESOURCE));
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panfrost_make_resource_table(T, PAN_TABLE_UBO, batch->uniform_buffers[stage],
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batch->nr_uniform_buffers[stage]);
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panfrost_make_resource_table(T, PAN_TABLE_TEXTURE, batch->textures[stage],
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ctx->sampler_view_count[stage]);
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/* We always need at least 1 sampler for txf to work */
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panfrost_make_resource_table(T, PAN_TABLE_SAMPLER, batch->samplers[stage],
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MAX2(ctx->sampler_count[stage], 1));
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panfrost_make_resource_table(T, PAN_TABLE_IMAGE, batch->images[stage],
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util_last_bit(ctx->image_mask[stage]));
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if (stage == PIPE_SHADER_VERTEX) {
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panfrost_make_resource_table(T, PAN_TABLE_ATTRIBUTE,
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batch->attribs[stage],
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ctx->vertex->num_elements);
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panfrost_make_resource_table(T, PAN_TABLE_ATTRIBUTE_BUFFER,
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batch->attrib_bufs[stage],
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util_last_bit(ctx->vb_mask));
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}
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return T.gpu | nr_tables;
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}
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static void
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jm_emit_shader_env(struct panfrost_batch *batch,
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struct MALI_SHADER_ENVIRONMENT *cfg,
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@ -3297,39 +3057,6 @@ jm_emit_tiler_draw(void *out, struct panfrost_batch *batch, bool fs_required,
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}
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#if PAN_ARCH >= 9
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static mali_ptr
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panfrost_get_position_shader(struct panfrost_batch *batch,
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const struct pipe_draw_info *info)
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{
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/* IDVS/points vertex shader */
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mali_ptr vs_ptr = batch->rsd[PIPE_SHADER_VERTEX];
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/* IDVS/triangle vertex shader */
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if (vs_ptr && info->mode != MESA_PRIM_POINTS)
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vs_ptr += pan_size(SHADER_PROGRAM);
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return vs_ptr;
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}
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static mali_ptr
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panfrost_get_varying_shader(struct panfrost_batch *batch)
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{
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return batch->rsd[PIPE_SHADER_VERTEX] + (2 * pan_size(SHADER_PROGRAM));
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}
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static unsigned
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panfrost_vertex_attribute_stride(struct panfrost_compiled_shader *vs,
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struct panfrost_compiled_shader *fs)
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{
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unsigned v = vs->info.varyings.output_count;
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unsigned f = fs->info.varyings.input_count;
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unsigned slots = MAX2(v, f);
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slots += util_bitcount(fs->key.fs.fixed_varying_mask);
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/* Assumes 16 byte slots. We could do better. */
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return slots * 16;
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}
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static void
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jm_emit_malloc_vertex_job(struct panfrost_batch *batch,
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const struct pipe_draw_info *info,
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320
src/gallium/drivers/panfrost/pan_cmdstream.h
Normal file
320
src/gallium/drivers/panfrost/pan_cmdstream.h
Normal file
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@ -0,0 +1,320 @@
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/*
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* Copyright (C) 2018 Alyssa Rosenzweig
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* Copyright (C) 2020 Collabora Ltd.
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* Copyright © 2017 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef __PAN_CMDSTREAM_H__
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#define __PAN_CMDSTREAM_H__
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#ifndef PAN_ARCH
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#error "PAN_ARCH undefined!"
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#endif
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#include "genxml/gen_macros.h"
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#include "pan_context.h"
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#include "pan_job.h"
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#include "pipe/p_defines.h"
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#include "pipe/p_state.h"
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#include "util/u_prim.h"
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#define PAN_GPU_INDIRECTS (PAN_ARCH == 7)
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struct panfrost_rasterizer {
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struct pipe_rasterizer_state base;
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#if PAN_ARCH <= 7
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/* Partially packed RSD words */
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struct mali_multisample_misc_packed multisample;
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struct mali_stencil_mask_misc_packed stencil_misc;
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#endif
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};
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struct panfrost_zsa_state {
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struct pipe_depth_stencil_alpha_state base;
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/* Is any depth, stencil, or alpha testing enabled? */
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bool enabled;
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/* Does the depth and stencil tests always pass? This ignores write
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* masks, we are only interested in whether pixels may be killed.
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*/
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bool zs_always_passes;
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/* Are depth or stencil writes possible? */
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bool writes_zs;
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#if PAN_ARCH <= 7
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/* Prepacked words from the RSD */
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struct mali_multisample_misc_packed rsd_depth;
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struct mali_stencil_mask_misc_packed rsd_stencil;
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struct mali_stencil_packed stencil_front, stencil_back;
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#else
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/* Depth/stencil descriptor template */
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struct mali_depth_stencil_packed desc;
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#endif
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};
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struct panfrost_vertex_state {
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unsigned num_elements;
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struct pipe_vertex_element pipe[PIPE_MAX_ATTRIBS];
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uint16_t strides[PIPE_MAX_ATTRIBS];
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#if PAN_ARCH >= 9
|
||||
/* Packed attribute descriptors */
|
||||
struct mali_attribute_packed attributes[PIPE_MAX_ATTRIBS];
|
||||
#else
|
||||
/* buffers corresponds to attribute buffer, element_buffers corresponds
|
||||
* to an index in buffers for each vertex element */
|
||||
struct pan_vertex_buffer buffers[PIPE_MAX_ATTRIBS];
|
||||
unsigned element_buffer[PIPE_MAX_ATTRIBS];
|
||||
unsigned nr_bufs;
|
||||
|
||||
unsigned formats[PIPE_MAX_ATTRIBS];
|
||||
#endif
|
||||
};
|
||||
|
||||
static inline bool
|
||||
panfrost_is_implicit_prim_restart(const struct pipe_draw_info *info)
|
||||
{
|
||||
/* As a reminder primitive_restart should always be checked before any
|
||||
access to restart_index. */
|
||||
return info->primitive_restart &&
|
||||
info->restart_index == (unsigned)BITFIELD_MASK(info->index_size * 8);
|
||||
}
|
||||
|
||||
static inline bool
|
||||
pan_allow_forward_pixel_to_kill(struct panfrost_context *ctx,
|
||||
struct panfrost_compiled_shader *fs)
|
||||
{
|
||||
/* Track if any colour buffer is reused across draws, either
|
||||
* from reading it directly, or from failing to write it
|
||||
*/
|
||||
unsigned rt_mask = ctx->fb_rt_mask;
|
||||
uint64_t rt_written = (fs->info.outputs_written >> FRAG_RESULT_DATA0) &
|
||||
ctx->blend->enabled_mask;
|
||||
bool blend_reads_dest = (ctx->blend->load_dest_mask & rt_mask);
|
||||
bool alpha_to_coverage = ctx->blend->base.alpha_to_coverage;
|
||||
|
||||
return fs->info.fs.can_fpk && !(rt_mask & ~rt_written) &&
|
||||
!alpha_to_coverage && !blend_reads_dest;
|
||||
}
|
||||
|
||||
/*
|
||||
* Determine whether to set the respective overdraw alpha flag.
|
||||
*
|
||||
* The overdraw alpha=1 flag should be set when alpha=1 implies full overdraw,
|
||||
* equivalently, all enabled render targets have alpha_one_store set. Likewise,
|
||||
* overdraw alpha=0 should be set when alpha=0 implies no overdraw,
|
||||
* equivalently, all enabled render targets have alpha_zero_nop set.
|
||||
*/
|
||||
#if PAN_ARCH >= 6
|
||||
static inline bool
|
||||
panfrost_overdraw_alpha(const struct panfrost_context *ctx, bool zero)
|
||||
{
|
||||
const struct panfrost_blend_state *so = ctx->blend;
|
||||
|
||||
for (unsigned i = 0; i < ctx->pipe_framebuffer.nr_cbufs; ++i) {
|
||||
const struct pan_blend_info info = so->info[i];
|
||||
|
||||
bool enabled = ctx->pipe_framebuffer.cbufs[i] && !info.enabled;
|
||||
bool flag = zero ? info.alpha_zero_nop : info.alpha_one_store;
|
||||
|
||||
if (enabled && !flag)
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
#endif
|
||||
|
||||
static inline void
|
||||
panfrost_emit_primitive_size(struct panfrost_context *ctx, bool points,
|
||||
mali_ptr size_array, void *prim_size)
|
||||
{
|
||||
struct panfrost_rasterizer *rast = ctx->rasterizer;
|
||||
|
||||
pan_pack(prim_size, PRIMITIVE_SIZE, cfg) {
|
||||
if (panfrost_writes_point_size(ctx)) {
|
||||
cfg.size_array = size_array;
|
||||
} else {
|
||||
cfg.constant = points ? rast->base.point_size : rast->base.line_width;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static inline uint8_t
|
||||
pan_draw_mode(enum mesa_prim mode)
|
||||
{
|
||||
switch (mode) {
|
||||
|
||||
#define DEFINE_CASE(c) \
|
||||
case MESA_PRIM_##c: \
|
||||
return MALI_DRAW_MODE_##c;
|
||||
|
||||
DEFINE_CASE(POINTS);
|
||||
DEFINE_CASE(LINES);
|
||||
DEFINE_CASE(LINE_LOOP);
|
||||
DEFINE_CASE(LINE_STRIP);
|
||||
DEFINE_CASE(TRIANGLES);
|
||||
DEFINE_CASE(TRIANGLE_STRIP);
|
||||
DEFINE_CASE(TRIANGLE_FAN);
|
||||
DEFINE_CASE(QUADS);
|
||||
DEFINE_CASE(POLYGON);
|
||||
#if PAN_ARCH <= 6
|
||||
DEFINE_CASE(QUAD_STRIP);
|
||||
#endif
|
||||
|
||||
#undef DEFINE_CASE
|
||||
|
||||
default:
|
||||
unreachable("Invalid draw mode");
|
||||
}
|
||||
}
|
||||
|
||||
static inline enum mali_index_type
|
||||
panfrost_translate_index_size(unsigned size)
|
||||
{
|
||||
STATIC_ASSERT(MALI_INDEX_TYPE_NONE == 0);
|
||||
STATIC_ASSERT(MALI_INDEX_TYPE_UINT8 == 1);
|
||||
STATIC_ASSERT(MALI_INDEX_TYPE_UINT16 == 2);
|
||||
|
||||
return (size == 4) ? MALI_INDEX_TYPE_UINT32 : size;
|
||||
}
|
||||
|
||||
static inline bool
|
||||
panfrost_fs_required(struct panfrost_compiled_shader *fs,
|
||||
struct panfrost_blend_state *blend,
|
||||
struct pipe_framebuffer_state *state,
|
||||
const struct panfrost_zsa_state *zsa)
|
||||
{
|
||||
/* If we generally have side effects. This inclues use of discard,
|
||||
* which can affect the results of an occlusion query. */
|
||||
if (fs->info.fs.sidefx)
|
||||
return true;
|
||||
|
||||
/* Using an empty FS requires early-z to be enabled, but alpha test
|
||||
* needs it disabled. Alpha test is only native on Midgard, so only
|
||||
* check there.
|
||||
*/
|
||||
if (PAN_ARCH <= 5 && zsa->base.alpha_func != PIPE_FUNC_ALWAYS)
|
||||
return true;
|
||||
|
||||
/* If colour is written we need to execute */
|
||||
for (unsigned i = 0; i < state->nr_cbufs; ++i) {
|
||||
if (state->cbufs[i] && blend->info[i].enabled)
|
||||
return true;
|
||||
}
|
||||
|
||||
/* If depth is written and not implied we need to execute.
|
||||
* TODO: Predicate on Z/S writes being enabled */
|
||||
return (fs->info.fs.writes_depth || fs->info.fs.writes_stencil);
|
||||
}
|
||||
|
||||
#if PAN_ARCH >= 9
|
||||
static inline mali_ptr
|
||||
panfrost_get_position_shader(struct panfrost_batch *batch,
|
||||
const struct pipe_draw_info *info)
|
||||
{
|
||||
/* IDVS/points vertex shader */
|
||||
mali_ptr vs_ptr = batch->rsd[PIPE_SHADER_VERTEX];
|
||||
|
||||
/* IDVS/triangle vertex shader */
|
||||
if (vs_ptr && info->mode != MESA_PRIM_POINTS)
|
||||
vs_ptr += pan_size(SHADER_PROGRAM);
|
||||
|
||||
return vs_ptr;
|
||||
}
|
||||
|
||||
static inline mali_ptr
|
||||
panfrost_get_varying_shader(struct panfrost_batch *batch)
|
||||
{
|
||||
return batch->rsd[PIPE_SHADER_VERTEX] + (2 * pan_size(SHADER_PROGRAM));
|
||||
}
|
||||
|
||||
static inline unsigned
|
||||
panfrost_vertex_attribute_stride(struct panfrost_compiled_shader *vs,
|
||||
struct panfrost_compiled_shader *fs)
|
||||
{
|
||||
unsigned v = vs->info.varyings.output_count;
|
||||
unsigned f = fs->info.varyings.input_count;
|
||||
unsigned slots = MAX2(v, f);
|
||||
slots += util_bitcount(fs->key.fs.fixed_varying_mask);
|
||||
|
||||
/* Assumes 16 byte slots. We could do better. */
|
||||
return slots * 16;
|
||||
}
|
||||
|
||||
static inline mali_ptr
|
||||
panfrost_emit_resources(struct panfrost_batch *batch,
|
||||
enum pipe_shader_type stage)
|
||||
{
|
||||
struct panfrost_context *ctx = batch->ctx;
|
||||
struct panfrost_ptr T;
|
||||
unsigned nr_tables = 12;
|
||||
|
||||
/* Although individual resources need only 16 byte alignment, the
|
||||
* resource table as a whole must be 64-byte aligned.
|
||||
*/
|
||||
T = pan_pool_alloc_aligned(&batch->pool.base, nr_tables * pan_size(RESOURCE),
|
||||
64);
|
||||
memset(T.cpu, 0, nr_tables * pan_size(RESOURCE));
|
||||
|
||||
panfrost_make_resource_table(T, PAN_TABLE_UBO, batch->uniform_buffers[stage],
|
||||
batch->nr_uniform_buffers[stage]);
|
||||
|
||||
panfrost_make_resource_table(T, PAN_TABLE_TEXTURE, batch->textures[stage],
|
||||
ctx->sampler_view_count[stage]);
|
||||
|
||||
/* We always need at least 1 sampler for txf to work */
|
||||
panfrost_make_resource_table(T, PAN_TABLE_SAMPLER, batch->samplers[stage],
|
||||
MAX2(ctx->sampler_count[stage], 1));
|
||||
|
||||
panfrost_make_resource_table(T, PAN_TABLE_IMAGE, batch->images[stage],
|
||||
util_last_bit(ctx->image_mask[stage]));
|
||||
|
||||
if (stage == PIPE_SHADER_VERTEX) {
|
||||
panfrost_make_resource_table(T, PAN_TABLE_ATTRIBUTE,
|
||||
batch->attribs[stage],
|
||||
ctx->vertex->num_elements);
|
||||
|
||||
panfrost_make_resource_table(T, PAN_TABLE_ATTRIBUTE_BUFFER,
|
||||
batch->attrib_bufs[stage],
|
||||
util_last_bit(ctx->vb_mask));
|
||||
}
|
||||
|
||||
return T.gpu | nr_tables;
|
||||
}
|
||||
#endif /* PAN_ARCH >= 9 */
|
||||
|
||||
static bool
|
||||
allow_rotating_primitives(const struct panfrost_compiled_shader *fs,
|
||||
const struct pipe_draw_info *info)
|
||||
{
|
||||
return u_reduced_prim(info->mode) != MESA_PRIM_LINES &&
|
||||
!fs->info.bifrost.uses_flat_shading;
|
||||
}
|
||||
|
||||
#endif
|
||||
Loading…
Add table
Reference in a new issue