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https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-05-01 08:08:06 +02:00
nv30: Add separate nv30 state stuff for fb, based on nv40 one, need to use it now
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parent
d785a0c8b2
commit
5e1d657d50
3 changed files with 170 additions and 0 deletions
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@ -14,6 +14,7 @@ DRIVER_SOURCES = \
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nv30_screen.c \
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nv30_state.c \
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nv30_state_emit.c \
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nv30_state_fb.c \
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nv30_surface.c \
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nv30_vbo.c \
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nv30_vertprog.c
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@ -76,6 +76,10 @@ enum nv30_state_index {
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#define NV30_NEW_ARRAYS (1 << 11)
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#define NV30_NEW_UCP (1 << 12)
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struct nv30_state {
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struct nouveau_stateobj *hw[NV30_STATE_MAX];
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};
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struct nv30_context {
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struct pipe_context pipe;
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@ -85,6 +89,9 @@ struct nv30_context {
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struct draw_context *draw;
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/* HW state derived from pipe states */
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struct nv30_state state;
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uint32_t dirty;
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struct nv30_sampler_state *tex_sampler[PIPE_MAX_SAMPLERS];
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@ -93,6 +100,9 @@ struct nv30_context {
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unsigned fp_samplers;
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unsigned vp_samplers;
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/* Context state */
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struct pipe_framebuffer_state framebuffer;
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uint32_t rt_enable;
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struct pipe_buffer *rt[2];
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struct pipe_buffer *zeta;
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@ -132,6 +142,14 @@ nv30_context(struct pipe_context *pipe)
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return (struct nv30_context *)pipe;
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}
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struct nv30_state_entry {
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boolean (*validate)(struct nv30_context *nv30);
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struct {
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unsigned pipe;
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unsigned hw;
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} dirty;
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};
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extern void nv30_init_state_functions(struct nv30_context *nv30);
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extern void nv30_init_surface_functions(struct nv30_context *nv30);
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extern void nv30_init_query_functions(struct nv30_context *nv30);
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151
src/gallium/drivers/nv30/nv30_state_fb.c
Normal file
151
src/gallium/drivers/nv30/nv30_state_fb.c
Normal file
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@ -0,0 +1,151 @@
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#include "nv30_context.h"
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static boolean
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nv30_state_framebuffer_validate(struct nv30_context *nv30)
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{
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struct pipe_framebuffer_state *fb = &nv30->framebuffer;
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struct pipe_surface *rt[4], *zeta = NULL;
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uint32_t rt_enable, rt_format;
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int i, colour_format = 0, zeta_format = 0;
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struct nouveau_stateobj *so = so_new(64, 10);
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unsigned rt_flags = NOUVEAU_BO_RDWR | NOUVEAU_BO_VRAM;
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unsigned w = fb->width;
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unsigned h = fb->height;
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rt_enable = 0;
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for (i = 0; i < fb->num_cbufs; i++) {
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if (colour_format) {
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assert(colour_format == fb->cbufs[i]->format);
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} else {
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colour_format = fb->cbufs[i]->format;
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rt_enable |= (NV34TCL_RT_ENABLE_COLOR0 << i);
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rt[i] = fb->cbufs[i];
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}
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}
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if (rt_enable & (NV34TCL_RT_ENABLE_COLOR1 | NV34TCL_RT_ENABLE_COLOR2 |
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NV34TCL_RT_ENABLE_COLOR3))
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rt_enable |= NV34TCL_RT_ENABLE_MRT;
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if (fb->zsbuf) {
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zeta_format = fb->zsbuf->format;
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zeta = fb->zsbuf;
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}
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rt_format = NV34TCL_RT_FORMAT_TYPE_LINEAR;
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switch (colour_format) {
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case PIPE_FORMAT_A8R8G8B8_UNORM:
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case 0:
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rt_format |= NV34TCL_RT_FORMAT_COLOR_A8R8G8B8;
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break;
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case PIPE_FORMAT_R5G6B5_UNORM:
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rt_format |= NV34TCL_RT_FORMAT_COLOR_R5G6B5;
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break;
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default:
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assert(0);
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}
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switch (zeta_format) {
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case PIPE_FORMAT_Z16_UNORM:
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rt_format |= NV34TCL_RT_FORMAT_ZETA_Z16;
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break;
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case PIPE_FORMAT_Z24S8_UNORM:
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case 0:
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rt_format |= NV34TCL_RT_FORMAT_ZETA_Z24S8;
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break;
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default:
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assert(0);
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}
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if (rt_enable & NV34TCL_RT_ENABLE_COLOR0) {
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uint32_t pitch = rt[0]->pitch * rt[0]->cpp;
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if (zeta) {
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pitch |= (zeta->pitch * zeta->cpp)<<16;
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} else {
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pitch |= pitch<<16;
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}
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so_method(so, nv30->screen->rankine, NV34TCL_DMA_COLOR0, 1);
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so_reloc (so, rt[0]->buffer, 0, rt_flags | NOUVEAU_BO_OR,
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nv30->nvws->channel->vram->handle,
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nv30->nvws->channel->gart->handle);
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so_method(so, nv30->screen->rankine, NV34TCL_COLOR0_PITCH, 2);
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so_data (so, pitch);
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so_reloc (so, rt[0]->buffer, rt[0]->offset, rt_flags |
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NOUVEAU_BO_LOW, 0, 0);
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}
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if (rt_enable & NV34TCL_RT_ENABLE_COLOR1) {
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so_method(so, nv30->screen->rankine, NV34TCL_DMA_COLOR1, 1);
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so_reloc (so, rt[1]->buffer, 0, rt_flags | NOUVEAU_BO_OR,
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nv30->nvws->channel->vram->handle,
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nv30->nvws->channel->gart->handle);
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so_method(so, nv30->screen->rankine, NV34TCL_COLOR1_OFFSET, 2);
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so_reloc (so, rt[1]->buffer, rt[1]->offset, rt_flags |
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NOUVEAU_BO_LOW, 0, 0);
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so_data (so, rt[1]->pitch * rt[1]->cpp);
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}
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/*
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if (rt_enable & NV34TCL_RT_ENABLE_COLOR2) {
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so_method(so, nv30->screen->rankine, NV34TCL_DMA_COLOR2, 1);
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so_reloc (so, rt[2]->buffer, 0, rt_flags | NOUVEAU_BO_OR,
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nv30->nvws->channel->vram->handle,
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nv30->nvws->channel->gart->handle);
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so_method(so, nv30->screen->rankine, NV34TCL_COLOR2_OFFSET, 1);
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so_reloc (so, rt[2]->buffer, rt[2]->offset, rt_flags |
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NOUVEAU_BO_LOW, 0, 0);
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so_method(so, nv30->screen->rankine, NV34TCL_COLOR2_PITCH, 1);
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so_data (so, rt[2]->pitch * rt[2]->cpp);
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}
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if (rt_enable & NV34TCL_RT_ENABLE_COLOR3) {
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so_method(so, nv30->screen->rankine, NV34TCL_DMA_COLOR3, 1);
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so_reloc (so, rt[3]->buffer, 0, rt_flags | NOUVEAU_BO_OR,
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nv30->nvws->channel->vram->handle,
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nv30->nvws->channel->gart->handle);
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so_method(so, nv30->screen->rankine, NV34TCL_COLOR3_OFFSET, 1);
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so_reloc (so, rt[3]->buffer, rt[3]->offset, rt_flags |
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NOUVEAU_BO_LOW, 0, 0);
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so_method(so, nv30->screen->rankine, NV34TCL_COLOR3_PITCH, 1);
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so_data (so, rt[3]->pitch * rt[3]->cpp);
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}
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*/
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if (zeta_format) {
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so_method(so, nv30->screen->rankine, NV34TCL_DMA_ZETA, 1);
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so_reloc (so, zeta->buffer, 0, rt_flags | NOUVEAU_BO_OR,
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nv30->nvws->channel->vram->handle,
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nv30->nvws->channel->gart->handle);
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so_method(so, nv30->screen->rankine, NV34TCL_ZETA_OFFSET, 1);
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so_reloc (so, zeta->buffer, zeta->offset, rt_flags |
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NOUVEAU_BO_LOW, 0, 0);
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/*so_method(so, nv30->screen->rankine, NV34TCL_ZETA_PITCH, 1);
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so_data (so, zeta->pitch * zeta->cpp);*/
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}
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so_method(so, nv30->screen->rankine, NV34TCL_RT_ENABLE, 1);
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so_data (so, rt_enable);
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so_method(so, nv30->screen->rankine, NV34TCL_RT_HORIZ, 3);
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so_data (so, (w << 16) | 0);
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so_data (so, (h << 16) | 0);
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so_data (so, rt_format);
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so_method(so, nv30->screen->rankine, NV34TCL_VIEWPORT_HORIZ, 2);
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so_data (so, (w << 16) | 0);
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so_data (so, (h << 16) | 0);
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so_method(so, nv30->screen->rankine, NV34TCL_VIEWPORT_CLIP_HORIZ(0), 2);
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so_data (so, ((w - 1) << 16) | 0);
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so_data (so, ((h - 1) << 16) | 0);
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so_method(so, nv30->screen->rankine, 0x1d88, 1);
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so_data (so, (1 << 12) | h);
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so_ref(so, &nv30->state.hw[NV30_STATE_FB]);
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return TRUE;
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}
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struct nv30_state_entry nv30_state_framebuffer = {
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.validate = nv30_state_framebuffer_validate,
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.dirty = {
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.pipe = NV30_NEW_FB,
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.hw = NV30_STATE_FB
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}
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};
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