From 5e1ada315c30838b57a78cb7ea4e238a51e7d653 Mon Sep 17 00:00:00 2001 From: Adam Jackson Date: Tue, 5 May 2026 16:15:29 -0400 Subject: [PATCH] i915: improve shader-db stats reporting Report actual instruction counts (alu+tex) instead of program dwords/3, add a separate "alu" field for the 64-instruction bottleneck metric, and fix "temps" to use the actual temp register count instead of util_last_bit (highest register number). Before: "69 inst, 2 tex, 3 tex_indirect, 4 temps, 5 const" After: "21 instructions, 19 alu, 2 tex, 2 tex_indirect, 16 temps, 3 const" Assisted-by: Claude --- src/gallium/drivers/i915/i915_fpc_translate.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/i915/i915_fpc_translate.c b/src/gallium/drivers/i915/i915_fpc_translate.c index b6cfb2a3dfb..f07095ee110 100644 --- a/src/gallium/drivers/i915/i915_fpc_translate.c +++ b/src/gallium/drivers/i915/i915_fpc_translate.c @@ -1032,9 +1032,11 @@ i915_fini_compile(struct i915_context *i915, struct i915_fp_compile *p) if (i915) { util_debug_message( &i915->debug, SHADER_INFO, - "%s shader: %d inst, %d tex, %d tex_indirect, %d temps, %d const", + "%s shader: %d instructions, %d alu, %d tex, %d tex_indirect, " + "%d temps, %d const", _mesa_shader_stage_to_abbrev(MESA_SHADER_FRAGMENT), - (int)program_size, p->nr_tex_insn, p->nr_tex_indirect, + p->nr_alu_insn + p->nr_tex_insn, + p->nr_alu_insn, p->nr_tex_insn, p->nr_tex_indirect, p->shader->info.file_max[TGSI_FILE_TEMPORARY] + 1, ifs->num_constants); }