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tu: Save/restore *_BIN_CONTROL in 3d GMEM store path

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These are normally only set once because it's constant across the entire
renderpass, but they're trashed by the 3d store path because it needs to
store to CCU instead of GMEM. Therefore we need to save/restore them. Do
it in a way compatible with #5181.

Fixes: b157a5d ("tu: Implement non-aligned multisample GMEM STORE_OP_STORE")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17058>
(cherry picked from commit cba6da2b21)
This commit is contained in:
Connor Abbott 2022-06-15 18:39:33 +02:00 • committed by Dylan Baker
parent 74f9873950
commit 5df89bf7bc
2 changed files with 23 additions and 1 deletions
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2
.pick_status.json
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@ -211,7 +211,7 @@
"description": "tu: Save/restore *_BIN_CONTROL in 3d GMEM store path",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": "b157a5d0d68ee8a1b4cb862a56b97bd881841413"
},

22
src/freedreno/vulkan/tu_clear_blit.c
View file

@ -2893,6 +2893,17 @@ store_3d_blit(struct tu_cmd_buffer *cmd,
uint32_t gmem_offset,
uint32_t cpp)
{
/* RB_BIN_CONTROL/GRAS_BIN_CONTROL are normally only set once and they
* aren't set until we know whether we're HW binning or not, and we want to
* avoid a dependence on that here to be able to store attachments before
* the end of the renderpass in the future. Use the scratch space to
* save/restore them dynamically.
*/
tu_cs_emit_pkt7(cs, CP_REG_TO_SCRATCH, 1);
tu_cs_emit(cs, CP_REG_TO_SCRATCH_0_REG(REG_A6XX_RB_BIN_CONTROL) |
CP_REG_TO_SCRATCH_0_SCRATCH(0) |
CP_REG_TO_SCRATCH_0_CNT(1 - 1));
r3d_setup(cmd, cs, format, VK_IMAGE_ASPECT_COLOR_BIT, 0, false,
iview->view.ubwc_enabled, dst_samples);
@ -2924,6 +2935,17 @@ store_3d_blit(struct tu_cmd_buffer *cmd,
* writes to depth images as a color RT, so there's no need to flush depth.
*/
tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_COLOR_TS);
/* Restore RB_BIN_CONTROL/GRAS_BIN_CONTROL saved above. */
tu_cs_emit_pkt7(cs, CP_SCRATCH_TO_REG, 1);
tu_cs_emit(cs, CP_SCRATCH_TO_REG_0_REG(REG_A6XX_RB_BIN_CONTROL) |
CP_SCRATCH_TO_REG_0_SCRATCH(0) |
CP_SCRATCH_TO_REG_0_CNT(1 - 1));
tu_cs_emit_pkt7(cs, CP_SCRATCH_TO_REG, 1);
tu_cs_emit(cs, CP_SCRATCH_TO_REG_0_REG(REG_A6XX_GRAS_BIN_CONTROL) |
CP_SCRATCH_TO_REG_0_SCRATCH(0) |
CP_SCRATCH_TO_REG_0_CNT(1 - 1));
}
void