mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2025-12-21 20:10:14 +01:00
i965/vec4: Rewrite dead code elimination to use live in/out.
Improves 359 shaders by >=10%
114 shaders by >=20%
91 shaders by >=30%
82 shaders by >=40%
22 shaders by >=50%
4 shaders by >=60%
2 shaders by >=80%
total instructions in shared programs: 5845346 -> 5822422 (-0.39%)
instructions in affected programs: 364979 -> 342055 (-6.28%)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Matt Turner
parent
7a5cc789de
commit
5df88c2096
3 changed files with 170 additions and 155 deletions
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@ -103,6 +103,7 @@ i965_FILES = \
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brw_vec4.cpp \
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brw_vec4.cpp \
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brw_vec4_copy_propagation.cpp \
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brw_vec4_copy_propagation.cpp \
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brw_vec4_cse.cpp \
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brw_vec4_cse.cpp \
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brw_vec4_dead_code_eliminate.cpp \
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brw_vec4_generator.cpp \
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brw_vec4_generator.cpp \
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brw_vec4_gs_visitor.cpp \
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brw_vec4_gs_visitor.cpp \
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brw_vec4_live_variables.cpp \
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brw_vec4_live_variables.cpp \
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@ -429,161 +429,6 @@ vec4_visitor::opt_reduce_swizzle()
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return progress;
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return progress;
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}
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}
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static bool
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try_eliminate_instruction(vec4_instruction *inst, int new_writemask,
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const struct brw_context *brw)
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{
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if (inst->has_side_effects())
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return false;
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if (new_writemask == 0) {
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/* Don't dead code eliminate instructions that write to the
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* accumulator as a side-effect. Instead just set the destination
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* to the null register to free it.
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*/
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if (inst->writes_accumulator || inst->writes_flag()) {
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inst->dst = dst_reg(retype(brw_null_reg(), inst->dst.type));
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} else {
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inst->opcode = BRW_OPCODE_NOP;
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}
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return true;
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} else if (inst->dst.writemask != new_writemask) {
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switch (inst->opcode) {
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case SHADER_OPCODE_TXF_CMS:
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case SHADER_OPCODE_GEN4_SCRATCH_READ:
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case VS_OPCODE_PULL_CONSTANT_LOAD:
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case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
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break;
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default:
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/* Do not set a writemask on Gen6 for math instructions, those are
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* executed using align1 mode that does not support a destination mask.
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*/
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if (!(brw->gen == 6 && inst->is_math()) && !inst->is_tex()) {
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inst->dst.writemask = new_writemask;
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return true;
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}
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}
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}
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return false;
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}
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/**
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* Must be called after calculate_live_intervals() to remove unused
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* writes to registers -- register allocation will fail otherwise
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* because something deffed but not used won't be considered to
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* interfere with other regs.
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*/
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bool
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vec4_visitor::dead_code_eliminate()
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{
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bool progress = false;
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int pc = -1;
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calculate_live_intervals();
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foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
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pc++;
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bool inst_writes_flag = false;
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if (inst->dst.file != GRF) {
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if (inst->dst.is_null() && inst->writes_flag()) {
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inst_writes_flag = true;
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} else {
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continue;
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}
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}
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if (inst->dst.file == GRF) {
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int write_mask = inst->dst.writemask;
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for (int c = 0; c < 4; c++) {
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if (write_mask & (1 << c)) {
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assert(this->virtual_grf_end[inst->dst.reg * 4 + c] >= pc);
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if (this->virtual_grf_end[inst->dst.reg * 4 + c] == pc) {
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write_mask &= ~(1 << c);
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}
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}
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}
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progress = try_eliminate_instruction(inst, write_mask, brw) ||
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progress;
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}
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if (inst->predicate || inst->prev == NULL)
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continue;
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int dead_channels;
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if (inst_writes_flag) {
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/* Arbitrarily chosen, other than not being an xyzw writemask. */
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#define FLAG_WRITEMASK (1 << 5)
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dead_channels = inst->reads_flag() ? 0 : FLAG_WRITEMASK;
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} else {
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dead_channels = inst->dst.writemask;
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for (int i = 0; i < 3; i++) {
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if (inst->src[i].file != GRF ||
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inst->src[i].reg != inst->dst.reg)
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continue;
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for (int j = 0; j < 4; j++) {
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int swiz = BRW_GET_SWZ(inst->src[i].swizzle, j);
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dead_channels &= ~(1 << swiz);
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}
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}
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}
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foreach_inst_in_block_reverse_starting_from(vec4_instruction, scan_inst,
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inst, block) {
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if (dead_channels == 0)
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break;
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if (inst_writes_flag) {
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if (scan_inst->dst.is_null() && scan_inst->writes_flag()) {
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scan_inst->opcode = BRW_OPCODE_NOP;
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progress = true;
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continue;
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} else if (scan_inst->reads_flag()) {
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break;
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}
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}
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if (inst->dst.file == scan_inst->dst.file &&
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inst->dst.reg == scan_inst->dst.reg &&
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inst->dst.reg_offset == scan_inst->dst.reg_offset) {
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int new_writemask = scan_inst->dst.writemask & ~dead_channels;
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progress = try_eliminate_instruction(scan_inst, new_writemask, brw) ||
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progress;
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}
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for (int i = 0; i < 3; i++) {
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if (scan_inst->src[i].file != inst->dst.file ||
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scan_inst->src[i].reg != inst->dst.reg)
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continue;
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for (int j = 0; j < 4; j++) {
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int swiz = BRW_GET_SWZ(scan_inst->src[i].swizzle, j);
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dead_channels &= ~(1 << swiz);
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}
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}
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}
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}
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if (progress) {
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foreach_block_and_inst_safe (block, backend_instruction, inst, cfg) {
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if (inst->opcode == BRW_OPCODE_NOP) {
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inst->remove(block);
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}
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}
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invalidate_live_intervals();
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}
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return progress;
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}
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void
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void
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vec4_visitor::split_uniform_registers()
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vec4_visitor::split_uniform_registers()
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{
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{
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169
src/mesa/drivers/dri/i965/brw_vec4_dead_code_eliminate.cpp
Normal file
169
src/mesa/drivers/dri/i965/brw_vec4_dead_code_eliminate.cpp
Normal file
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@ -0,0 +1,169 @@
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/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "brw_vec4.h"
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#include "brw_vec4_live_variables.h"
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#include "brw_cfg.h"
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/** @file brw_vec4_dead_code_eliminate.cpp
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*
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* Dataflow-aware dead code elimination.
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*
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* Walks the instruction list from the bottom, removing instructions that
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* have results that both aren't used in later blocks and haven't been read
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* yet in the tail end of this block.
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*/
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using namespace brw;
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static bool
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can_do_writemask(const struct brw_context *brw,
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const vec4_instruction *inst)
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{
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switch (inst->opcode) {
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case SHADER_OPCODE_GEN4_SCRATCH_READ:
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case VS_OPCODE_PULL_CONSTANT_LOAD:
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case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
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return false;
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default:
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/* The MATH instruction on Gen6 only executes in align1 mode, which does
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* not support writemasking.
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*/
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if (brw->gen == 6 && inst->is_math())
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return false;
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if (inst->is_tex())
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return false;
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return true;
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}
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}
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bool
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vec4_visitor::dead_code_eliminate()
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{
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bool progress = false;
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calculate_live_intervals();
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int num_vars = live_intervals->num_vars;
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BITSET_WORD *live = ralloc_array(NULL, BITSET_WORD, BITSET_WORDS(num_vars));
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BITSET_WORD *flag_live = ralloc_array(NULL, BITSET_WORD, 1);
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foreach_block(block, cfg) {
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memcpy(live, live_intervals->block_data[block->num].liveout,
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sizeof(BITSET_WORD) * BITSET_WORDS(num_vars));
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memcpy(flag_live, live_intervals->block_data[block->num].flag_liveout,
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sizeof(BITSET_WORD));
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foreach_inst_in_block_reverse(vec4_instruction, inst, block) {
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if (inst->dst.file == GRF && !inst->has_side_effects()) {
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bool result_live[4] = { false };
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for (int c = 0; c < 4; c++) {
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int var = inst->dst.reg * 4 + c;
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result_live[c] = BITSET_TEST(live, var);
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}
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/* If the instruction can't do writemasking, then it's all or
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* nothing.
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*/
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if (!can_do_writemask(brw, inst)) {
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bool result = result_live[0] | result_live[1] |
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result_live[2] | result_live[3];
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result_live[0] = result;
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result_live[1] = result;
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result_live[2] = result;
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result_live[3] = result;
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}
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for (int c = 0; c < 4; c++) {
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if (!result_live[c] && inst->dst.writemask & (1 << c)) {
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inst->dst.writemask &= ~(1 << c);
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progress = true;
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if (inst->dst.writemask == 0) {
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if (inst->writes_accumulator) {
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inst->dst = dst_reg(retype(brw_null_reg(), inst->dst.type));
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} else {
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inst->opcode = BRW_OPCODE_NOP;
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continue;
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}
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}
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}
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}
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}
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if (inst->dst.is_null() && inst->writes_flag()) {
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if (!BITSET_TEST(flag_live, 0)) {
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inst->opcode = BRW_OPCODE_NOP;
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progress = true;
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continue;
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}
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}
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if (inst->dst.file == GRF && !inst->predicate) {
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for (int c = 0; c < 4; c++) {
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if (inst->dst.writemask & (1 << c)) {
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int var = inst->dst.reg * 4 + c;
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BITSET_CLEAR(live, var);
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}
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}
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}
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if (inst->writes_flag()) {
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BITSET_CLEAR(flag_live, 0);
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}
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for (int i = 0; i < 3; i++) {
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if (inst->src[i].file == GRF) {
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for (int c = 0; c < 4; c++) {
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int swiz = BRW_GET_SWZ(inst->src[i].swizzle, c);
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int var = inst->src[i].reg * 4 + swiz;
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BITSET_SET(live, var);
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}
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}
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}
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if (inst->reads_flag()) {
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BITSET_SET(flag_live, 0);
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}
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}
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}
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ralloc_free(live);
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ralloc_free(flag_live);
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if (progress) {
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foreach_block_and_inst_safe(block, backend_instruction, inst, cfg) {
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if (inst->opcode == BRW_OPCODE_NOP) {
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inst->remove(block);
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}
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}
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invalidate_live_intervals();
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}
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return progress;
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}
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