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https://gitlab.freedesktop.org/mesa/mesa.git
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radeonsi: merge constant and shader buffers descriptor lists into one
Constant buffers: slot[16], .. slot[31] (ascending) Shader buffers: slot[15], .. slot[0] (descending) The idea is that if we have 4 constant buffers and 2 shader buffers, we only have to upload 6 slots. That optimization is left for a later commit. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák
parent
d88ca12350
commit
5df24c3fa6
8 changed files with 152 additions and 132 deletions
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@ -380,23 +380,24 @@ static void si_dump_framebuffer(struct si_context *sctx, FILE *f)
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}
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}
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typedef unsigned (*slot_remap_func)(unsigned);
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static void si_dump_descriptor_list(struct si_descriptors *desc,
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const char *shader_name,
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const char *elem_name,
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unsigned num_elements,
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slot_remap_func slot_remap,
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FILE *f)
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{
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unsigned i, j;
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uint32_t *cpu_list = desc->list;
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uint32_t *gpu_list = desc->gpu_list;
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const char *list_note = "GPU list";
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if (!gpu_list) {
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gpu_list = cpu_list;
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list_note = "CPU list";
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}
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for (i = 0; i < num_elements; i++) {
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unsigned dw_offset = slot_remap(i) * desc->element_dw_size;
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uint32_t *gpu_ptr = desc->gpu_list ? desc->gpu_list : desc->list;
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const char *list_note = desc->gpu_list ? "GPU list" : "CPU list";
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uint32_t *cpu_list = desc->list + dw_offset;
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uint32_t *gpu_list = gpu_ptr + dw_offset;
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fprintf(f, COLOR_GREEN "%s%s slot %u (%s):" COLOR_RESET "\n",
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shader_name, elem_name, i, list_note);
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@ -444,11 +445,14 @@ static void si_dump_descriptor_list(struct si_descriptors *desc,
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}
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fprintf(f, "\n");
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gpu_list += desc->element_dw_size;
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cpu_list += desc->element_dw_size;
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}
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}
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static unsigned si_identity(unsigned slot)
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{
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return slot;
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}
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static void si_dump_descriptors(struct si_context *sctx,
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enum pipe_shader_type processor,
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const struct tgsi_shader_info *info, FILE *f)
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@ -464,9 +468,16 @@ static void si_dump_descriptors(struct si_context *sctx,
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" - Sampler",
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" - Image",
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};
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static const slot_remap_func remap_func[] = {
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si_get_constbuf_slot,
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si_get_shaderbuf_slot,
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si_identity,
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si_identity,
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};
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unsigned enabled_slots[] = {
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sctx->const_buffers[processor].enabled_mask,
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sctx->shader_buffers[processor].enabled_mask,
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sctx->const_and_shader_buffers[processor].enabled_mask >> SI_NUM_SHADER_BUFFERS,
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util_bitreverse(sctx->const_and_shader_buffers[processor].enabled_mask &
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u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS)),
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sctx->samplers[processor].views.enabled_mask,
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sctx->images[processor].enabled_mask,
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};
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@ -481,12 +492,14 @@ static void si_dump_descriptors(struct si_context *sctx,
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assert(info); /* only CS may not have an info struct */
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si_dump_descriptor_list(&sctx->vertex_buffers, shader_name[processor],
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" - Vertex buffer", info->num_inputs, f);
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" - Vertex buffer", info->num_inputs,
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si_identity, f);
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}
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for (unsigned i = 0; i < SI_NUM_SHADER_DESCS; ++i, ++descs)
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si_dump_descriptor_list(descs, shader_name[processor], elem_name[i],
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util_last_bit(enabled_slots[i] | required_slots[i]), f);
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util_last_bit(enabled_slots[i] | required_slots[i]),
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remap_func[i], f);
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}
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static void si_dump_gfx_descriptors(struct si_context *sctx,
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@ -805,7 +818,8 @@ static void si_dump_debug_state(struct pipe_context *ctx, FILE *f,
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}
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si_dump_descriptor_list(&sctx->descriptors[SI_DESCS_RW_BUFFERS],
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"", "RW buffers", SI_NUM_RW_BUFFERS, f);
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"", "RW buffers", SI_NUM_RW_BUFFERS,
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si_identity, f);
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si_dump_gfx_descriptors(sctx, &sctx->vs_shader, f);
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si_dump_gfx_descriptors(sctx, &sctx->tcs_shader, f);
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si_dump_gfx_descriptors(sctx, &sctx->tes_shader, f);
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@ -936,11 +936,15 @@ static void si_init_buffer_resources(struct si_buffer_resources *buffers,
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unsigned num_buffers,
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unsigned shader_userdata_index,
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enum radeon_bo_usage shader_usage,
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enum radeon_bo_usage shader_usage_constbuf,
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enum radeon_bo_priority priority,
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enum radeon_bo_priority priority_constbuf,
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unsigned *ce_offset)
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{
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buffers->shader_usage = shader_usage;
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buffers->shader_usage_constbuf = shader_usage_constbuf;
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buffers->priority = priority;
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buffers->priority_constbuf = priority_constbuf;
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buffers->buffers = CALLOC(num_buffers, sizeof(struct pipe_resource*));
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si_init_descriptors(descs, shader_userdata_index, 4,
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@ -969,8 +973,11 @@ static void si_buffer_resources_begin_new_cs(struct si_context *sctx,
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int i = u_bit_scan(&mask);
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radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
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(struct r600_resource*)buffers->buffers[i],
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buffers->shader_usage, buffers->priority);
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r600_resource(buffers->buffers[i]),
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i < SI_NUM_SHADER_BUFFERS ? buffers->shader_usage :
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buffers->shader_usage_constbuf,
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i < SI_NUM_SHADER_BUFFERS ? buffers->priority :
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buffers->priority_constbuf);
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}
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}
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@ -1119,16 +1126,16 @@ bool si_upload_vertex_buffer_descriptors(struct si_context *sctx)
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/* CONSTANT BUFFERS */
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static unsigned
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si_const_buffer_descriptors_idx(unsigned shader)
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si_const_and_shader_buffer_descriptors_idx(unsigned shader)
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{
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return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
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SI_SHADER_DESCS_CONST_BUFFERS;
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SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS;
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}
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static struct si_descriptors *
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si_const_buffer_descriptors(struct si_context *sctx, unsigned shader)
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si_const_and_shader_buffer_descriptors(struct si_context *sctx, unsigned shader)
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{
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return &sctx->descriptors[si_const_buffer_descriptors_idx(shader)];
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return &sctx->descriptors[si_const_and_shader_buffer_descriptors_idx(shader)];
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}
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void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuffer,
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@ -1199,8 +1206,8 @@ static void si_set_constant_buffer(struct si_context *sctx,
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buffers->buffers[slot] = buffer;
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radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
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(struct r600_resource*)buffer,
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buffers->shader_usage,
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buffers->priority, true);
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buffers->shader_usage_constbuf,
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buffers->priority_constbuf, true);
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buffers->enabled_mask |= 1u << slot;
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} else {
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/* Clear the descriptor. */
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@ -1228,8 +1235,9 @@ static void si_pipe_set_constant_buffer(struct pipe_context *ctx,
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if (shader >= SI_NUM_SHADERS)
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return;
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si_set_constant_buffer(sctx, &sctx->const_buffers[shader],
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si_const_buffer_descriptors_idx(shader),
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slot = si_get_constbuf_slot(slot);
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si_set_constant_buffer(sctx, &sctx->const_and_shader_buffers[shader],
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si_const_and_shader_buffer_descriptors_idx(shader),
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slot, input);
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}
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@ -1238,35 +1246,22 @@ void si_get_pipe_constant_buffer(struct si_context *sctx, uint shader,
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{
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cbuf->user_buffer = NULL;
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si_get_buffer_from_descriptors(
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&sctx->const_buffers[shader],
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si_const_buffer_descriptors(sctx, shader),
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slot, &cbuf->buffer, &cbuf->buffer_offset, &cbuf->buffer_size);
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&sctx->const_and_shader_buffers[shader],
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si_const_and_shader_buffer_descriptors(sctx, shader),
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si_get_constbuf_slot(slot),
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&cbuf->buffer, &cbuf->buffer_offset, &cbuf->buffer_size);
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}
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/* SHADER BUFFERS */
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static unsigned
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si_shader_buffer_descriptors_idx(enum pipe_shader_type shader)
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{
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return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
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SI_SHADER_DESCS_SHADER_BUFFERS;
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}
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static struct si_descriptors *
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si_shader_buffer_descriptors(struct si_context *sctx,
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enum pipe_shader_type shader)
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{
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return &sctx->descriptors[si_shader_buffer_descriptors_idx(shader)];
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}
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static void si_set_shader_buffers(struct pipe_context *ctx,
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enum pipe_shader_type shader,
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unsigned start_slot, unsigned count,
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const struct pipe_shader_buffer *sbuffers)
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{
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struct si_context *sctx = (struct si_context *)ctx;
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struct si_buffer_resources *buffers = &sctx->shader_buffers[shader];
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struct si_descriptors *descs = si_shader_buffer_descriptors(sctx, shader);
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struct si_buffer_resources *buffers = &sctx->const_and_shader_buffers[shader];
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struct si_descriptors *descs = si_const_and_shader_buffer_descriptors(sctx, shader);
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unsigned i;
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assert(start_slot + count <= SI_NUM_SHADER_BUFFERS);
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@ -1274,7 +1269,7 @@ static void si_set_shader_buffers(struct pipe_context *ctx,
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for (i = 0; i < count; ++i) {
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const struct pipe_shader_buffer *sbuffer = sbuffers ? &sbuffers[i] : NULL;
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struct r600_resource *buf;
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unsigned slot = start_slot + i;
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unsigned slot = si_get_shaderbuf_slot(start_slot + i);
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uint32_t *desc = descs->list + slot * 4;
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uint64_t va;
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@ -1284,7 +1279,7 @@ static void si_set_shader_buffers(struct pipe_context *ctx,
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buffers->enabled_mask &= ~(1u << slot);
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descs->dirty_mask |= 1u << slot;
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sctx->descriptors_dirty |=
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1u << si_shader_buffer_descriptors_idx(shader);
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1u << si_const_and_shader_buffer_descriptors_idx(shader);
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continue;
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}
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@ -1311,7 +1306,7 @@ static void si_set_shader_buffers(struct pipe_context *ctx,
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buffers->enabled_mask |= 1u << slot;
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descs->dirty_mask |= 1u << slot;
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sctx->descriptors_dirty |=
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1u << si_shader_buffer_descriptors_idx(shader);
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1u << si_const_and_shader_buffer_descriptors_idx(shader);
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util_range_add(&buf->valid_buffer_range, sbuffer->buffer_offset,
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sbuffer->buffer_offset + sbuffer->buffer_size);
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@ -1323,12 +1318,13 @@ void si_get_shader_buffers(struct si_context *sctx,
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uint start_slot, uint count,
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struct pipe_shader_buffer *sbuf)
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{
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struct si_buffer_resources *buffers = &sctx->shader_buffers[shader];
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struct si_descriptors *descs = si_shader_buffer_descriptors(sctx, shader);
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struct si_buffer_resources *buffers = &sctx->const_and_shader_buffers[shader];
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struct si_descriptors *descs = si_const_and_shader_buffer_descriptors(sctx, shader);
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for (unsigned i = 0; i < count; ++i) {
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si_get_buffer_from_descriptors(
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buffers, descs, start_slot + i,
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buffers, descs,
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si_get_shaderbuf_slot(start_slot + i),
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&sbuf[i].buffer, &sbuf[i].buffer_offset,
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&sbuf[i].buffer_size);
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}
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@ -1603,11 +1599,14 @@ void si_update_compressed_colortex_masks(struct si_context *sctx)
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static void si_reset_buffer_resources(struct si_context *sctx,
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struct si_buffer_resources *buffers,
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unsigned descriptors_idx,
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unsigned slot_mask,
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struct pipe_resource *buf,
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uint64_t old_va)
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uint64_t old_va,
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enum radeon_bo_usage usage,
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enum radeon_bo_priority priority)
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{
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struct si_descriptors *descs = &sctx->descriptors[descriptors_idx];
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unsigned mask = buffers->enabled_mask;
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unsigned mask = buffers->enabled_mask & slot_mask;
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while (mask) {
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unsigned i = u_bit_scan(&mask);
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@ -1620,8 +1619,7 @@ static void si_reset_buffer_resources(struct si_context *sctx,
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radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
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(struct r600_resource *)buf,
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buffers->shader_usage,
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buffers->priority, true);
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usage, priority, true);
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}
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}
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}
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@ -1690,16 +1688,22 @@ static void si_rebind_buffer(struct pipe_context *ctx, struct pipe_resource *buf
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/* Constant and shader buffers. */
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if (rbuffer->bind_history & PIPE_BIND_CONSTANT_BUFFER) {
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for (shader = 0; shader < SI_NUM_SHADERS; shader++)
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si_reset_buffer_resources(sctx, &sctx->const_buffers[shader],
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si_const_buffer_descriptors_idx(shader),
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buf, old_va);
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si_reset_buffer_resources(sctx, &sctx->const_and_shader_buffers[shader],
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si_const_and_shader_buffer_descriptors_idx(shader),
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u_bit_consecutive(SI_NUM_SHADER_BUFFERS, SI_NUM_CONST_BUFFERS),
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buf, old_va,
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sctx->const_and_shader_buffers[shader].shader_usage_constbuf,
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sctx->const_and_shader_buffers[shader].priority_constbuf);
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}
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if (rbuffer->bind_history & PIPE_BIND_SHADER_BUFFER) {
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for (shader = 0; shader < SI_NUM_SHADERS; shader++)
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si_reset_buffer_resources(sctx, &sctx->shader_buffers[shader],
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si_shader_buffer_descriptors_idx(shader),
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buf, old_va);
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si_reset_buffer_resources(sctx, &sctx->const_and_shader_buffers[shader],
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si_const_and_shader_buffer_descriptors_idx(shader),
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u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS),
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buf, old_va,
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sctx->const_and_shader_buffers[shader].shader_usage,
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sctx->const_and_shader_buffers[shader].priority);
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}
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if (rbuffer->bind_history & PIPE_BIND_SAMPLER_VIEW) {
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@ -2000,8 +2004,8 @@ void si_init_all_descriptors(struct si_context *sctx)
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int i;
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unsigned ce_offset = 0;
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STATIC_ASSERT(GFX9_SGPR_TCS_CONST_BUFFERS % 2 == 0);
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STATIC_ASSERT(GFX9_SGPR_GS_CONST_BUFFERS % 2 == 0);
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STATIC_ASSERT(GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS % 2 == 0);
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STATIC_ASSERT(GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS % 2 == 0);
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for (i = 0; i < SI_NUM_SHADERS; i++) {
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bool gfx9_tcs = sctx->b.chip_class == GFX9 &&
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@ -2013,27 +2017,23 @@ void si_init_all_descriptors(struct si_context *sctx)
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*/
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bool big_ce = sctx->b.chip_class <= VI;
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bool images_use_ce = big_ce;
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bool shaderbufs_use_ce = big_ce ||
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i == PIPE_SHADER_COMPUTE;
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bool const_and_shaderbufs_use_ce = big_ce ||
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i == PIPE_SHADER_VERTEX ||
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i == PIPE_SHADER_FRAGMENT;
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bool samplers_use_ce = big_ce ||
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i == PIPE_SHADER_FRAGMENT;
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si_init_buffer_resources(&sctx->const_buffers[i],
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si_const_buffer_descriptors(sctx, i),
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SI_NUM_CONST_BUFFERS,
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gfx9_tcs ? GFX9_SGPR_TCS_CONST_BUFFERS :
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gfx9_gs ? GFX9_SGPR_GS_CONST_BUFFERS :
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SI_SGPR_CONST_BUFFERS,
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RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER,
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&ce_offset);
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si_init_buffer_resources(&sctx->shader_buffers[i],
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si_shader_buffer_descriptors(sctx, i),
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SI_NUM_SHADER_BUFFERS,
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gfx9_tcs ? GFX9_SGPR_TCS_SHADER_BUFFERS :
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gfx9_gs ? GFX9_SGPR_GS_SHADER_BUFFERS :
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SI_SGPR_SHADER_BUFFERS,
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RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RW_BUFFER,
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shaderbufs_use_ce ? &ce_offset : NULL);
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si_init_buffer_resources(&sctx->const_and_shader_buffers[i],
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si_const_and_shader_buffer_descriptors(sctx, i),
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SI_NUM_SHADER_BUFFERS + SI_NUM_CONST_BUFFERS,
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gfx9_tcs ? GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS :
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gfx9_gs ? GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS :
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SI_SGPR_CONST_AND_SHADER_BUFFERS,
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RADEON_USAGE_READWRITE,
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RADEON_USAGE_READ,
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RADEON_PRIO_SHADER_RW_BUFFER,
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RADEON_PRIO_CONST_BUFFER,
|
||||
const_and_shaderbufs_use_ce ? &ce_offset : NULL);
|
||||
|
||||
si_init_descriptors(si_sampler_descriptors(sctx, i),
|
||||
gfx9_tcs ? GFX9_SGPR_TCS_SAMPLERS :
|
||||
|
|
@ -2055,7 +2055,10 @@ void si_init_all_descriptors(struct si_context *sctx)
|
|||
si_init_buffer_resources(&sctx->rw_buffers,
|
||||
&sctx->descriptors[SI_DESCS_RW_BUFFERS],
|
||||
SI_NUM_RW_BUFFERS, SI_SGPR_RW_BUFFERS,
|
||||
RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS,
|
||||
/* The second set of usage/priority is used by
|
||||
* const buffers in RW buffer slots. */
|
||||
RADEON_USAGE_READWRITE, RADEON_USAGE_READ,
|
||||
RADEON_PRIO_SHADER_RINGS, RADEON_PRIO_CONST_BUFFER,
|
||||
&ce_offset);
|
||||
si_init_descriptors(&sctx->vertex_buffers, SI_SGPR_VERTEX_BUFFERS,
|
||||
4, SI_NUM_VERTEX_BUFFERS, NULL, NULL);
|
||||
|
|
@ -2148,10 +2151,8 @@ void si_release_all_descriptors(struct si_context *sctx)
|
|||
int i;
|
||||
|
||||
for (i = 0; i < SI_NUM_SHADERS; i++) {
|
||||
si_release_buffer_resources(&sctx->const_buffers[i],
|
||||
si_const_buffer_descriptors(sctx, i));
|
||||
si_release_buffer_resources(&sctx->shader_buffers[i],
|
||||
si_shader_buffer_descriptors(sctx, i));
|
||||
si_release_buffer_resources(&sctx->const_and_shader_buffers[i],
|
||||
si_const_and_shader_buffer_descriptors(sctx, i));
|
||||
si_release_sampler_views(&sctx->samplers[i].views);
|
||||
si_release_image_views(&sctx->images[i]);
|
||||
}
|
||||
|
|
@ -2168,8 +2169,7 @@ void si_all_descriptors_begin_new_cs(struct si_context *sctx)
|
|||
int i;
|
||||
|
||||
for (i = 0; i < SI_NUM_SHADERS; i++) {
|
||||
si_buffer_resources_begin_new_cs(sctx, &sctx->const_buffers[i]);
|
||||
si_buffer_resources_begin_new_cs(sctx, &sctx->shader_buffers[i]);
|
||||
si_buffer_resources_begin_new_cs(sctx, &sctx->const_and_shader_buffers[i]);
|
||||
si_sampler_views_begin_new_cs(sctx, &sctx->samplers[i].views);
|
||||
si_image_views_begin_new_cs(sctx, &sctx->images[i]);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -295,8 +295,7 @@ struct si_context {
|
|||
unsigned shader_pointers_dirty;
|
||||
unsigned compressed_tex_shader_mask;
|
||||
struct si_buffer_resources rw_buffers;
|
||||
struct si_buffer_resources const_buffers[SI_NUM_SHADERS];
|
||||
struct si_buffer_resources shader_buffers[SI_NUM_SHADERS];
|
||||
struct si_buffer_resources const_and_shader_buffers[SI_NUM_SHADERS];
|
||||
struct si_textures_info samplers[SI_NUM_SHADERS];
|
||||
struct si_images_info images[SI_NUM_SHADERS];
|
||||
|
||||
|
|
|
|||
|
|
@ -1726,10 +1726,10 @@ static void declare_compute_memory(struct si_shader_context *ctx,
|
|||
static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
|
||||
{
|
||||
LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
|
||||
ctx->param_const_buffers);
|
||||
ctx->param_const_and_shader_buffers);
|
||||
|
||||
return ac_build_indexed_load_const(&ctx->ac, list_ptr,
|
||||
LLVMConstInt(ctx->i32, i, 0));
|
||||
LLVMConstInt(ctx->i32, si_get_constbuf_slot(i), 0));
|
||||
}
|
||||
|
||||
static LLVMValueRef fetch_constant(
|
||||
|
|
@ -1759,11 +1759,13 @@ static LLVMValueRef fetch_constant(
|
|||
idx = reg->Register.Index * 4 + swizzle;
|
||||
|
||||
if (reg->Register.Dimension && reg->Dimension.Indirect) {
|
||||
LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_buffers);
|
||||
LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
|
||||
LLVMValueRef index;
|
||||
index = si_get_bounded_indirect_index(ctx, ®->DimIndirect,
|
||||
reg->Dimension.Index,
|
||||
SI_NUM_CONST_BUFFERS);
|
||||
index = LLVMBuildAdd(ctx->gallivm.builder, index,
|
||||
LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
|
||||
bufp = ac_build_indexed_load_const(&ctx->ac, ptr, index);
|
||||
} else
|
||||
bufp = load_const_buffer_desc(ctx, buf);
|
||||
|
|
@ -2796,13 +2798,11 @@ static void si_set_ls_return_value_for_tcs(struct si_shader_context *ctx)
|
|||
|
||||
unsigned desc_param = ctx->param_tcs_factor_addr_base64k + 2;
|
||||
ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param,
|
||||
8 + GFX9_SGPR_TCS_CONST_BUFFERS);
|
||||
8 + GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS);
|
||||
ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param + 1,
|
||||
8 + GFX9_SGPR_TCS_SAMPLERS);
|
||||
ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param + 2,
|
||||
8 + GFX9_SGPR_TCS_IMAGES);
|
||||
ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param + 3,
|
||||
8 + GFX9_SGPR_TCS_SHADER_BUFFERS);
|
||||
|
||||
unsigned vgpr = 8 + GFX9_TCS_NUM_USER_SGPR;
|
||||
ret = si_insert_input_ret_float(ctx, ret,
|
||||
|
|
@ -2825,13 +2825,11 @@ static void si_set_es_return_value_for_gs(struct si_shader_context *ctx)
|
|||
|
||||
unsigned desc_param = ctx->param_vs_state_bits + 1;
|
||||
ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param,
|
||||
8 + GFX9_SGPR_GS_CONST_BUFFERS);
|
||||
8 + GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS);
|
||||
ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param + 1,
|
||||
8 + GFX9_SGPR_GS_SAMPLERS);
|
||||
ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param + 2,
|
||||
8 + GFX9_SGPR_GS_IMAGES);
|
||||
ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param + 3,
|
||||
8 + GFX9_SGPR_GS_SHADER_BUFFERS);
|
||||
|
||||
unsigned vgpr = 8 + GFX9_GS_NUM_USER_SGPR;
|
||||
for (unsigned i = 0; i < 5; i++) {
|
||||
|
|
@ -4061,16 +4059,15 @@ static void declare_per_stage_desc_pointers(struct si_shader_context *ctx,
|
|||
unsigned *num_params,
|
||||
bool assign_params)
|
||||
{
|
||||
params[(*num_params)++] = si_const_array(ctx->v4i32, SI_NUM_CONST_BUFFERS);
|
||||
params[(*num_params)++] = si_const_array(ctx->v4i32,
|
||||
SI_NUM_SHADER_BUFFERS + SI_NUM_CONST_BUFFERS);
|
||||
params[(*num_params)++] = si_const_array(ctx->v8i32, SI_NUM_SAMPLERS);
|
||||
params[(*num_params)++] = si_const_array(ctx->v8i32, SI_NUM_IMAGES);
|
||||
params[(*num_params)++] = si_const_array(ctx->v4i32, SI_NUM_SHADER_BUFFERS);
|
||||
|
||||
if (assign_params) {
|
||||
ctx->param_const_buffers = *num_params - 4;
|
||||
ctx->param_samplers = *num_params - 3;
|
||||
ctx->param_images = *num_params - 2;
|
||||
ctx->param_shader_buffers = *num_params - 1;
|
||||
ctx->param_const_and_shader_buffers = *num_params - 3;
|
||||
ctx->param_samplers = *num_params - 2;
|
||||
ctx->param_images = *num_params - 1;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -6670,7 +6667,6 @@ static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
|
|||
params[num_params++] = ctx->i64;
|
||||
params[num_params++] = ctx->i64;
|
||||
params[num_params++] = ctx->i64;
|
||||
params[num_params++] = ctx->i64;
|
||||
params[num_params++] = ctx->i32;
|
||||
params[num_params++] = ctx->i32;
|
||||
params[num_params++] = ctx->i32;
|
||||
|
|
@ -6685,7 +6681,6 @@ static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
|
|||
params[num_params++] = ctx->i64;
|
||||
params[num_params++] = ctx->i64;
|
||||
params[num_params++] = ctx->i64;
|
||||
params[num_params++] = ctx->i64;
|
||||
params[ctx->param_tcs_offchip_layout = num_params++] = ctx->i32;
|
||||
params[num_params++] = ctx->i32;
|
||||
params[num_params++] = ctx->i32;
|
||||
|
|
@ -7042,10 +7037,9 @@ static void si_build_ps_epilog_function(struct si_shader_context *ctx,
|
|||
|
||||
/* Declare input SGPRs. */
|
||||
params[ctx->param_rw_buffers = num_params++] = ctx->i64;
|
||||
params[ctx->param_const_buffers = num_params++] = ctx->i64;
|
||||
params[ctx->param_const_and_shader_buffers = num_params++] = ctx->i64;
|
||||
params[ctx->param_samplers = num_params++] = ctx->i64;
|
||||
params[ctx->param_images = num_params++] = ctx->i64;
|
||||
params[ctx->param_shader_buffers = num_params++] = ctx->i64;
|
||||
assert(num_params == SI_PARAM_ALPHA_REF);
|
||||
params[SI_PARAM_ALPHA_REF] = ctx->f32;
|
||||
last_sgpr = SI_PARAM_ALPHA_REF;
|
||||
|
|
|
|||
|
|
@ -157,14 +157,12 @@ enum {
|
|||
*/
|
||||
SI_SGPR_RW_BUFFERS, /* rings (& stream-out, VS only) */
|
||||
SI_SGPR_RW_BUFFERS_HI,
|
||||
SI_SGPR_CONST_BUFFERS,
|
||||
SI_SGPR_CONST_BUFFERS_HI,
|
||||
SI_SGPR_CONST_AND_SHADER_BUFFERS,
|
||||
SI_SGPR_CONST_AND_SHADER_BUFFERS_HI,
|
||||
SI_SGPR_SAMPLERS, /* images & sampler states interleaved */
|
||||
SI_SGPR_SAMPLERS_HI,
|
||||
SI_SGPR_IMAGES,
|
||||
SI_SGPR_IMAGES_HI,
|
||||
SI_SGPR_SHADER_BUFFERS,
|
||||
SI_SGPR_SHADER_BUFFERS_HI,
|
||||
SI_NUM_RESOURCE_SGPRS,
|
||||
|
||||
/* all VS variants */
|
||||
|
|
@ -197,25 +195,21 @@ enum {
|
|||
GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K,
|
||||
GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K,
|
||||
GFX9_SGPR_unused_to_align_the_next_pointer,
|
||||
GFX9_SGPR_TCS_CONST_BUFFERS,
|
||||
GFX9_SGPR_TCS_CONST_BUFFERS_HI,
|
||||
GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS,
|
||||
GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS_HI,
|
||||
GFX9_SGPR_TCS_SAMPLERS, /* images & sampler states interleaved */
|
||||
GFX9_SGPR_TCS_SAMPLERS_HI,
|
||||
GFX9_SGPR_TCS_IMAGES,
|
||||
GFX9_SGPR_TCS_IMAGES_HI,
|
||||
GFX9_SGPR_TCS_SHADER_BUFFERS,
|
||||
GFX9_SGPR_TCS_SHADER_BUFFERS_HI,
|
||||
GFX9_TCS_NUM_USER_SGPR,
|
||||
|
||||
/* GFX9: Merged ES-GS (VS-GS or TES-GS). */
|
||||
GFX9_SGPR_GS_CONST_BUFFERS = SI_VS_NUM_USER_SGPR,
|
||||
GFX9_SGPR_GS_CONST_BUFFERS_HI,
|
||||
GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS = SI_VS_NUM_USER_SGPR,
|
||||
GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS_HI,
|
||||
GFX9_SGPR_GS_SAMPLERS,
|
||||
GFX9_SGPR_GS_SAMPLERS_HI,
|
||||
GFX9_SGPR_GS_IMAGES,
|
||||
GFX9_SGPR_GS_IMAGES_HI,
|
||||
GFX9_SGPR_GS_SHADER_BUFFERS,
|
||||
GFX9_SGPR_GS_SHADER_BUFFERS_HI,
|
||||
GFX9_GS_NUM_USER_SGPR,
|
||||
|
||||
/* GS limits */
|
||||
|
|
@ -229,7 +223,7 @@ enum {
|
|||
|
||||
/* LLVM function parameter indices */
|
||||
enum {
|
||||
SI_NUM_RESOURCE_PARAMS = 5,
|
||||
SI_NUM_RESOURCE_PARAMS = 4,
|
||||
|
||||
/* PS only parameters */
|
||||
SI_PARAM_ALPHA_REF = SI_NUM_RESOURCE_PARAMS,
|
||||
|
|
|
|||
|
|
@ -109,10 +109,9 @@ struct si_shader_context {
|
|||
|
||||
/* Parameter indices for LLVMGetParam. */
|
||||
int param_rw_buffers;
|
||||
int param_const_buffers;
|
||||
int param_const_and_shader_buffers;
|
||||
int param_samplers;
|
||||
int param_images;
|
||||
int param_shader_buffers;
|
||||
/* Common inputs for merged shaders. */
|
||||
int param_merged_wave_info;
|
||||
int param_merged_scratch_offset;
|
||||
|
|
|
|||
|
|
@ -84,14 +84,19 @@ shader_buffer_fetch_rsrc(struct si_shader_context *ctx,
|
|||
{
|
||||
LLVMValueRef index;
|
||||
LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
|
||||
ctx->param_shader_buffers);
|
||||
ctx->param_const_and_shader_buffers);
|
||||
|
||||
if (!reg->Register.Indirect)
|
||||
index = LLVMConstInt(ctx->i32, reg->Register.Index, 0);
|
||||
else
|
||||
if (!reg->Register.Indirect) {
|
||||
index = LLVMConstInt(ctx->i32,
|
||||
si_get_shaderbuf_slot(reg->Register.Index), 0);
|
||||
} else {
|
||||
index = si_get_bounded_indirect_index(ctx, ®->Indirect,
|
||||
reg->Register.Index,
|
||||
SI_NUM_SHADER_BUFFERS);
|
||||
index = LLVMBuildSub(ctx->gallivm.builder,
|
||||
LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS - 1, 0),
|
||||
index, "");
|
||||
}
|
||||
|
||||
return ac_build_indexed_load_const(&ctx->ac, rsrc_ptr, index);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -194,11 +194,12 @@ enum {
|
|||
* 21 - compute const buffers
|
||||
* ...
|
||||
*/
|
||||
#define SI_SHADER_DESCS_CONST_BUFFERS 0
|
||||
#define SI_SHADER_DESCS_SHADER_BUFFERS 1
|
||||
#define SI_SHADER_DESCS_SAMPLERS 2
|
||||
#define SI_SHADER_DESCS_IMAGES 3
|
||||
#define SI_NUM_SHADER_DESCS 4
|
||||
enum {
|
||||
SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS,
|
||||
SI_SHADER_DESCS_SAMPLERS,
|
||||
SI_SHADER_DESCS_IMAGES,
|
||||
SI_NUM_SHADER_DESCS,
|
||||
};
|
||||
|
||||
#define SI_DESCS_RW_BUFFERS 0
|
||||
#define SI_DESCS_FIRST_SHADER 1
|
||||
|
|
@ -251,7 +252,9 @@ struct si_sampler_views {
|
|||
|
||||
struct si_buffer_resources {
|
||||
enum radeon_bo_usage shader_usage; /* READ, WRITE, or READWRITE */
|
||||
enum radeon_bo_usage shader_usage_constbuf;
|
||||
enum radeon_bo_priority priority;
|
||||
enum radeon_bo_priority priority_constbuf;
|
||||
struct pipe_resource **buffers; /* this has num_buffers elements */
|
||||
|
||||
/* The i-th bit is set if that element is enabled (non-NULL resource). */
|
||||
|
|
@ -372,4 +375,16 @@ si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
|
|||
return rtex->surface.u.legacy.tiling_index[level];
|
||||
}
|
||||
|
||||
static inline unsigned si_get_constbuf_slot(unsigned slot)
|
||||
{
|
||||
/* Constant buffers are in slots [16..31], ascending */
|
||||
return SI_NUM_SHADER_BUFFERS + slot;
|
||||
}
|
||||
|
||||
static inline unsigned si_get_shaderbuf_slot(unsigned slot)
|
||||
{
|
||||
/* shader buffers are in slots [15..0], descending */
|
||||
return SI_NUM_SHADER_BUFFERS - 1 - slot;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue