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i965/fs: Remove FS_OPCODE_PACK_STENCIL_REF virtual instruction.

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It's just a byte MOV with strided source.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
This commit is contained in:
Francisco Jerez 2016-05-20 00:13:19 -07:00
parent 29ce110be6
commit 5db4d62395
5 changed files with 2 additions and 52 deletions
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1
src/mesa/drivers/dri/i965/brw_defines.h
View file

@ -951,7 +951,6 @@ enum opcode {
FS_OPCODE_FB_WRITE_LOGICAL,
FS_OPCODE_REP_FB_WRITE,
FS_OPCODE_PACK_STENCIL_REF,
SHADER_OPCODE_RCP,
SHADER_OPCODE_RSQ,
SHADER_OPCODE_SQRT,

4
src/mesa/drivers/dri/i965/brw_fs.cpp
View file

@ -3824,8 +3824,8 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst,
sources[length] = bld.vgrf(BRW_REGISTER_TYPE_UD);
bld.exec_all().annotate("FB write OS")
.emit(FS_OPCODE_PACK_STENCIL_REF, sources[length],
retype(src_stencil, BRW_REGISTER_TYPE_UB));
.MOV(retype(sources[length], BRW_REGISTER_TYPE_UB),
subscript(src_stencil, BRW_REGISTER_TYPE_UB, 0));
length++;
}

2
src/mesa/drivers/dri/i965/brw_fs.h
View file

@ -430,8 +430,6 @@ private:
void generate_urb_read(fs_inst *inst, struct brw_reg dst, struct brw_reg payload);
void generate_urb_write(fs_inst *inst, struct brw_reg payload);
void generate_cs_terminate(fs_inst *inst, struct brw_reg payload);
void generate_stencil_ref_packing(fs_inst *inst, struct brw_reg dst,
struct brw_reg src);
void generate_barrier(fs_inst *inst, struct brw_reg src);
void generate_linterp(fs_inst *inst, struct brw_reg dst,
struct brw_reg *src);

45
src/mesa/drivers/dri/i965/brw_fs_generator.cpp
View file

@ -509,47 +509,6 @@ fs_generator::generate_cs_terminate(fs_inst *inst, struct brw_reg payload)
brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
}
void
fs_generator::generate_stencil_ref_packing(fs_inst *inst,
struct brw_reg dst,
struct brw_reg src)
{
assert(dispatch_width == 8);
assert(devinfo->gen >= 9);
/* Stencil value updates are provided in 8 slots of 1 byte per slot.
* Presumably, in order to save memory bandwidth, the stencil reference
* values written from the FS need to be packed into 2 dwords (this makes
* sense because the stencil values are limited to 1 byte each and a SIMD8
* send, so stencil slots 0-3 in dw0, and 4-7 in dw1.)
*
* The spec is confusing here because in the payload definition of MDP_RTW_S8
* (Message Data Payload for Render Target Writes with Stencil 8b) the
* stencil value seems to be dw4.0-dw4.7. However, if you look at the type of
* dw4 it is type MDPR_STENCIL (Message Data Payload Register) which is the
* packed values specified above and diagrammed below:
*
* 31 0
* --------------------------------
* DW | |
* 2-7 | IGNORED |
* | |
* --------------------------------
* DW1 | STC | STC | STC | STC |
* | slot7 | slot6 | slot5 | slot4|
* --------------------------------
* DW0 | STC | STC | STC | STC |
* | slot3 | slot2 | slot1 | slot0|
* --------------------------------
*/
src.vstride = BRW_VERTICAL_STRIDE_4;
src.width = BRW_WIDTH_1;
src.hstride = BRW_HORIZONTAL_STRIDE_0;
assert(src.type == BRW_REGISTER_TYPE_UB);
brw_MOV(p, retype(dst, BRW_REGISTER_TYPE_UB), src);
}
void
fs_generator::generate_barrier(fs_inst *inst, struct brw_reg src)
{
@ -2102,10 +2061,6 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
generate_barrier(inst, src[0]);
break;
case FS_OPCODE_PACK_STENCIL_REF:
generate_stencil_ref_packing(inst, dst, src[0]);
break;
default:
unreachable("Unsupported opcode");

2
src/mesa/drivers/dri/i965/brw_shader.cpp
View file

@ -163,8 +163,6 @@ brw_instruction_name(const struct brw_device_info *devinfo, enum opcode op)
return "fb_write";
case FS_OPCODE_FB_WRITE_LOGICAL:
return "fb_write_logical";
case FS_OPCODE_PACK_STENCIL_REF:
return "pack_stencil_ref";
case FS_OPCODE_REP_FB_WRITE:
return "rep_fb_write";