diff --git a/src/amd/vulkan/radv_pipeline_graphics.c b/src/amd/vulkan/radv_pipeline_graphics.c
index 92469f234ae..dc532d3ffc2 100644
--- a/src/amd/vulkan/radv_pipeline_graphics.c
+++ b/src/amd/vulkan/radv_pipeline_graphics.c
@@ -1556,20 +1556,6 @@ radv_graphics_shaders_link_varyings(struct radv_shader_stage *stages, enum amd_g
 
       /* Update load/store alignments because inter-stage code motion may move instructions used to deduce this info. */
       NIR_PASS(_, shader, nir_opt_load_store_update_alignments);
-
-      /* Scalarize all I/O, because nir_opt_varyings and nir_opt_vectorize_io expect all I/O to be scalarized. */
-      nir_variable_mode sca_mode = nir_var_shader_in;
-      bool sca_progress = false;
-      if (s != MESA_SHADER_FRAGMENT)
-         sca_mode |= nir_var_shader_out;
-
-      NIR_PASS(sca_progress, shader, nir_lower_io_to_scalar, sca_mode, NULL, NULL);
-
-      if (sca_progress) {
-         /* Eliminate useless vec->mov copies resulting from scalarization. */
-         NIR_PASS(_, shader, nir_opt_copy_prop);
-         NIR_PASS(_, shader, nir_opt_constant_folding);
-      }
    }
 
    int highest_changed_producer = -1;
@@ -2761,6 +2747,15 @@ radv_graphics_shaders_compile(struct radv_device *device, struct vk_pipeline_cac
 
       radv_nir_lower_io(device, stages[i].nir);
 
+      if (!stages[i].key.optimisations_disabled) {
+         /* Scalarize all I/O, because nir_opt_varyings and nir_opt_vectorize_io expect all I/O to be scalarized. */
+         NIR_PASS(_, stages[i].nir, nir_lower_io_to_scalar, nir_var_shader_in | nir_var_shader_out, NULL, NULL);
+
+         /* Eliminate useless vec->mov copies resulting from scalarization. */
+         NIR_PASS(_, stages[i].nir, nir_opt_copy_prop);
+         NIR_PASS(_, stages[i].nir, nir_opt_constant_folding);
+      }
+
       stages[i].feedback.duration += os_time_get_nano() - stage_start;
    }
 
@@ -2771,9 +2766,6 @@ radv_graphics_shaders_compile(struct radv_device *device, struct vk_pipeline_cac
       if (!gfx_state->ps.has_epilog) {
          NIR_PASS(_, stages[MESA_SHADER_FRAGMENT].nir, radv_nir_remap_color_attachment, gfx_state);
 
-         /* Lower FS outputs to scalar to allow dce. */
-         NIR_PASS(_, stages[MESA_SHADER_FRAGMENT].nir, nir_lower_io_to_scalar, nir_var_shader_out, NULL, NULL);
-
          NIR_PASS(_, stages[MESA_SHADER_FRAGMENT].nir, radv_nir_trim_fs_color_exports, &gfx_state->ps.epilog);
 
          NIR_PASS(_, stages[MESA_SHADER_FRAGMENT].nir, nir_opt_copy_prop);