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intel/fs/ra: Define REG_CLASS_COUNT constant specifying the number of register classes.

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Rework:
 * Jordan: 16=>20 following d33aff783d ("intel/fs: add support for
   sparse accesses")

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
This commit is contained in:
Francisco Jerez 2022-02-18 22:25:58 -08:00 • committed by Jordan Justen
parent 502b864dcc
commit 5d87f41a54
1 changed files with 9 additions and 6 deletions
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15
src/intel/compiler/brw_fs_reg_allocate.cpp
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@ -33,6 +33,8 @@
using namespace brw; using namespace brw;
#define REG_CLASS_COUNT 20
static void static void
assign_reg(unsigned *reg_hw_locations, fs_reg *reg) assign_reg(unsigned *reg_hw_locations, fs_reg *reg)
{ {
@ -113,21 +115,22 @@ brw_alloc_reg_set(struct brw_compiler *compiler, int dispatch_width)
* instruction, and on gfx4 we need 8 contiguous regs for workaround simd16 * instruction, and on gfx4 we need 8 contiguous regs for workaround simd16
* texturing. * texturing.
*/ */
const int class_count = MAX_VGRF_SIZE; int class_sizes[REG_CLASS_COUNT];
int class_sizes[MAX_VGRF_SIZE]; assert(REG_CLASS_COUNT == MAX_VGRF_SIZE);
for (unsigned i = 0; i < MAX_VGRF_SIZE; i++) for (unsigned i = 0; i < REG_CLASS_COUNT; i++)
class_sizes[i] = i + 1; class_sizes[i] = i + 1;
struct ra_regs *regs = ra_alloc_reg_set(compiler, BRW_MAX_GRF, false); struct ra_regs *regs = ra_alloc_reg_set(compiler, BRW_MAX_GRF, false);
if (devinfo->ver >= 6) if (devinfo->ver >= 6)
ra_set_allocate_round_robin(regs); ra_set_allocate_round_robin(regs);
struct ra_class **classes = ralloc_array(compiler, struct ra_class *, class_count); struct ra_class **classes = ralloc_array(compiler, struct ra_class *,
REG_CLASS_COUNT);
struct ra_class *aligned_bary_class = NULL; struct ra_class *aligned_bary_class = NULL;
/* Now, make the register classes for each size of contiguous register /* Now, make the register classes for each size of contiguous register
* allocation we might need to make. * allocation we might need to make.
*/ */
for (int i = 0; i < class_count; i++) { for (int i = 0; i < REG_CLASS_COUNT; i++) {
classes[i] = ra_alloc_contig_reg_class(regs, class_sizes[i]); classes[i] = ra_alloc_contig_reg_class(regs, class_sizes[i]);
if (devinfo->ver <= 5 && dispatch_width >= 16) { if (devinfo->ver <= 5 && dispatch_width >= 16) {
@ -166,7 +169,7 @@ brw_alloc_reg_set(struct brw_compiler *compiler, int dispatch_width)
compiler->fs_reg_sets[index].regs = regs; compiler->fs_reg_sets[index].regs = regs;
for (unsigned i = 0; i < ARRAY_SIZE(compiler->fs_reg_sets[index].classes); i++) for (unsigned i = 0; i < ARRAY_SIZE(compiler->fs_reg_sets[index].classes); i++)
compiler->fs_reg_sets[index].classes[i] = NULL; compiler->fs_reg_sets[index].classes[i] = NULL;
for (int i = 0; i < class_count; i++) for (int i = 0; i < REG_CLASS_COUNT; i++)
compiler->fs_reg_sets[index].classes[class_sizes[i] - 1] = classes[i]; compiler->fs_reg_sets[index].classes[class_sizes[i] - 1] = classes[i];
compiler->fs_reg_sets[index].aligned_bary_class = aligned_bary_class; compiler->fs_reg_sets[index].aligned_bary_class = aligned_bary_class;
} }