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panfrost: XML-ify the multi-target framebuffer descriptors
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6797>
This commit is contained in:
Boris Brezillon
Alyssa Rosenzweig
parent
efce73d99d
commit
5d5f7552a5
7 changed files with 782 additions and 948 deletions
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@ -744,13 +744,13 @@ panfrost_batch_reserve_framebuffer(struct panfrost_batch *batch)
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if (!batch->framebuffer.gpu) {
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unsigned size = (dev->quirks & MIDGARD_SFBD) ?
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MALI_SINGLE_TARGET_FRAMEBUFFER_LENGTH :
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sizeof(struct mali_framebuffer);
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MALI_MULTI_TARGET_FRAMEBUFFER_LENGTH;
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batch->framebuffer = panfrost_pool_alloc_aligned(&batch->pool, size, 64);
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/* Tag the pointer */
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if (!(dev->quirks & MIDGARD_SFBD))
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batch->framebuffer.gpu |= MALI_MFBD;
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batch->framebuffer.gpu |= MALI_FBD_TAG_IS_MFBD;
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}
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return batch->framebuffer.gpu;
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File diff suppressed because it is too large
Load diff
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@ -392,14 +392,6 @@ struct mali_payload_write_value {
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* 4. Otherwise, set magic_divisor = m and extra_flags = 0.
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*/
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#define FBD_MASK (~0x3f)
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/* MFBD, rather than SFBD */
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#define MALI_MFBD (0x1)
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/* ORed into an MFBD address to specify the fbx section is included */
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#define MALI_MFBD_TAG_EXTRA (0x2)
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/* On Bifrost, these fields are the same between the vertex and tiler payloads.
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* They also seem to be the same between Bifrost and Midgard. They're shared in
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* fused payloads.
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@ -518,187 +510,4 @@ struct mali_payload_fragment {
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mali_ptr framebuffer;
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} __attribute__((packed));
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/* Configures multisampling on Bifrost fragment jobs */
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struct bifrost_multisampling {
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u64 zero1;
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u64 zero2;
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mali_ptr sample_locations;
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u64 zero4;
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} __attribute__((packed));
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#define MALI_MFBD_FORMAT_SRGB (1 << 0)
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struct mali_rt_format {
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unsigned unk1 : 32;
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unsigned unk2 : 3;
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unsigned nr_channels : 2; /* MALI_POSITIVE */
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unsigned unk3 : 4;
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unsigned unk4 : 1;
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enum mali_block_format block : 2;
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enum mali_msaa msaa : 2;
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unsigned flags : 2;
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unsigned swizzle : 12;
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unsigned zero : 3;
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/* Disables MFBD preload. When this bit is set, the render target will
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* be cleared every frame. When this bit is clear, the hardware will
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* automatically wallpaper the render target back from main memory.
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* Unfortunately, MFBD preload is very broken on Midgard, so in
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* practice, this is a chicken bit that should always be set.
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* Discovered by accident, as all good chicken bits are. */
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unsigned no_preload : 1;
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} __attribute__((packed));
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/* Flags for afbc.flags and ds_afbc.flags */
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#define MALI_AFBC_FLAGS 0x10009
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/* Lossless RGB and RGBA colorspace transform */
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#define MALI_AFBC_YTR (1 << 17)
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struct mali_render_target {
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struct mali_rt_format format;
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u64 zero1;
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struct {
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/* Stuff related to ARM Framebuffer Compression. When AFBC is enabled,
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* there is an extra metadata buffer that contains 16 bytes per tile.
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* The framebuffer needs to be the same size as before, since we don't
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* know ahead of time how much space it will take up. The
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* framebuffer_stride is set to 0, since the data isn't stored linearly
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* anymore.
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*
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* When AFBC is disabled, these fields are zero.
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*/
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mali_ptr metadata;
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u32 stride; // stride in units of tiles
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u32 flags; // = 0x20000
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} afbc;
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mali_ptr framebuffer;
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u32 zero2 : 4;
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u32 framebuffer_stride : 28; // in units of bytes, row to next
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u32 layer_stride; /* For multisample rendering */
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u32 clear_color_1; // RGBA8888 from glClear, actually used by hardware
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u32 clear_color_2; // always equal, but unclear function?
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u32 clear_color_3; // always equal, but unclear function?
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u32 clear_color_4; // always equal, but unclear function?
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} __attribute__((packed));
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/* An optional part of mali_framebuffer. It comes between the main structure
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* and the array of render targets. It must be included if any of these are
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* enabled:
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*
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* - Transaction Elimination
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* - Depth/stencil
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* - TODO: Anything else?
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*/
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/* flags_hi */
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#define MALI_EXTRA_PRESENT (0x1)
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/* flags_lo */
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#define MALI_EXTRA_ZS (0x4)
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struct mali_framebuffer_extra {
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mali_ptr checksum;
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/* Each tile has an 8 byte checksum, so the stride is "width in tiles * 8" */
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u32 checksum_stride;
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unsigned flags_lo : 4;
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enum mali_block_format zs_block : 2;
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/* Number of samples in Z/S attachment, MALI_POSITIVE. So zero for
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* 1-sample (non-MSAA), 0x3 for MSAA 4x, etc */
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unsigned zs_samples : 4;
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unsigned flags_hi : 22;
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union {
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/* Note: AFBC is only allowed for 24/8 combined depth/stencil. */
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struct {
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mali_ptr depth_stencil_afbc_metadata;
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u32 depth_stencil_afbc_stride; // in units of tiles
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u32 flags;
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mali_ptr depth_stencil;
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u64 padding;
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} ds_afbc;
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struct {
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/* Depth becomes depth/stencil in case of combined D/S */
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mali_ptr depth;
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u32 depth_stride_zero : 4;
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u32 depth_stride : 28;
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u32 depth_layer_stride;
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mali_ptr stencil;
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u32 stencil_stride_zero : 4;
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u32 stencil_stride : 28;
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u32 stencil_layer_stride;
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} ds_linear;
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};
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u32 clear_color_1;
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u32 clear_color_2;
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u64 zero3;
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} __attribute__((packed));
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/* Flags for mfbd_flags */
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/* Enables writing depth results back to main memory (rather than keeping them
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* on-chip in the tile buffer and then discarding) */
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#define MALI_MFBD_DEPTH_WRITE (1 << 10)
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/* The MFBD contains the extra mali_framebuffer_extra section */
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#define MALI_MFBD_EXTRA (1 << 13)
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struct mali_framebuffer {
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union {
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struct mali_local_storage_packed shared_memory;
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struct bifrost_multisampling msaa;
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};
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/* 0x20 */
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u16 width1, height1;
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u32 zero3;
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u16 width2, height2;
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u32 unk1 : 19; // = 0x01000
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u32 rt_count_1 : 3; // off-by-one (use MALI_POSITIVE)
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u32 unk2 : 2; // = 0
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u32 rt_count_2 : 3; // no off-by-one
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u32 zero4 : 5;
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/* 0x30 */
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u32 clear_stencil : 8;
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u32 mfbd_flags : 24; // = 0x100
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float clear_depth;
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union {
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struct {
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struct mali_midgard_tiler_packed tiler;
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struct mali_midgard_tiler_weights_packed tiler_weights;
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};
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struct {
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mali_ptr tiler_meta;
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u32 zeros[16];
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};
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};
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/* optional: struct mali_framebuffer_extra extra */
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/* struct mali_render_target rts[] */
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} __attribute__((packed));
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#endif /* __PANFROST_JOB_H__ */
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@ -183,76 +183,6 @@ pandecode_validate_buffer(mali_ptr addr, size_t sz)
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}
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}
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struct pandecode_flag_info {
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u64 flag;
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const char *name;
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};
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static void
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pandecode_log_decoded_flags(const struct pandecode_flag_info *flag_info,
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u64 flags)
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{
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bool decodable_flags_found = false;
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for (int i = 0; flag_info[i].name; i++) {
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if ((flags & flag_info[i].flag) != flag_info[i].flag)
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continue;
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if (!decodable_flags_found) {
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decodable_flags_found = true;
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} else {
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pandecode_log_cont(" | ");
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}
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pandecode_log_cont("%s", flag_info[i].name);
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flags &= ~flag_info[i].flag;
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}
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if (decodable_flags_found) {
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if (flags)
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pandecode_log_cont(" | 0x%" PRIx64, flags);
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} else {
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pandecode_log_cont("0x%" PRIx64, flags);
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}
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}
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#define FLAG_INFO(flag) { MALI_MFBD_FORMAT_##flag, "MALI_MFBD_FORMAT_" #flag }
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static const struct pandecode_flag_info mfbd_fmt_flag_info[] = {
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FLAG_INFO(SRGB),
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{}
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};
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#undef FLAG_INFO
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#define FLAG_INFO(flag) { MALI_AFBC_##flag, "MALI_AFBC_" #flag }
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static const struct pandecode_flag_info afbc_fmt_flag_info[] = {
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FLAG_INFO(YTR),
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{}
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};
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#undef FLAG_INFO
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#define FLAG_INFO(flag) { MALI_EXTRA_##flag, "MALI_EXTRA_" #flag }
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static const struct pandecode_flag_info mfbd_extra_flag_hi_info[] = {
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FLAG_INFO(PRESENT),
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{}
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};
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#undef FLAG_INFO
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#define FLAG_INFO(flag) { MALI_EXTRA_##flag, "MALI_EXTRA_" #flag }
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static const struct pandecode_flag_info mfbd_extra_flag_lo_info[] = {
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FLAG_INFO(ZS),
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{}
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};
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#undef FLAG_INFO
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#define FLAG_INFO(flag) { MALI_MFBD_##flag, "MALI_MFBD_" #flag }
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static const struct pandecode_flag_info mfbd_flag_info [] = {
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FLAG_INFO(DEPTH_WRITE),
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FLAG_INFO(EXTRA),
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{}
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};
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#undef FLAG_INFO
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/* Midgard's tiler descriptor is embedded within the
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* larger FBD */
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@ -350,30 +280,6 @@ pandecode_midgard_tiler_descriptor(
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DUMP_UNPACKED(MIDGARD_TILER_WEIGHTS, w, "Tiler Weights:\n");
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}
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/* TODO: The Bifrost tiler is not understood at all yet */
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static void
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pandecode_bifrost_tiler_descriptor(const struct mali_framebuffer *fb)
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{
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pandecode_log(".tiler = {\n");
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pandecode_indent++;
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MEMORY_PROP(fb, tiler_meta);
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for (int i = 0; i < 16; i++) {
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if (fb->zeros[i] != 0) {
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pandecode_msg("XXX: tiler descriptor zero %d tripped, value %x\n",
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i, fb->zeros[i]);
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}
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}
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pandecode_log("},\n");
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pandecode_indent--;
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pandecode_log("}\n");
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}
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/* Information about the framebuffer passed back for
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* additional analysis */
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@ -524,111 +430,49 @@ pandecode_swizzle(unsigned swizzle, enum mali_format format)
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}
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static void
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pandecode_rt_format(struct mali_rt_format format)
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pandecode_render_target(uint64_t gpu_va, unsigned job_no, bool is_bifrost, unsigned gpu_id,
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const struct MALI_MULTI_TARGET_FRAMEBUFFER_PARAMETERS *fb)
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{
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pandecode_log(".format = {\n");
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pandecode_log("Color Render Targets:\n");
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pandecode_indent++;
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pandecode_prop("unk1 = 0x%" PRIx32, format.unk1);
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pandecode_prop("unk2 = 0x%" PRIx32, format.unk2);
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pandecode_prop("unk3 = 0x%" PRIx32, format.unk3);
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pandecode_prop("unk4 = 0x%" PRIx32, format.unk4);
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pandecode_prop("block = %s", mali_block_format_as_str(format.block));
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/* TODO: Map formats so we can check swizzles and print nicely */
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pandecode_log("swizzle");
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pandecode_swizzle(format.swizzle, MALI_RGBA8_UNORM);
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pandecode_log_cont(",\n");
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pandecode_prop("nr_channels = MALI_POSITIVE(%d)",
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(format.nr_channels + 1));
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pandecode_log(".flags = ");
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pandecode_log_decoded_flags(mfbd_fmt_flag_info, format.flags);
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pandecode_log_cont(",\n");
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pandecode_prop("msaa = %s", mali_msaa_as_str(format.msaa));
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/* In theory, the no_preload bit can be cleared to enable MFBD preload,
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* which is a faster hardware-based alternative to the wallpaper method
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* to preserve framebuffer contents across frames. In practice, MFBD
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* preload is buggy on Midgard, and so this is a chicken bit. If this
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* bit isn't set, most likely something broke unrelated to preload */
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if (!format.no_preload) {
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pandecode_msg("XXX: buggy MFBD preload enabled - chicken bit should be clear\n");
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pandecode_prop("no_preload = 0x%" PRIx32, format.no_preload);
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for (int i = 0; i < (fb->render_target_count); i++) {
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mali_ptr rt_va = gpu_va + i * MALI_RENDER_TARGET_LENGTH;
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struct pandecode_mapped_memory *mem =
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pandecode_find_mapped_gpu_mem_containing(rt_va);
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const struct mali_render_target_packed *PANDECODE_PTR_VAR(rtp, mem, (mali_ptr) rt_va);
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DUMP_CL(RENDER_TARGET, rtp, "Color Render Target %d:\n", i);
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}
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if (format.zero)
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pandecode_prop("zero = 0x%" PRIx32, format.zero);
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pandecode_indent--;
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pandecode_log("},\n");
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pandecode_log("\n");
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}
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static void
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pandecode_render_target(uint64_t gpu_va, unsigned job_no, const struct mali_framebuffer *fb)
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pandecode_mfbd_bifrost_deps(const void *fb, int job_no)
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{
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pandecode_log("struct mali_render_target rts_list_%"PRIx64"_%d[] = {\n", gpu_va, job_no);
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pan_section_unpack(fb, MULTI_TARGET_FRAMEBUFFER, BIFROST_PARAMETERS, params);
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/* The blob stores all possible sample locations in a single buffer
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* allocated on startup, and just switches the pointer when switching
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* MSAA state. For now, we just put the data into the cmdstream, but we
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* should do something like what the blob does with a real driver.
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*
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* There seem to be 32 slots for sample locations, followed by another
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* 16. The second 16 is just the center location followed by 15 zeros
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* in all the cases I've identified (maybe shader vs. depth/color
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* samples?).
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*/
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struct pandecode_mapped_memory *smem =
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pandecode_find_mapped_gpu_mem_containing(params.sample_locations);
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const u16 *PANDECODE_PTR_VAR(samples, smem, params.sample_locations);
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pandecode_log("uint16_t sample_locations_%d[] = {\n", job_no);
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pandecode_indent++;
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for (int i = 0; i < (fb->rt_count_1 + 1); i++) {
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mali_ptr rt_va = gpu_va + i * sizeof(struct mali_render_target);
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struct pandecode_mapped_memory *mem =
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pandecode_find_mapped_gpu_mem_containing(rt_va);
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const struct mali_render_target *PANDECODE_PTR_VAR(rt, mem, (mali_ptr) rt_va);
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pandecode_log("{\n");
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pandecode_indent++;
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pandecode_rt_format(rt->format);
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if (rt->format.block == MALI_BLOCK_FORMAT_AFBC) {
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pandecode_log(".afbc = {\n");
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pandecode_indent++;
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char *a = pointer_as_memory_reference(rt->afbc.metadata);
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pandecode_prop("metadata = %s", a);
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free(a);
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pandecode_prop("stride = %d", rt->afbc.stride);
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pandecode_log(".flags = ");
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pandecode_log_decoded_flags(afbc_fmt_flag_info, rt->afbc.flags);
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pandecode_log_cont(",\n");
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pandecode_indent--;
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pandecode_log("},\n");
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} else if (rt->afbc.metadata || rt->afbc.stride || rt->afbc.flags) {
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pandecode_msg("XXX: AFBC disabled but AFBC field set (0x%lX, 0x%x, 0x%x)\n",
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rt->afbc.metadata,
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rt->afbc.stride,
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rt->afbc.flags);
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}
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MEMORY_PROP(rt, framebuffer);
|
||||
pandecode_prop("framebuffer_stride = %d", rt->framebuffer_stride);
|
||||
|
||||
if (rt->layer_stride)
|
||||
pandecode_prop("layer_stride = %d", rt->layer_stride);
|
||||
|
||||
if (rt->clear_color_1 | rt->clear_color_2 | rt->clear_color_3 | rt->clear_color_4) {
|
||||
pandecode_prop("clear_color_1 = 0x%" PRIx32, rt->clear_color_1);
|
||||
pandecode_prop("clear_color_2 = 0x%" PRIx32, rt->clear_color_2);
|
||||
pandecode_prop("clear_color_3 = 0x%" PRIx32, rt->clear_color_3);
|
||||
pandecode_prop("clear_color_4 = 0x%" PRIx32, rt->clear_color_4);
|
||||
}
|
||||
|
||||
if (rt->zero1 || rt->zero2) {
|
||||
pandecode_msg("XXX: render target zeros tripped\n");
|
||||
pandecode_prop("zero1 = 0x%" PRIx64, rt->zero1);
|
||||
pandecode_prop("zero2 = 0x%" PRIx32, rt->zero2);
|
||||
}
|
||||
|
||||
pandecode_indent--;
|
||||
pandecode_log("},\n");
|
||||
for (int i = 0; i < 32 + 16; i++) {
|
||||
pandecode_log("%d, %d,\n", samples[2 * i], samples[2 * i + 1]);
|
||||
}
|
||||
|
||||
pandecode_indent--;
|
||||
|
|
@ -636,212 +480,66 @@ pandecode_render_target(uint64_t gpu_va, unsigned job_no, const struct mali_fram
|
|||
}
|
||||
|
||||
static struct pandecode_fbd
|
||||
pandecode_mfbd_bfr(uint64_t gpu_va, int job_no, bool is_fragment, bool is_compute, bool is_bifrost)
|
||||
pandecode_mfbd_bfr(uint64_t gpu_va, int job_no, bool is_fragment, bool is_compute, bool is_bifrost, unsigned gpu_id)
|
||||
{
|
||||
struct pandecode_mapped_memory *mem = pandecode_find_mapped_gpu_mem_containing(gpu_va);
|
||||
const struct mali_framebuffer *PANDECODE_PTR_VAR(fb, mem, (mali_ptr) gpu_va);
|
||||
const void *PANDECODE_PTR_VAR(fb, mem, (mali_ptr) gpu_va);
|
||||
pan_section_unpack(fb, MULTI_TARGET_FRAMEBUFFER, PARAMETERS, params);
|
||||
|
||||
struct pandecode_fbd info;
|
||||
|
||||
if (is_bifrost && fb->msaa.sample_locations) {
|
||||
/* The blob stores all possible sample locations in a single buffer
|
||||
* allocated on startup, and just switches the pointer when switching
|
||||
* MSAA state. For now, we just put the data into the cmdstream, but we
|
||||
* should do something like what the blob does with a real driver.
|
||||
*
|
||||
* There seem to be 32 slots for sample locations, followed by another
|
||||
* 16. The second 16 is just the center location followed by 15 zeros
|
||||
* in all the cases I've identified (maybe shader vs. depth/color
|
||||
* samples?).
|
||||
*/
|
||||
|
||||
struct pandecode_mapped_memory *smem = pandecode_find_mapped_gpu_mem_containing(fb->msaa.sample_locations);
|
||||
|
||||
const u16 *PANDECODE_PTR_VAR(samples, smem, fb->msaa.sample_locations);
|
||||
|
||||
pandecode_log("uint16_t sample_locations_%d[] = {\n", job_no);
|
||||
pandecode_indent++;
|
||||
|
||||
for (int i = 0; i < 32 + 16; i++) {
|
||||
pandecode_log("%d, %d,\n", samples[2 * i], samples[2 * i + 1]);
|
||||
}
|
||||
|
||||
pandecode_indent--;
|
||||
pandecode_log("};\n");
|
||||
}
|
||||
if (is_bifrost)
|
||||
pandecode_mfbd_bifrost_deps(fb, job_no);
|
||||
|
||||
pandecode_log("struct mali_framebuffer framebuffer_%"PRIx64"_%d = {\n", gpu_va, job_no);
|
||||
pandecode_log("Multi-Target Framebuffer:\n");
|
||||
pandecode_indent++;
|
||||
|
||||
if (is_bifrost) {
|
||||
pandecode_log(".msaa = {\n");
|
||||
pandecode_indent++;
|
||||
|
||||
if (fb->msaa.sample_locations)
|
||||
pandecode_prop("sample_locations = sample_locations_%d", job_no);
|
||||
else
|
||||
pandecode_msg("XXX: sample_locations missing\n");
|
||||
|
||||
if (fb->msaa.zero1 || fb->msaa.zero2 || fb->msaa.zero4) {
|
||||
pandecode_msg("XXX: multisampling zero tripped\n");
|
||||
pandecode_prop("zero1 = %" PRIx64, fb->msaa.zero1);
|
||||
pandecode_prop("zero2 = %" PRIx64, fb->msaa.zero2);
|
||||
pandecode_prop("zero4 = %" PRIx64, fb->msaa.zero4);
|
||||
}
|
||||
|
||||
pandecode_indent--;
|
||||
pandecode_log("},\n");
|
||||
DUMP_SECTION(MULTI_TARGET_FRAMEBUFFER, BIFROST_PARAMETERS, fb, "Bifrost Params:\n");
|
||||
} else {
|
||||
struct mali_local_storage_packed ls = fb->shared_memory;
|
||||
DUMP_CL(LOCAL_STORAGE, &ls, "Local Storage:\n");
|
||||
DUMP_SECTION(MULTI_TARGET_FRAMEBUFFER, LOCAL_STORAGE, fb, "Local Storage:\n");
|
||||
}
|
||||
|
||||
info.width = fb->width1 + 1;
|
||||
info.height = fb->height1 + 1;
|
||||
info.rt_count = fb->rt_count_1 + 1;
|
||||
info.width = params.width;
|
||||
info.height = params.height;
|
||||
info.rt_count = params.render_target_count;
|
||||
DUMP_UNPACKED(MULTI_TARGET_FRAMEBUFFER_PARAMETERS, params, "Parameters:\n");
|
||||
|
||||
pandecode_prop("width1 = MALI_POSITIVE(%d)", fb->width1 + 1);
|
||||
pandecode_prop("height1 = MALI_POSITIVE(%d)", fb->height1 + 1);
|
||||
pandecode_prop("width2 = MALI_POSITIVE(%d)", fb->width2 + 1);
|
||||
pandecode_prop("height2 = MALI_POSITIVE(%d)", fb->height2 + 1);
|
||||
|
||||
pandecode_prop("unk1 = 0x%x", fb->unk1);
|
||||
pandecode_prop("unk2 = 0x%x", fb->unk2);
|
||||
pandecode_prop("rt_count_1 = MALI_POSITIVE(%d)", fb->rt_count_1 + 1);
|
||||
pandecode_prop("rt_count_2 = %d", fb->rt_count_2);
|
||||
|
||||
pandecode_log(".mfbd_flags = ");
|
||||
pandecode_log_decoded_flags(mfbd_flag_info, fb->mfbd_flags);
|
||||
pandecode_log_cont(",\n");
|
||||
|
||||
if (fb->clear_stencil)
|
||||
pandecode_prop("clear_stencil = 0x%x", fb->clear_stencil);
|
||||
|
||||
if (fb->clear_depth)
|
||||
pandecode_prop("clear_depth = %f", fb->clear_depth);
|
||||
|
||||
if (!is_compute)
|
||||
if (is_bifrost)
|
||||
pandecode_bifrost_tiler_descriptor(fb);
|
||||
else {
|
||||
const struct mali_midgard_tiler_packed t = fb->tiler;
|
||||
const struct mali_midgard_tiler_weights_packed w = fb->tiler_weights;
|
||||
pandecode_midgard_tiler_descriptor(&t, &w, fb->width1 + 1, fb->height1 + 1, is_fragment, true);
|
||||
if (!is_compute) {
|
||||
if (is_bifrost) {
|
||||
DUMP_SECTION(MULTI_TARGET_FRAMEBUFFER, BIFROST_TILER_POINTER, fb, "Tiler Pointer");
|
||||
} else {
|
||||
const void *t = pan_section_ptr(fb, MULTI_TARGET_FRAMEBUFFER, TILER);
|
||||
const void *w = pan_section_ptr(fb, MULTI_TARGET_FRAMEBUFFER, TILER_WEIGHTS);
|
||||
pandecode_midgard_tiler_descriptor(t, w, params.width, params.height, is_fragment, true);
|
||||
}
|
||||
else
|
||||
} else {
|
||||
pandecode_msg("XXX: skipping compute MFBD, fixme\n");
|
||||
}
|
||||
|
||||
if (fb->zero3 || fb->zero4) {
|
||||
pandecode_msg("XXX: framebuffer zeros tripped\n");
|
||||
pandecode_prop("zero3 = 0x%" PRIx32, fb->zero3);
|
||||
pandecode_prop("zero4 = 0x%" PRIx32, fb->zero4);
|
||||
if (is_bifrost) {
|
||||
pan_section_unpack(fb, MULTI_TARGET_FRAMEBUFFER, BIFROST_PADDING, padding);
|
||||
}
|
||||
|
||||
pandecode_indent--;
|
||||
pandecode_log("};\n");
|
||||
pandecode_log("\n");
|
||||
|
||||
gpu_va += sizeof(struct mali_framebuffer);
|
||||
gpu_va += MALI_MULTI_TARGET_FRAMEBUFFER_LENGTH;
|
||||
|
||||
info.has_extra = (fb->mfbd_flags & MALI_MFBD_EXTRA) && is_fragment;
|
||||
info.has_extra = params.has_zs_crc_extension;
|
||||
|
||||
if (info.has_extra) {
|
||||
mem = pandecode_find_mapped_gpu_mem_containing(gpu_va);
|
||||
const struct mali_framebuffer_extra *PANDECODE_PTR_VAR(fbx, mem, (mali_ptr) gpu_va);
|
||||
struct pandecode_mapped_memory *mem =
|
||||
pandecode_find_mapped_gpu_mem_containing(gpu_va);
|
||||
const struct mali_zs_crc_extension_packed *PANDECODE_PTR_VAR(zs_crc, mem, (mali_ptr)gpu_va);
|
||||
DUMP_CL(ZS_CRC_EXTENSION, zs_crc, "ZS CRC Extension:\n");
|
||||
pandecode_log("\n");
|
||||
|
||||
pandecode_log("struct mali_framebuffer_extra fb_extra_%"PRIx64"_%d = {\n", gpu_va, job_no);
|
||||
pandecode_indent++;
|
||||
|
||||
MEMORY_PROP(fbx, checksum);
|
||||
|
||||
if (fbx->checksum_stride)
|
||||
pandecode_prop("checksum_stride = %d", fbx->checksum_stride);
|
||||
|
||||
pandecode_log(".flags_hi = ");
|
||||
pandecode_log_decoded_flags(mfbd_extra_flag_hi_info, fbx->flags_hi);
|
||||
pandecode_log_cont(",\n");
|
||||
|
||||
pandecode_log(".flags_lo = ");
|
||||
pandecode_log_decoded_flags(mfbd_extra_flag_lo_info, fbx->flags_lo);
|
||||
pandecode_log_cont(",\n");
|
||||
|
||||
pandecode_prop("zs_block = %s", mali_block_format_as_str(fbx->zs_block));
|
||||
pandecode_prop("zs_samples = MALI_POSITIVE(%u)", fbx->zs_samples + 1);
|
||||
|
||||
if (fbx->zs_block == MALI_BLOCK_FORMAT_AFBC) {
|
||||
pandecode_log(".ds_afbc = {\n");
|
||||
pandecode_indent++;
|
||||
|
||||
MEMORY_PROP_DIR(fbx->ds_afbc, depth_stencil_afbc_metadata);
|
||||
pandecode_prop("depth_stencil_afbc_stride = %d",
|
||||
fbx->ds_afbc.depth_stencil_afbc_stride);
|
||||
MEMORY_PROP_DIR(fbx->ds_afbc, depth_stencil);
|
||||
|
||||
pandecode_log(".flags = ");
|
||||
pandecode_log_decoded_flags(afbc_fmt_flag_info, fbx->ds_afbc.flags);
|
||||
pandecode_log_cont(",\n");
|
||||
|
||||
if (fbx->ds_afbc.padding) {
|
||||
pandecode_msg("XXX: Depth/stencil AFBC zeros tripped\n");
|
||||
pandecode_prop("padding = 0x%" PRIx64, fbx->ds_afbc.padding);
|
||||
}
|
||||
|
||||
pandecode_indent--;
|
||||
pandecode_log("},\n");
|
||||
} else {
|
||||
pandecode_log(".ds_linear = {\n");
|
||||
pandecode_indent++;
|
||||
|
||||
if (fbx->ds_linear.depth) {
|
||||
MEMORY_PROP_DIR(fbx->ds_linear, depth);
|
||||
pandecode_prop("depth_stride = %d",
|
||||
fbx->ds_linear.depth_stride);
|
||||
pandecode_prop("depth_layer_stride = %d",
|
||||
fbx->ds_linear.depth_layer_stride);
|
||||
} else if (fbx->ds_linear.depth_stride || fbx->ds_linear.depth_layer_stride) {
|
||||
pandecode_msg("XXX: depth stride zero tripped %d %d\n", fbx->ds_linear.depth_stride, fbx->ds_linear.depth_layer_stride);
|
||||
}
|
||||
|
||||
if (fbx->ds_linear.stencil) {
|
||||
MEMORY_PROP_DIR(fbx->ds_linear, stencil);
|
||||
pandecode_prop("stencil_stride = %d",
|
||||
fbx->ds_linear.stencil_stride);
|
||||
pandecode_prop("stencil_layer_stride = %d",
|
||||
fbx->ds_linear.stencil_layer_stride);
|
||||
} else if (fbx->ds_linear.stencil_stride || fbx->ds_linear.stencil_layer_stride) {
|
||||
pandecode_msg("XXX: stencil stride zero tripped %d %d\n", fbx->ds_linear.stencil_stride, fbx->ds_linear.stencil_layer_stride);
|
||||
}
|
||||
|
||||
if (fbx->ds_linear.depth_stride_zero ||
|
||||
fbx->ds_linear.stencil_stride_zero) {
|
||||
pandecode_msg("XXX: Depth/stencil zeros tripped\n");
|
||||
pandecode_prop("depth_stride_zero = 0x%x",
|
||||
fbx->ds_linear.depth_stride_zero);
|
||||
pandecode_prop("stencil_stride_zero = 0x%x",
|
||||
fbx->ds_linear.stencil_stride_zero);
|
||||
}
|
||||
|
||||
pandecode_indent--;
|
||||
pandecode_log("},\n");
|
||||
}
|
||||
|
||||
if (fbx->clear_color_1 | fbx->clear_color_2) {
|
||||
pandecode_prop("clear_color_1 = 0x%" PRIx32, fbx->clear_color_1);
|
||||
pandecode_prop("clear_color_2 = 0x%" PRIx32, fbx->clear_color_2);
|
||||
}
|
||||
|
||||
if (fbx->zero3) {
|
||||
pandecode_msg("XXX: fb_extra zeros tripped\n");
|
||||
pandecode_prop("zero3 = 0x%" PRIx64, fbx->zero3);
|
||||
}
|
||||
|
||||
pandecode_indent--;
|
||||
pandecode_log("};\n");
|
||||
|
||||
gpu_va += sizeof(struct mali_framebuffer_extra);
|
||||
gpu_va += MALI_ZS_CRC_EXTENSION_LENGTH;
|
||||
}
|
||||
|
||||
if (is_fragment)
|
||||
pandecode_render_target(gpu_va, job_no, fb);
|
||||
pandecode_render_target(gpu_va, job_no, is_bifrost, gpu_id, ¶ms);
|
||||
|
||||
return info;
|
||||
}
|
||||
|
|
@ -1412,8 +1110,9 @@ pandecode_vertex_tiler_postfix_pre(
|
|||
|
||||
if (is_bifrost)
|
||||
pandecode_compute_fbd(p->shared & ~1, job_no);
|
||||
else if (p->shared & MALI_MFBD)
|
||||
fbd_info = pandecode_mfbd_bfr((u64) ((uintptr_t) p->shared) & FBD_MASK, job_no, false, job_type == MALI_JOB_TYPE_COMPUTE, false);
|
||||
else if (p->shared & MALI_FBD_TAG_IS_MFBD)
|
||||
fbd_info = pandecode_mfbd_bfr((u64) ((uintptr_t) p->shared) & ~MALI_FBD_TAG_MASK,
|
||||
job_no, false, job_type == MALI_JOB_TYPE_COMPUTE, is_bifrost, gpu_id);
|
||||
else if (job_type == MALI_JOB_TYPE_COMPUTE)
|
||||
pandecode_compute_fbd((u64) (uintptr_t) p->shared, job_no);
|
||||
else
|
||||
|
|
@ -1509,7 +1208,8 @@ pandecode_vertex_tiler_postfix_pre(
|
|||
/* MRT blend fields are used whenever MFBD is used, with
|
||||
* per-RT descriptors */
|
||||
|
||||
if (job_type == MALI_JOB_TYPE_TILER && (is_bifrost || p->shared & MALI_MFBD)) {
|
||||
if (job_type == MALI_JOB_TYPE_TILER &&
|
||||
(is_bifrost || p->shared & MALI_FBD_TAG_IS_MFBD)) {
|
||||
void* blend_base = ((void *) cl) + MALI_STATE_LENGTH;
|
||||
|
||||
for (unsigned i = 0; i < fbd_info.rt_count; i++) {
|
||||
|
|
@ -1706,7 +1406,7 @@ pandecode_fragment_job(const struct pandecode_mapped_memory *mem,
|
|||
{
|
||||
const struct mali_payload_fragment *PANDECODE_PTR_VAR(s, mem, payload);
|
||||
|
||||
bool is_mfbd = s->framebuffer & MALI_MFBD;
|
||||
bool is_mfbd = s->framebuffer & MALI_FBD_TAG_IS_MFBD;
|
||||
|
||||
if (!is_mfbd && is_bifrost)
|
||||
pandecode_msg("XXX: Bifrost fragment must use MFBD\n");
|
||||
|
|
@ -1714,20 +1414,22 @@ pandecode_fragment_job(const struct pandecode_mapped_memory *mem,
|
|||
struct pandecode_fbd info;
|
||||
|
||||
if (is_mfbd)
|
||||
info = pandecode_mfbd_bfr(s->framebuffer & FBD_MASK, job_no, true, false, is_bifrost);
|
||||
info = pandecode_mfbd_bfr(s->framebuffer & ~MALI_FBD_TAG_MASK, job_no,
|
||||
true, false, is_bifrost, gpu_id);
|
||||
else
|
||||
info = pandecode_sfbd(s->framebuffer & FBD_MASK, job_no, true, gpu_id);
|
||||
info = pandecode_sfbd(s->framebuffer & ~MALI_FBD_TAG_MASK, job_no,
|
||||
true, gpu_id);
|
||||
|
||||
/* Compute the tag for the tagged pointer. This contains the type of
|
||||
* FBD (MFBD/SFBD), and in the case of an MFBD, information about which
|
||||
* additional structures follow the MFBD header (an extra payload or
|
||||
* not, as well as a count of render targets) */
|
||||
|
||||
unsigned expected_tag = is_mfbd ? MALI_MFBD : 0;
|
||||
unsigned expected_tag = is_mfbd ? MALI_FBD_TAG_IS_MFBD : 0;
|
||||
|
||||
if (is_mfbd) {
|
||||
if (info.has_extra)
|
||||
expected_tag |= MALI_MFBD_TAG_EXTRA;
|
||||
expected_tag |= MALI_FBD_TAG_HAS_ZS_RT;
|
||||
|
||||
expected_tag |= (MALI_POSITIVE(info.rt_count) << 2);
|
||||
}
|
||||
|
|
@ -1780,7 +1482,7 @@ pandecode_fragment_job(const struct pandecode_mapped_memory *mem,
|
|||
|
||||
/* The FBD is a tagged pointer */
|
||||
|
||||
unsigned tag = (s->framebuffer & ~FBD_MASK);
|
||||
unsigned tag = (s->framebuffer & MALI_FBD_TAG_MASK);
|
||||
|
||||
if (tag != expected_tag)
|
||||
pandecode_msg("XXX: expected FBD tag %X but got %X\n", expected_tag, tag);
|
||||
|
|
|
|||
|
|
@ -186,6 +186,14 @@
|
|||
<value name="AFBC" value="3"/>
|
||||
</enum>
|
||||
|
||||
<enum name="Block Format v7">
|
||||
<value name="No Write" value="0"/>
|
||||
<value name="Tiled U-Interleaved" value="1"/>
|
||||
<value name="Linear" value="2"/>
|
||||
<value name="AFBC" value="12"/>
|
||||
<value name="AFBC Tiled" value="13"/>
|
||||
</enum>
|
||||
|
||||
<enum name="Mipmap Mode">
|
||||
<value name="Nearest" value="0"/>
|
||||
<value name="None" value="1"/>
|
||||
|
|
@ -637,6 +645,37 @@
|
|||
<value name="A1B5G5R5" value="29"/>
|
||||
</enum>
|
||||
|
||||
<enum name="MFBD Color Format">
|
||||
<value name="RAW8" value="0"/>
|
||||
<value name="RAW16" value="1"/>
|
||||
<value name="RAW24" value="2"/>
|
||||
<value name="RAW32" value="3"/>
|
||||
<value name="RAW48" value="4"/>
|
||||
<value name="RAW64" value="5"/>
|
||||
<value name="RAW96" value="6"/>
|
||||
<value name="RAW128" value="7"/>
|
||||
<value name="RAW192" value="8"/>
|
||||
<value name="RAW256" value="9"/>
|
||||
<value name="RAW384" value="10"/>
|
||||
<value name="RAW512" value="11"/>
|
||||
<value name="RAW768" value="12"/>
|
||||
<value name="RAW1024" value="13"/>
|
||||
<value name="RAW1536" value="14"/>
|
||||
<value name="RAW2048" value="15"/>
|
||||
<value name="R8" value="16"/>
|
||||
<value name="R8G8" value="17"/>
|
||||
<value name="R8G8B8" value="18"/>
|
||||
<value name="R8G8B8A8" value="19"/>
|
||||
<value name="R4G4B4A4" value="20"/>
|
||||
<value name="R5G6B5" value="21"/>
|
||||
<value name="R8G8B8_FROM_R8G8B8A2" value="22"/>
|
||||
<value name="R10G10B10A2" value="24"/>
|
||||
<value name="A2B10G10R10" value="25"/>
|
||||
<value name="R5G5B5A1" value="28"/>
|
||||
<value name="A1B5G5R5" value="29"/>
|
||||
<value name="NATIVE" value="31"/>
|
||||
</enum>
|
||||
|
||||
<enum name="Downsampling Accumulation Mode">
|
||||
<value name="Unsigned normalized integer" value="0"/>
|
||||
<value name="Signed normalized integer" value="1"/>
|
||||
|
|
@ -661,6 +700,10 @@
|
|||
<value name="D32_S8X24" value="15"/>
|
||||
</enum>
|
||||
|
||||
<enum name="ZS Preload Format">
|
||||
<value name="D32_S8X24" value="4"/>
|
||||
</enum>
|
||||
|
||||
<enum name="S Format">
|
||||
<value name="S8" value="1"/>
|
||||
<value name="S8X8" value="2"/>
|
||||
|
|
@ -760,6 +803,206 @@
|
|||
<value name="D3D 16x Grid" value="4"/>
|
||||
</enum>
|
||||
|
||||
<enum name="Z Internal Format">
|
||||
<value name="D16" value="0"/>
|
||||
<value name="D24" value="1"/>
|
||||
<value name="D32" value="2"/>
|
||||
</enum>
|
||||
|
||||
<enum name="FBD Tag">
|
||||
<value name="IS_MFBD" value="1"/>
|
||||
<value name="HAS_ZS_RT" value="2"/>
|
||||
<value name="MASK" value="63"/>
|
||||
</enum>
|
||||
|
||||
<struct name="Multi-Target Framebuffer Parameters">
|
||||
<field name="Width" size="16" start="0:0" type="uint" modifier="minus(1)"/>
|
||||
<field name="Height" size="16" start="0:16" type="uint" modifier="minus(1)"/>
|
||||
<field name="Bound Min X" size="16" start="1:0" type="uint"/>
|
||||
<field name="Bound Min Y" size="16" start="1:16" type="uint"/>
|
||||
<field name="Bound Max X" size="16" start="2:0" type="uint"/>
|
||||
<field name="Bound Max Y" size="16" start="2:16" type="uint"/>
|
||||
<field name="Sample Count" size="3" start="3:0" type="uint" default="1" modifier="log2"/>
|
||||
<field name="Sample Pattern" size="3" start="3:3" type="Sample Pattern"/>
|
||||
<field name="Tie-Break Rule" size="3" start="3:6" type="Tie-Break Rule"/>
|
||||
<field name="Effective Tile Size" size="4" start="3:9" type="uint" modifier="log2"/>
|
||||
<field name="X Downsampling Scale" size="3" start="3:13" type="uint"/>
|
||||
<field name="Y Downsampling Scale" size="3" start="3:16" type="uint"/>
|
||||
<field name="Render Target Count" size="4" start="3:19" type="uint" modifier="minus(1)"/>
|
||||
<field name="Color Buffer Allocation" size="8" start="3:24" type="uint" modifier="shr(10)"/>
|
||||
<field name="S Clear" size="8" start="4:0" type="uint"/>
|
||||
<field name="S Write Enable" size="1" start="4:8" type="bool"/>
|
||||
<field name="S Preload Enable" size="1" start="4:9" type="bool"/>
|
||||
<field name="S Unload Enable" size="1" start="4:10" type="bool"/>
|
||||
<field name="Z Internal Format" size="2" start="4:16" type="Z Internal Format"/>
|
||||
<field name="Z Write Enable" size="1" start="4:18" type="bool"/>
|
||||
<field name="Z Preload Enable" size="1" start="4:19" type="bool"/>
|
||||
<field name="Z Unload Enable" size="1" start="4:20" type="bool"/>
|
||||
<field name="Has ZS CRC Extension" size="1" start="4:21" type="bool"/>
|
||||
<field name="CRC Read Enable" size="1" start="4:30" type="bool"/>
|
||||
<field name="CRC Write Enable" size="1" start="4:31" type="bool"/>
|
||||
<field name="Z Clear" size="32" start="5:0" type="float"/>
|
||||
</struct>
|
||||
|
||||
<struct name="ZS CRC Extension">
|
||||
<field name="CRC Base" size="64" start="0:0" type="address"/>
|
||||
<field name="CRC Row Stride" size="32" start="2:0" type="uint"/>
|
||||
<field name="ZS Write Format" size="4" start="3:0" type="ZS Format"/>
|
||||
<field name="ZS Block Format" size="2" start="3:4" type="Block Format"/>
|
||||
<field name="ZS Block Format v7" size="2" start="3:4" type="Block Format v7"/>
|
||||
<field name="ZS MSAA" size="2" start="3:6" default="Single" type="MSAA"/>
|
||||
<field name="ZS Big Endian" size="1" start="3:8" type="bool"/>
|
||||
<field name="ZS Clean Pixel Write Enable" size="1" start="3:10" type="bool"/>
|
||||
<field name="CRC Render Target" size="4" start="3:11" type="uint"/>
|
||||
<field name="S Write Format" size="4" start="3:16" type="S Format"/>
|
||||
<field name="S Block Format" size="2" start="3:20" type="Block Format"/>
|
||||
<field name="S MSAA" size="2" start="3:22" default="Single" type="MSAA"/>
|
||||
<field name="ZS Preload Format" size="4" start="3:28" type="ZS Preload Format"/>
|
||||
<field name="ZS Writeback Base" size="64" start="4:0" type="address"/>
|
||||
<field name="ZS Writeback Row Stride" size="32" start="6:0" type="uint"/>
|
||||
<field name="ZS Writeback Surface Stride" size="32" start="7:0" type="uint"/>
|
||||
<field name="S Writeback Base" size="64" start="8:0" type="address"/>
|
||||
<field name="S Writeback Row Stride" size="32" start="10:0" type="uint"/>
|
||||
<field name="S Writeback Surface Stride" size="32" start="11:0" type="uint"/>
|
||||
<field name="ZS AFBC Header" size="64" start="4:0" type="address"/>
|
||||
<field name="ZS AFBC Row Stride" size="13" start="6:0" type="uint"/>
|
||||
<field name="ZS AFBC Chunk Size" size="12" start="7:0" type="uint"/>
|
||||
<field name="ZS AFBC Sparse" size="1" start="7:16" type="bool"/>
|
||||
<field name="ZS AFBC Body" size="64" start="8:0" type="address"/>
|
||||
<field name="ZS AFBC Body Size" size="32" start="10:0" type="uint"/>
|
||||
<field name="ZS Preload Base" size="64" start="12:0" type="address"/>
|
||||
<field name="ZS Preload Row Stride" size="32" start="14:0" type="uint"/>
|
||||
<field name="ZS Preload Surface Stride" size="32" start="15:0" type="uint"/>
|
||||
<field name="CRC Clear Color" size="64" start="12:0" type="uint"/>
|
||||
</struct>
|
||||
|
||||
<enum name="RT Endianness">
|
||||
<value name="Little Endian" value="0"/>
|
||||
<value name="Big Endian 2B" value="1"/>
|
||||
<value name="Big Endian 4B" value="2"/>
|
||||
<value name="Big Endian 8B" value="3"/>
|
||||
</enum>
|
||||
|
||||
<enum name="YUV Conv K6">
|
||||
<value name="0" value="0"/>
|
||||
<value name="16" value="1"/>
|
||||
</enum>
|
||||
|
||||
<enum name="YUV Conv K7 Clamp">
|
||||
<value name="MINUS_128_TO_127" value="0"/>
|
||||
<value name="MINUS_112_TO_111" value="1"/>
|
||||
<value name="0_TO_255" value="2"/>
|
||||
<value name="16_TO_239" value="3"/>
|
||||
</enum>
|
||||
|
||||
<enum name="YUV Conv K8">
|
||||
<value name="220" value="0"/>
|
||||
<value name="256" value="1"/>
|
||||
</enum>
|
||||
|
||||
<enum name="YUV Swizzle">
|
||||
<value name="YUVA" value="0"/>
|
||||
<value name="YVUA" value="1"/>
|
||||
<value name="UYVA" value="2"/>
|
||||
<value name="UVYA" value="3"/>
|
||||
<value name="VUYA" value="4"/>
|
||||
<value name="VYUA" value="5"/>
|
||||
<value name="Y00A" value="6"/>
|
||||
<value name="YXXA" value="7"/>
|
||||
</enum>
|
||||
|
||||
<enum name="YUV Conversion Mode">
|
||||
<value name="No Conversion" value="0"/>
|
||||
<value name="BT 601" value="3"/>
|
||||
<value name="BT 709" value="4"/>
|
||||
<value name="BT 2020" value="6"/>
|
||||
</enum>
|
||||
|
||||
<enum name="YUV Cr Siting">
|
||||
<value name="Co-Sited" value="0"/>
|
||||
<value name="Center Y" value="1"/>
|
||||
<value name="Center X" value="2"/>
|
||||
<value name="Center" value="3"/>
|
||||
<value name="One Quarter" value="4"/>
|
||||
<value name="Three Quarters" value="5"/>
|
||||
</enum>
|
||||
|
||||
<struct name="Render Target">
|
||||
<field name="Internal Buffer Offset" size="12" start="0:4" type="uint" modifier="shr(4)"/>
|
||||
<field name="YUV Enable" size="1" start="0:24" type="bool"/>
|
||||
<field name="Dithered Clear" size="1" start="0:25" type="bool"/>
|
||||
<field name="Internal Format" size="6" start="0:26" type="Color Buffer Internal Format"/>
|
||||
<field name="Write Enable" size="1" start="1:0" type="bool"/>
|
||||
<field name="Writeback Format" size="5" start="1:3" type="MFBD Color Format"/>
|
||||
<field name="Writeback Endianness" size="2" start="1:8" type="RT Endianness"/>
|
||||
<field name="Writeback Block Format" size="2" start="1:10" type="Block Format"/>
|
||||
<field name="Writeback Block Format v7" size="4" start="1:8" type="Block Format v7"/>
|
||||
<field name="Writeback MSAA" size="2" start="1:12" type="MSAA"/>
|
||||
<field name="sRGB" size="1" start="1:14" type="bool"/>
|
||||
<field name="Dithering Enable" size="1" start="1:15" type="bool"/>
|
||||
<field name="Swizzle" size="12" start="1:16" type="uint"/>
|
||||
<field name="Writeback Sampling Mode" size="2" start="1:29" type="Downsampling Accumulation Mode"/>
|
||||
<field name="Clean Pixel Write Enable" size="1" start="1:31" type="bool"/>
|
||||
<field name="Preload Enable" size="1" start="2:0" type="bool"/>
|
||||
<field name="Unload Enable" size="1" start="2:1" type="bool"/>
|
||||
<field name="Preload Format" size="5" start="2:3" type="MFBD Color Format"/>
|
||||
<field name="Preload Endianness" size="2" start="2:8" type="RT Endianness"/>
|
||||
<field name="Preload Block Format" size="4" start="2:10" type="Block Format"/>
|
||||
<field name="Preload MSAA" size="2" start="2:14" type="MSAA"/>
|
||||
<field name="YUV Conv K5" size="8" start="2:16" type="uint"/>
|
||||
<field name="YUV Swizzle" size="3" start="2:16" type="YUV Swizzle"/>
|
||||
<field name="YUV Full Range" size="1" start="2:20" type="bool"/>
|
||||
<field name="YUV Conversion Mode" size="4" start="2:21" type="YUV Conversion Mode"/>
|
||||
<field name="YUV Cr Siting" size="3" start="2:25" type="YUV Cr Siting"/>
|
||||
<field name="YUV Unsigned Cr Range" size="1" start="2:28" type="bool"/>
|
||||
<field name="YUV Conv K6" size="1" start="2:24" type="YUV Conv K6"/>
|
||||
<field name="YUV Conv K7 Clamp" size="2" start="2:25" type="YUV Conv K7 Clamp"/>
|
||||
<field name="YUV Conv K8" size="1" start="2:27" type="YUV Conv K8"/>
|
||||
<field name="YUV Conv Disable" size="1" start="2:31" type="bool"/>
|
||||
<field name="YUV Conv K1" size="8" start="3:0" type="uint"/>
|
||||
<field name="YUV Conv K2" size="8" start="3:8" type="uint"/>
|
||||
<field name="YUV Conv K3" size="8" start="3:16" type="uint"/>
|
||||
<field name="YUV Conv K4" size="8" start="3:24" type="uint"/>
|
||||
<field name="YUV Plane 0 Base" size="64" start="4:0" type="address"/>
|
||||
<field name="YUV Plane 1 Base" size="64" start="6:0" type="address"/>
|
||||
<field name="YUV Plane 2 Base" size="64" start="8:0" type="address"/>
|
||||
<field name="YUV Plane 0 Stride" size="32" start="10:0" type="uint"/>
|
||||
<field name="YUV Plane 1 2 Stride" size="32" start="11:0" type="uint"/>
|
||||
<field name="AFBC Header" size="64" start="4:0" type="address"/>
|
||||
<field name="AFBC Row Stride" size="13" start="6:0" type="uint"/>
|
||||
<field name="AFBC Chunk Size" size="12" start="7:0" type="uint"/>
|
||||
<field name="AFBC Sparse" size="1" start="7:16" type="bool"/>
|
||||
<field name="AFBC YUV Transform Enable" size="1" start="7:17" type="bool"/>
|
||||
<field name="AFBC Split Block Enable" size="1" start="7:18" type="bool"/>
|
||||
<field name="AFBC Wide Block Enable" size="1" start="7:19" type="bool"/>
|
||||
<field name="AFBC Body" size="64" start="8:0" type="address"/>
|
||||
<field name="AFBC Body Size" size="32" start="10:0" type="uint"/>
|
||||
<field name="Writeback Base" size="64" start="8:0" type="address"/>
|
||||
<field name="Writeback Row Stride" size="32" start="10:0" type="uint"/>
|
||||
<field name="Writeback Surface Stride" size="32" start="11:0" type="uint"/>
|
||||
<field name="Preload Base" size="64" start="12:0" type="address"/>
|
||||
<field name="Preload Row Stride" size="32" start="14:0" type="uint"/>
|
||||
<field name="Preload Surface Stride" size="32" start="15:0" type="uint"/>
|
||||
<field name="Clear Color 0" size="32" start="12:0" type="uint"/>
|
||||
<field name="Clear Color 1" size="32" start="13:0" type="uint"/>
|
||||
<field name="Clear Color 2" size="32" start="14:0" type="uint"/>
|
||||
<field name="Clear Color 3" size="32" start="15:0" type="uint"/>
|
||||
</struct>
|
||||
|
||||
<enum name="Pre Post Frame Shader Mode">
|
||||
<value name="Never" value="0"/>
|
||||
<value name="Always" value="1"/>
|
||||
<value name="Intersect" value="2"/>
|
||||
</enum>
|
||||
|
||||
<struct name="Bifrost Framebuffer Parameters">
|
||||
<field name="Pre Frame 0" size="3" start="0:0" type="Pre Post Frame Shader Mode"/>
|
||||
<field name="Pre Frame 1" size="3" start="0:3" type="Pre Post Frame Shader Mode"/>
|
||||
<field name="Post Frame" size="3" start="0:6" type="Pre Post Frame Shader Mode"/>
|
||||
<field name="Sample Locations" size="64" start="4:0" type="address"/>
|
||||
<field name="Frame Shader DCDs" size="64" start="6:0" type="address"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Bifrost Tiler Heap">
|
||||
<field name="Size" size="32" start="1:0" type="uint" modifier="align(4096)"/>
|
||||
<field name="Base" size="64" start="2:0" type="address"/>
|
||||
|
|
@ -781,4 +1024,21 @@
|
|||
<field name="Heap" size="64" start="6:0" type="address"/>
|
||||
<field name="Weights" size="32" start="8:0" type="Bifrost Tiler Weights" elements="8"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Bifrost Tiler Pointer">
|
||||
<field name="Address" size="64" start="0:0" type="address"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Bifrost Framebuffer Padding" size="16">
|
||||
</struct>
|
||||
|
||||
<aggregate name="Multi-Target Framebuffer">
|
||||
<section name="Local Storage" offset="0" type="Local Storage"/>
|
||||
<section name="Bifrost Parameters" offset="0" type="Bifrost Framebuffer Parameters"/>
|
||||
<section name="Parameters" offset="32" type="Multi-Target Framebuffer Parameters"/>
|
||||
<section name="Tiler" offset="56" type="Midgard Tiler"/>
|
||||
<section name="Tiler Weights" offset="96" type="Midgard Tiler Weights"/>
|
||||
<section name="Bifrost Tiler Pointer" offset="56" type="Bifrost Tiler Pointer"/>
|
||||
<section name="Bifrost Padding" offset="64" type="Bifrost Framebuffer Padding"/>
|
||||
</aggregate>
|
||||
</panxml>
|
||||
|
|
|
|||
|
|
@ -408,3 +408,21 @@ panfrost_format_to_bifrost_blend(const struct util_format_description *desc)
|
|||
return format;
|
||||
}
|
||||
}
|
||||
|
||||
enum mali_z_internal_format
|
||||
panfrost_get_z_internal_format(enum pipe_format fmt)
|
||||
{
|
||||
switch (fmt) {
|
||||
case PIPE_FORMAT_Z16_UNORM:
|
||||
case PIPE_FORMAT_Z16_UNORM_S8_UINT:
|
||||
return MALI_Z_INTERNAL_FORMAT_D16;
|
||||
case PIPE_FORMAT_Z24_UNORM_S8_UINT:
|
||||
case PIPE_FORMAT_Z24X8_UNORM:
|
||||
return MALI_Z_INTERNAL_FORMAT_D24;
|
||||
case PIPE_FORMAT_Z32_FLOAT:
|
||||
case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
|
||||
return MALI_Z_INTERNAL_FORMAT_D32;
|
||||
default:
|
||||
unreachable("Unsupported depth/stencil format.");
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -147,6 +147,9 @@ extern struct panfrost_format panfrost_pipe_format_table[PIPE_FORMAT_COUNT];
|
|||
bool
|
||||
panfrost_is_z24s8_variant(enum pipe_format fmt);
|
||||
|
||||
enum mali_z_internal_format
|
||||
panfrost_get_z_internal_format(enum pipe_format fmt);
|
||||
|
||||
unsigned
|
||||
panfrost_translate_swizzle_4(const unsigned char swizzle[4]);
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue