fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-29 12:20:10 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

freedreno/ir3: Fix initial_variants_synchronous() condition

Browse source 
This was meant to be an || rather than &&, although it didn't matter for
shaderdb because both conditions would be true.  But it did matter if
you were trying to force synchronous compile to avoid having nir/ir3
prints interleaved from multiple threads.

While at it, add a more specific debug flag to force initial variant
compile to be synchronous, because at some point the 'shaderdb' flag
itself will not force this.

Fixes: 75b0c4b5e1 ("freedreno/ir3: Async shader compile")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9264>
This commit is contained in:
Rob Clark 2021-02-25 09:12:54 -08:00 • committed by Marge Bot
parent 1b2a35509e
commit 5d217774f2
3 changed files with 6 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
src/gallium/drivers/freedreno/freedreno_screen.c
View file

@ -74,8 +74,8 @@ static const struct debug_named_value fd_debug_options[] = {
{"nobypass", FD_DBG_NOBYPASS, "Disable GMEM bypass"},
{"perf", FD_DBG_PERF, "Enable performance warnings"},
{"nobin", FD_DBG_NOBIN, "Disable hw binning"},
{"nogmem", FD_DBG_NOGMEM, "Disable GMEM rendering (bypass only)"},
/* BIT(10) */
{"nogmem", FD_DBG_NOGMEM, "Disable GMEM rendering (bypass only)"},
{"serialc", FD_DBG_SERIALC,"Disable asynchronous shader compile"},
{"shaderdb", FD_DBG_SHADERDB, "Enable shaderdb output"},
{"flush", FD_DBG_FLUSH, "Force flush after every draw"},
{"deqp", FD_DBG_DEQP, "Enable dEQP hacks"},

2
src/gallium/drivers/freedreno/freedreno_util.h
View file

@ -72,7 +72,7 @@ enum fd_debug_flag {
FD_DBG_PERF = BITFIELD_BIT(7),
FD_DBG_NOBIN = BITFIELD_BIT(8),
FD_DBG_NOGMEM = BITFIELD_BIT(9),
/* BIT(10) */
FD_DBG_SERIALC = BITFIELD_BIT(10),
FD_DBG_SHADERDB = BITFIELD_BIT(11),
FD_DBG_FLUSH = BITFIELD_BIT(12),
FD_DBG_DEQP = BITFIELD_BIT(13),

4
src/gallium/drivers/freedreno/ir3/ir3_gallium.c
View file

@ -67,7 +67,9 @@ struct ir3_shader_state {
static bool
initial_variants_synchronous(struct fd_context *ctx)
{
return unlikely(ctx->debug.debug_message && (fd_mesa_debug & FD_DBG_SHADERDB));
return unlikely(ctx->debug.debug_message ||
(fd_mesa_debug & FD_DBG_SHADERDB)) ||
(fd_mesa_debug & FD_DBG_SERIALC);
}
static void