freedreno/ir3: Apply the a6xx samgq workaround to TES/TCS/GS as well.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12454>
This commit is contained in:
Emma Anholt 2021-08-18 12:34:01 -07:00 committed by Marge Bot
parent a6a449837b
commit 5d192c2036
2 changed files with 3 additions and 4 deletions

View file

@ -53,8 +53,6 @@ KHR-GLES31.core.tessellation_shader.tessellation_shader_tc_barriers.barrier_guar
# no debug info in the qpa
KHR-GLES31.core.texture_cube_map_array.color_depth_attachments,Fail
# failures in GS,TCS,TES texturing
KHR-GLES31.core.texture_cube_map_array.sampling,Fail
# rendering errors in ~4x4 blocks around the bottom side of the diagonal for the quad
bypass-dEQP-GLES31.functional.blend_equation_advanced.msaa.colorburn,Fail

View file

@ -234,8 +234,9 @@ legalize_block(struct ir3_legalize_ctx *ctx, struct ir3_block *block)
if (list_is_empty(&block->instr_list) && (opc_cat(n->opc) >= 5))
ir3_NOP(block);
if (ctx->compiler->samgq_workaround && ctx->type == MESA_SHADER_VERTEX &&
n->opc == OPC_SAMGQ) {
if (ctx->compiler->samgq_workaround &&
ctx->type != MESA_SHADER_FRAGMENT &&
ctx->type != MESA_SHADER_COMPUTE && n->opc == OPC_SAMGQ) {
struct ir3_instruction *samgp;
list_delinit(&n->node);