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freedreno/ir3: Apply the a6xx samgq workaround to TES/TCS/GS as well.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12454>
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a6a449837b
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5d192c2036
2 changed files with 3 additions and 4 deletions
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@ -53,8 +53,6 @@ KHR-GLES31.core.tessellation_shader.tessellation_shader_tc_barriers.barrier_guar
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# no debug info in the qpa
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KHR-GLES31.core.texture_cube_map_array.color_depth_attachments,Fail
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# failures in GS,TCS,TES texturing
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KHR-GLES31.core.texture_cube_map_array.sampling,Fail
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# rendering errors in ~4x4 blocks around the bottom side of the diagonal for the quad
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bypass-dEQP-GLES31.functional.blend_equation_advanced.msaa.colorburn,Fail
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@ -234,8 +234,9 @@ legalize_block(struct ir3_legalize_ctx *ctx, struct ir3_block *block)
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if (list_is_empty(&block->instr_list) && (opc_cat(n->opc) >= 5))
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ir3_NOP(block);
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if (ctx->compiler->samgq_workaround && ctx->type == MESA_SHADER_VERTEX &&
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n->opc == OPC_SAMGQ) {
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if (ctx->compiler->samgq_workaround &&
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ctx->type != MESA_SHADER_FRAGMENT &&
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ctx->type != MESA_SHADER_COMPUTE && n->opc == OPC_SAMGQ) {
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struct ir3_instruction *samgp;
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list_delinit(&n->node);
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