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brw: add a NOP in between WHILE instructions on LNL
This is a workaround that is still in progress, see HSD 22020521218. If we don't have these NOPs we may see rendering corruption or even GPU hangs. While we still don't fully understand the issue from the hardware point of view, let's have this workaround so we can pass CTS and move things forward. If we need to change this later, we can. Besides, the impact is minimal. Shaderdb/fossilize report no changes for this patch. On our Blackops trace, the lack of this patch causes corruption in fog rendering (rectangles where fog was supposed to be shown don't show the fog). On dEQP-VK.graphicsfuzz.cov-array-copies-loops-with-limiters, without this patch we get a GPU hang. Backport-to: 24.2 Testcase: dEQP-VK.graphicsfuzz.cov-array-copies-loops-with-limiters Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11813 Reviewed-by: Ivan Briano <ivan.briano@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31331>
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1 changed files with 11 additions and 2 deletions
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@ -773,6 +773,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
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struct disasm_info *disasm_info = disasm_initialize(p->isa, cfg);
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struct disasm_info *disasm_info = disasm_initialize(p->isa, cfg);
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enum opcode prev_opcode = BRW_OPCODE_ILLEGAL;
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foreach_block_and_inst (block, fs_inst, inst, cfg) {
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foreach_block_and_inst (block, fs_inst, inst, cfg) {
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if (inst->opcode == SHADER_OPCODE_UNDEF)
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if (inst->opcode == SHADER_OPCODE_UNDEF)
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continue;
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continue;
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@ -1084,9 +1085,16 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
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break;
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break;
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case BRW_OPCODE_WHILE:
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case BRW_OPCODE_WHILE:
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brw_WHILE(p);
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/* On LNL and newer, if we don't put a NOP in between two consecutive
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* WHILE instructions we may end up with misrendering or GPU hangs.
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* See HSD 22020521218.
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*/
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if (devinfo->ver >= 20 && unlikely(prev_opcode == BRW_OPCODE_WHILE))
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brw_NOP(p);
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brw_WHILE(p);
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loop_count++;
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loop_count++;
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break;
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break;
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case SHADER_OPCODE_RCP:
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case SHADER_OPCODE_RCP:
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case SHADER_OPCODE_RSQ:
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case SHADER_OPCODE_RSQ:
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@ -1354,6 +1362,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
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case SHADER_OPCODE_LOAD_PAYLOAD:
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case SHADER_OPCODE_LOAD_PAYLOAD:
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unreachable("Should be lowered by lower_load_payload()");
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unreachable("Should be lowered by lower_load_payload()");
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}
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}
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prev_opcode = inst->opcode;
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if (multiple_instructions_emitted)
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if (multiple_instructions_emitted)
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continue;
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continue;
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