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radeonsi/gfx9: fix most things wrong with shader images

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There are 2 major hw changes:
- The address must always point to the address of level 0. GFX9 tiling
  modes don't allow binding to a non-0 level.
- 3D must always be bound as 3D, because 2D and 3D use entirely different
  tiling modes, and the texture target determines which set of modes is
  used.

Cc: 17.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák 2017-04-23 23:06:38 +02:00
parent 65e0c3fba7
commit 5c94779585
2 changed files with 24 additions and 12 deletions
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33
src/gallium/drivers/radeonsi/si_descriptors.c
View file

@ -765,7 +765,7 @@ static void si_set_shader_image(struct si_context *ctx,
static const unsigned char swizzle[4] = { 0, 1, 2, 3 };
struct r600_texture *tex = (struct r600_texture *)res;
unsigned level = view->u.tex.level;
unsigned width, height, depth;
unsigned width, height, depth, hw_level;
bool uses_dcc = vi_dcc_enabled(tex, level);
assert(!tex->is_depth);
@ -794,20 +794,31 @@ static void si_set_shader_image(struct si_context *ctx,
p_atomic_read(&tex->framebuffers_bound))
ctx->need_check_render_feedback = true;
/* Always force the base level to the selected level.
*
* This is required for 3D textures, where otherwise
* selecting a single slice for non-layered bindings
* fails. It doesn't hurt the other targets.
*/
width = u_minify(res->b.b.width0, level);
height = u_minify(res->b.b.height0, level);
depth = u_minify(res->b.b.depth0, level);
if (ctx->b.chip_class >= GFX9) {
/* Always set the base address. The swizzle modes don't
* allow setting mipmap level offsets as the base.
*/
width = res->b.b.width0;
height = res->b.b.height0;
depth = res->b.b.depth0;
hw_level = level;
} else {
/* Always force the base level to the selected level.
*
* This is required for 3D textures, where otherwise
* selecting a single slice for non-layered bindings
* fails. It doesn't hurt the other targets.
*/
width = u_minify(res->b.b.width0, level);
height = u_minify(res->b.b.height0, level);
depth = u_minify(res->b.b.depth0, level);
hw_level = 0;
}
si_make_texture_descriptor(screen, tex,
false, res->b.b.target,
view->format, swizzle,
0, 0,
hw_level, hw_level,
view->u.tex.first_layer,
view->u.tex.last_layer,
width, height, depth,

3
src/gallium/drivers/radeonsi/si_state.c
View file

@ -3189,7 +3189,8 @@ si_make_texture_descriptor(struct si_screen *screen,
if (!sampler &&
(res->target == PIPE_TEXTURE_CUBE ||
res->target == PIPE_TEXTURE_CUBE_ARRAY ||
res->target == PIPE_TEXTURE_3D)) {
(screen->b.chip_class <= VI &&
res->target == PIPE_TEXTURE_3D))) {
/* For the purpose of shader images, treat cube maps and 3D
* textures as 2D arrays. For 3D textures, the address
* calculations for mipmaps are different, so we rely on the