radeonsi: support more than 64 options for AMD_DEBUG

As we are going to add more debug options for mesh shader,
but now AMD_DEBUG options are full (=64).

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35931>

src/gallium/drivers/radeonsi/si_compute.c

@@ -16,7 +16,7 @@
 
 #define COMPUTE_DBG(sscreen, fmt, args...)                                                         \
    do {                                                                                            \
-      if ((sscreen->debug_flags & DBG(COMPUTE)))                                                   \
+      if ((sscreen->shader_debug_flags & DBG(COMPUTE)))                                            \
          fprintf(stderr, fmt, ##args);                                                             \
    } while (0);
 

src/gallium/drivers/radeonsi/si_get.c

@@ -1012,12 +1012,12 @@ void si_init_compute_caps(struct si_screen *sscreen)
 
    unsigned threads = 1024;
    unsigned subgroup_size =
-      sscreen->debug_flags & DBG(W64_CS) || sscreen->info.gfx_level < GFX10 ? 64 : 32;
+      sscreen->shader_debug_flags & DBG(W64_CS) || sscreen->info.gfx_level < GFX10 ? 64 : 32;
    caps->max_subgroups = threads / subgroup_size;
 
-   if (sscreen->debug_flags & DBG(W32_CS))
+   if (sscreen->shader_debug_flags & DBG(W32_CS))
       caps->subgroup_sizes = 32;
-   else if (sscreen->debug_flags & DBG(W64_CS))
+   else if (sscreen->shader_debug_flags & DBG(W64_CS))
       caps->subgroup_sizes = 64;
    else
       caps->subgroup_sizes = sscreen->info.gfx_level < GFX10 ? 64 : 64 | 32;

src/gallium/drivers/radeonsi/si_pipe.c

@@ -39,38 +39,6 @@
 static struct pipe_context *si_create_context(struct pipe_screen *screen, unsigned flags);
 
 static const struct debug_named_value radeonsi_debug_options[] = {
-   /* Shader logging options: */
-   {"vs", DBG(VS), "Print vertex shaders"},
-   {"ps", DBG(PS), "Print pixel shaders"},
-   {"gs", DBG(GS), "Print geometry shaders"},
-   {"tcs", DBG(TCS), "Print tessellation control shaders"},
-   {"tes", DBG(TES), "Print tessellation evaluation shaders"},
-   {"cs", DBG(CS), "Print compute shaders"},
-
-   {"initnir", DBG(INIT_NIR), "Print initial input NIR when shaders are created"},
-   {"nir", DBG(NIR), "Print final NIR after lowering when shader variants are created"},
-   {"initllvm", DBG(INIT_LLVM), "Print initial LLVM IR before optimizations"},
-   {"llvm", DBG(LLVM), "Print final LLVM IR"},
-   {"initaco", DBG(INIT_ACO), "Print initial ACO IR before optimizations"},
-   {"aco", DBG(ACO), "Print final ACO IR"},
-   {"asm", DBG(ASM), "Print final shaders in asm"},
-   {"stats", DBG(STATS), "Print shader-db stats to stderr"},
-
-   /* Shader compiler options the shader cache should be aware of: */
-   {"w32ge", DBG(W32_GE), "Use Wave32 for vertex, tessellation, and geometry shaders."},
-   {"w32ps", DBG(W32_PS), "Use Wave32 for pixel shaders."},
-   {"w32cs", DBG(W32_CS), "Use Wave32 for computes shaders."},
-   {"w64ge", DBG(W64_GE), "Use Wave64 for vertex, tessellation, and geometry shaders."},
-   {"w64ps", DBG(W64_PS), "Use Wave64 for pixel shaders."},
-   {"w64cs", DBG(W64_CS), "Use Wave64 for computes shaders."},
-
-   /* Shader compiler options (with no effect on the shader cache): */
-   {"checkir", DBG(CHECK_IR), "Enable additional sanity checks on shader IR"},
-   {"mono", DBG(MONOLITHIC_SHADERS), "Use old-style monolithic shaders compiled on demand"},
-   {"nooptvariant", DBG(NO_OPT_VARIANT), "Disable compiling optimized shader variants."},
-   {"useaco", DBG(USE_ACO), "Use ACO as shader compiler when possible"},
-   {"usellvm", DBG(USE_LLVM), "Use LLVM as shader compiler when possible"},
-
    /* Information logging options: */
    {"info", DBG(INFO), "Print driver information"},
    {"tex", DBG(TEX), "Print texture info"},
@@ -123,6 +91,40 @@ static const struct debug_named_value radeonsi_debug_options[] = {
    DEBUG_NAMED_VALUE_END /* must be last */
 };
 
+static const struct debug_named_value radeonsi_shader_debug_options[] = {
+   /* Shader logging options: */
+   {"vs", DBG(VS), "Print vertex shaders"},
+   {"ps", DBG(PS), "Print pixel shaders"},
+   {"gs", DBG(GS), "Print geometry shaders"},
+   {"tcs", DBG(TCS), "Print tessellation control shaders"},
+   {"tes", DBG(TES), "Print tessellation evaluation shaders"},
+   {"cs", DBG(CS), "Print compute shaders"},
+
+   {"initnir", DBG(INIT_NIR), "Print initial input NIR when shaders are created"},
+   {"nir", DBG(NIR), "Print final NIR after lowering when shader variants are created"},
+   {"initllvm", DBG(INIT_LLVM), "Print initial LLVM IR before optimizations"},
+   {"llvm", DBG(LLVM), "Print final LLVM IR"},
+   {"initaco", DBG(INIT_ACO), "Print initial ACO IR before optimizations"},
+   {"aco", DBG(ACO), "Print final ACO IR"},
+   {"asm", DBG(ASM), "Print final shaders in asm"},
+   {"stats", DBG(STATS), "Print shader-db stats to stderr"},
+
+   /* Shader compiler options the shader cache should be aware of: */
+   {"w32ge", DBG(W32_GE), "Use Wave32 for vertex, tessellation, and geometry shaders."},
+   {"w32ps", DBG(W32_PS), "Use Wave32 for pixel shaders."},
+   {"w32cs", DBG(W32_CS), "Use Wave32 for computes shaders."},
+   {"w64ge", DBG(W64_GE), "Use Wave64 for vertex, tessellation, and geometry shaders."},
+   {"w64ps", DBG(W64_PS), "Use Wave64 for pixel shaders."},
+   {"w64cs", DBG(W64_CS), "Use Wave64 for computes shaders."},
+
+   /* Shader compiler options (with no effect on the shader cache): */
+   {"checkir", DBG(CHECK_IR), "Enable additional sanity checks on shader IR"},
+   {"mono", DBG(MONOLITHIC_SHADERS), "Use old-style monolithic shaders compiled on demand"},
+   {"nooptvariant", DBG(NO_OPT_VARIANT), "Disable compiling optimized shader variants."},
+   {"useaco", DBG(USE_ACO), "Use ACO as shader compiler when possible"},
+   {"usellvm", DBG(USE_LLVM), "Use LLVM as shader compiler when possible"},
+};
+
 static const struct debug_named_value test_options[] = {
    /* Tests: */
    {"clearbuffer", DBG(TEST_CLEAR_BUFFER), "Test correctness of the clear_buffer compute shader"},
@@ -147,7 +149,7 @@ struct ac_llvm_compiler *si_create_llvm_compiler(struct si_screen *sscreen)
       return NULL;
 
    if (!ac_init_llvm_compiler(compiler, sscreen->info.family,
-                              sscreen->debug_flags & DBG(CHECK_IR) ? AC_TM_CHECK_IR : 0))
+                              sscreen->shader_debug_flags & DBG(CHECK_IR) ? AC_TM_CHECK_IR : 0))
       return NULL;
 
    compiler->beo = ac_create_backend_optimizer(compiler->tm);
@@ -957,7 +959,7 @@ static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen, v
 
    /* When shaders are logged to stderr, asynchronous compilation is
     * disabled too. */
-   if (sscreen->debug_flags & DBG_ALL_SHADERS)
+   if (sscreen->shader_debug_flags & DBG_ALL_SHADERS)
       return ctx;
 
    /* Use asynchronous flushes only on amdgpu, since the radeon
@@ -1124,7 +1126,7 @@ parse_hex(char *out, const char *in, unsigned length)
 static void si_disk_cache_create(struct si_screen *sscreen)
 {
    /* Don't use the cache if shader dumping is enabled. */
-   if (sscreen->debug_flags & DBG_ALL_SHADERS)
+   if (sscreen->shader_debug_flags & DBG_ALL_SHADERS)
       return;
 
    struct mesa_sha1 ctx;
@@ -1285,6 +1287,7 @@ static struct pipe_screen *radeonsi_screen_create_impl(struct radeon_winsys *ws,
    sscreen->context_roll_log_filename = debug_get_option("AMD_ROLLS", NULL);
    sscreen->debug_flags = debug_get_flags_option("R600_DEBUG", radeonsi_debug_options, 0);
    sscreen->debug_flags |= debug_get_flags_option("AMD_DEBUG", radeonsi_debug_options, 0);
+   sscreen->shader_debug_flags = debug_get_flags_option("AMD_DEBUG", radeonsi_shader_debug_options, 0);
    test_flags = debug_get_flags_option("AMD_TEST", test_options, 0);
 
    if (sscreen->debug_flags & DBG(NO_DISPLAY_DCC)) {
@@ -1306,10 +1309,10 @@ static struct pipe_screen *radeonsi_screen_create_impl(struct radeon_winsys *ws,
        (sscreen->info.gfx_level == GFX11_5 && LLVM_VERSION_MAJOR < 19))
       sscreen->use_aco = true;
    else if (sscreen->info.gfx_level >= GFX10)
-      sscreen->use_aco = (sscreen->debug_flags & DBG(USE_ACO));
+      sscreen->use_aco = (sscreen->shader_debug_flags & DBG(USE_ACO));
    else
       sscreen->use_aco = support_aco && sscreen->info.has_image_opcodes &&
-                         !(sscreen->debug_flags & DBG(USE_LLVM));
+                         !(sscreen->shader_debug_flags & DBG(USE_LLVM));
 #else
    sscreen->use_aco = true;
 #endif
@@ -1547,10 +1550,11 @@ static struct pipe_screen *radeonsi_screen_create_impl(struct radeon_winsys *ws,
    }
 
    (void)simple_mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
-   sscreen->use_monolithic_shaders = (sscreen->debug_flags & DBG(MONOLITHIC_SHADERS)) != 0;
+   sscreen->use_monolithic_shaders =
+      (sscreen->shader_debug_flags & DBG(MONOLITHIC_SHADERS)) != 0;
 
    if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
-      sscreen->debug_flags |= DBG_ALL_SHADERS;
+      sscreen->shader_debug_flags |= DBG_ALL_SHADERS;
 
    /* Syntax:
     *     EQAA=s,z,c

src/gallium/drivers/radeonsi/si_pipe.h

@@ -167,35 +167,6 @@ enum si_occlusion_query_mode {
 /* Debug flags. */
 enum
 {
-   /* Shader logging options: */
-   DBG_VS = MESA_SHADER_VERTEX,
-   DBG_TCS = MESA_SHADER_TESS_CTRL,
-   DBG_TES = MESA_SHADER_TESS_EVAL,
-   DBG_GS = MESA_SHADER_GEOMETRY,
-   DBG_PS = MESA_SHADER_FRAGMENT,
-   DBG_CS = MESA_SHADER_COMPUTE,
-   DBG_INIT_NIR,
-   DBG_NIR,
-   DBG_INIT_LLVM,
-   DBG_LLVM,
-   DBG_INIT_ACO,
-   DBG_ACO,
-   DBG_ASM,
-   DBG_STATS,
-
-   /* Shader compiler options the shader cache should be aware of: */
-   DBG_W32_GE,
-   DBG_W32_PS,
-   DBG_W32_CS,
-   DBG_W64_GE,
-   DBG_W64_PS,
-   DBG_W64_CS,
-
-   /* Shader compiler options (with no effect on the shader cache): */
-   DBG_CHECK_IR,
-   DBG_MONOLITHIC_SHADERS,
-   DBG_NO_OPT_VARIANT,
-
    /* Information logging options: */
    DBG_INFO,
    DBG_TEX,
@@ -250,6 +221,39 @@ enum
    DBG_COUNT
 };
 
+/* Debug options for shaders. */
+enum
+{
+   /* Shader logging options: */
+   DBG_VS = MESA_SHADER_VERTEX,
+   DBG_TCS = MESA_SHADER_TESS_CTRL,
+   DBG_TES = MESA_SHADER_TESS_EVAL,
+   DBG_GS = MESA_SHADER_GEOMETRY,
+   DBG_PS = MESA_SHADER_FRAGMENT,
+   DBG_CS = MESA_SHADER_COMPUTE,
+   DBG_INIT_NIR,
+   DBG_NIR,
+   DBG_INIT_LLVM,
+   DBG_LLVM,
+   DBG_INIT_ACO,
+   DBG_ACO,
+   DBG_ASM,
+   DBG_STATS,
+
+   /* Shader compiler options the shader cache should be aware of: */
+   DBG_W32_GE,
+   DBG_W32_PS,
+   DBG_W32_CS,
+   DBG_W64_GE,
+   DBG_W64_PS,
+   DBG_W64_CS,
+
+   /* Shader compiler options (with no effect on the shader cache): */
+   DBG_CHECK_IR,
+   DBG_MONOLITHIC_SHADERS,
+   DBG_NO_OPT_VARIANT,
+};
+
 enum
 {
    /* Tests: */
@@ -519,6 +523,7 @@ struct si_screen {
    struct radeon_info info;
    struct nir_shader_compiler_options *nir_options;
    uint64_t debug_flags;
+   uint64_t shader_debug_flags;
    char renderer_string[183];
 
    unsigned pa_sc_raster_config;

src/gallium/drivers/radeonsi/si_shader.c

@@ -762,8 +762,8 @@ bool si_can_dump_shader(struct si_screen *sscreen, gl_shader_stage stage,
    };
    assert(dump_type < ARRAY_SIZE(filter));
 
-   return sscreen->debug_flags & (1 << stage) &&
+   return sscreen->shader_debug_flags & (1 << stage) &&
-          sscreen->debug_flags & filter[dump_type];
+          sscreen->shader_debug_flags & filter[dump_type];
 }
 
 static void si_shader_dump_stats(struct si_screen *sscreen, struct si_shader *shader, FILE *file,

src/gallium/drivers/radeonsi/si_state_shaders.cpp

@@ -57,12 +57,12 @@ unsigned si_determine_wave_size(struct si_screen *sscreen, struct si_shader *sha
       return 32;
 
    /* AMD_DEBUG wave flags override everything else. */
-   if (sscreen->debug_flags &
+   if (sscreen->shader_debug_flags &
        (stage == MESA_SHADER_COMPUTE ? DBG(W32_CS) :
         stage == MESA_SHADER_FRAGMENT ? DBG(W32_PS) : DBG(W32_GE)))
       return 32;
 
-   if (sscreen->debug_flags &
+   if (sscreen->shader_debug_flags &
        (stage == MESA_SHADER_COMPUTE ? DBG(W64_CS) :
         stage == MESA_SHADER_FRAGMENT ? DBG(W64_PS) : DBG(W64_GE)))
       return 64;
@@ -2994,7 +2994,7 @@ static int si_shader_select_with_key(struct si_context *sctx, struct si_shader_c
     */
    SHADER_KEY_TYPE local_key;
 
-   if (unlikely(sscreen->debug_flags & DBG(NO_OPT_VARIANT))) {
+   if (unlikely(sscreen->shader_debug_flags & DBG(NO_OPT_VARIANT))) {
       /* Disable shader variant optimizations. */
       key = use_local_key_copy<SHADER_KEY_TYPE>(key, &local_key, key_size);
       memset(&local_key.opt, 0, key_opt_size);