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radeonsi: reduce syncing for initializing new buffers

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Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
This commit is contained in:
Marek Olšák 2021-03-19 23:34:03 -04:00 • committed by Marge Bot
parent 207bafd4dd
commit 5c827bde29
4 changed files with 12 additions and 12 deletions
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2
src/gallium/drivers/radeonsi/si_buffer.c
View file

@ -213,7 +213,7 @@ bool si_alloc_resource(struct si_screen *sscreen, struct si_resource *res)
}
if (res->b.b.flags & SI_RESOURCE_FLAG_CLEAR)
si_screen_clear_buffer(sscreen, &res->b.b, 0, res->bo_size, 0, SI_OP_SYNC_BEFORE_AFTER);
si_screen_clear_buffer(sscreen, &res->b.b, 0, res->bo_size, 0, SI_OP_SYNC_AFTER);
return true;
}

2
src/gallium/drivers/radeonsi/si_cp_reg_shadowing.c
View file

@ -172,7 +172,7 @@ void si_init_cp_reg_shadowing(struct si_context *sctx)
if (sctx->shadowed_regs) {
/* We need to clear the shadowed reg buffer. */
si_cp_dma_clear_buffer(sctx, &sctx->gfx_cs, &sctx->shadowed_regs->b.b,
0, sctx->shadowed_regs->bo_size, 0, SI_OP_SYNC_BEFORE_AFTER,
0, sctx->shadowed_regs->bo_size, 0, SI_OP_SYNC_AFTER,
SI_COHERENCY_CP, L2_BYPASS);
/* Create the shadowing preamble. */

2
src/gallium/drivers/radeonsi/si_pipe.c
View file

@ -734,7 +734,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, unsign
*/
uint32_t clear_value = 0;
si_clear_buffer(sctx, sctx->null_const_buf.buffer, 0, sctx->null_const_buf.buffer->width0,
&clear_value, 4, SI_OP_SYNC_BEFORE_AFTER, SI_COHERENCY_SHADER,
&clear_value, 4, SI_OP_SYNC_AFTER, SI_COHERENCY_SHADER,
SI_CP_DMA_CLEAR_METHOD);
}

18
src/gallium/drivers/radeonsi/si_texture.c
View file

@ -1012,7 +1012,7 @@ static struct si_texture *si_texture_create_object(struct pipe_screen *screen,
if (tex->cmask_buffer) {
/* Initialize the cmask to 0xCC (= compressed state). */
si_screen_clear_buffer(sscreen, &tex->cmask_buffer->b.b, tex->surface.cmask_offset,
tex->surface.cmask_size, 0xCCCCCCCC, SI_OP_SYNC_BEFORE_AFTER);
tex->surface.cmask_size, 0xCCCCCCCC, SI_OP_SYNC_AFTER);
}
if (tex->surface.htile_offset) {
uint32_t clear_value = 0;
@ -1021,7 +1021,7 @@ static struct si_texture *si_texture_create_object(struct pipe_screen *screen,
clear_value = 0x0000030F;
si_screen_clear_buffer(sscreen, &tex->buffer.b.b, tex->surface.htile_offset,
tex->surface.htile_size, clear_value, SI_OP_SYNC_BEFORE_AFTER);
tex->surface.htile_size, clear_value, SI_OP_SYNC_AFTER);
}
/* Initialize DCC only if the texture is not being imported. */
@ -1035,17 +1035,17 @@ static struct si_texture *si_texture_create_object(struct pipe_screen *screen,
tex->buffer.b.b.nr_samples <= 2) {
/* Simple case - all tiles have DCC enabled. */
si_screen_clear_buffer(sscreen, &tex->buffer.b.b, tex->surface.dcc_offset,
tex->surface.dcc_size, DCC_CLEAR_COLOR_0000, SI_OP_SYNC_BEFORE_AFTER);
tex->surface.dcc_size, DCC_CLEAR_COLOR_0000, SI_OP_SYNC_AFTER);
} else if (sscreen->info.chip_class >= GFX9) {
/* Clear to uncompressed. Clearing this to black is complicated. */
si_screen_clear_buffer(sscreen, &tex->buffer.b.b, tex->surface.dcc_offset,
tex->surface.dcc_size, DCC_UNCOMPRESSED, SI_OP_SYNC_BEFORE_AFTER);
tex->surface.dcc_size, DCC_UNCOMPRESSED, SI_OP_SYNC_AFTER);
} else {
/* GFX8: Initialize mipmap levels and multisamples separately. */
if (tex->buffer.b.b.nr_samples >= 2) {
/* Clearing this to black is complicated. */
si_screen_clear_buffer(sscreen, &tex->buffer.b.b, tex->surface.dcc_offset,
tex->surface.dcc_size, DCC_UNCOMPRESSED, SI_OP_SYNC_BEFORE_AFTER);
tex->surface.dcc_size, DCC_UNCOMPRESSED, SI_OP_SYNC_AFTER);
} else {
/* Clear the enabled mipmap levels to black. */
unsigned size = 0;
@ -1061,12 +1061,12 @@ static struct si_texture *si_texture_create_object(struct pipe_screen *screen,
/* Mipmap levels with DCC. */
if (size) {
si_screen_clear_buffer(sscreen, &tex->buffer.b.b, tex->surface.dcc_offset, size,
DCC_CLEAR_COLOR_0000, SI_OP_SYNC_BEFORE_AFTER);
DCC_CLEAR_COLOR_0000, SI_OP_SYNC_AFTER);
}
/* Mipmap levels without DCC. */
if (size != tex->surface.dcc_size) {
si_screen_clear_buffer(sscreen, &tex->buffer.b.b, tex->surface.dcc_offset + size,
tex->surface.dcc_size - size, DCC_UNCOMPRESSED, SI_OP_SYNC_BEFORE_AFTER);
tex->surface.dcc_size - size, DCC_UNCOMPRESSED, SI_OP_SYNC_AFTER);
}
}
}
@ -1078,7 +1078,7 @@ static struct si_texture *si_texture_create_object(struct pipe_screen *screen,
/* Uninitialized DCC can hang the display hw.
* Clear to white to indicate that. */
si_screen_clear_buffer(sscreen, &tex->buffer.b.b, tex->surface.display_dcc_offset,
tex->surface.u.gfx9.display_dcc_size, DCC_CLEAR_COLOR_1111, SI_OP_SYNC_BEFORE_AFTER);
tex->surface.u.gfx9.display_dcc_size, DCC_CLEAR_COLOR_1111, SI_OP_SYNC_AFTER);
}
/* Upload the DCC retile map.
@ -1105,7 +1105,7 @@ static struct si_texture *si_texture_create_object(struct pipe_screen *screen,
simple_mtx_lock(&sscreen->aux_context_lock);
si_copy_buffer(sctx, &tex->dcc_retile_buffer->b.b, &buf->b.b, 0,
0, buf->b.b.width0, SI_OP_SYNC_BEFORE_AFTER);
0, buf->b.b.width0, SI_OP_SYNC_AFTER);
sscreen->aux_context->flush(sscreen->aux_context, NULL, 0);
simple_mtx_unlock(&sscreen->aux_context_lock);