diff --git a/src/intel/vulkan/anv_internal_kernels.c b/src/intel/vulkan/anv_internal_kernels.c index aba6565996f..0e6a466359e 100644 --- a/src/intel/vulkan/anv_internal_kernels.c +++ b/src/intel/vulkan/anv_internal_kernels.c @@ -51,8 +51,8 @@ lower_base_workgroup_id(nir_builder *b, nir_intrinsic_instr *intrin, static void check_sends(struct genisa_stats *stats, unsigned send_count) { - assert(stats->spills == 0); - assert(stats->fills == 0); + assert(send_count == 0 || stats->spills == 0); + assert(send_count == 0 || stats->fills == 0); assert(send_count == 0 || stats->sends == send_count); } @@ -213,7 +213,8 @@ compile_shader(struct anv_device *device, } } - assert(prog_data.base.total_scratch == 0); + /* Complex shaders are allowed to spill */ + assert(sends_count_expectation == 0 || prog_data.base.total_scratch == 0); assert(program != NULL); struct anv_shader_internal *kernel = NULL; if (program == NULL) diff --git a/src/intel/vulkan/genX_simple_shader.c b/src/intel/vulkan/genX_simple_shader.c index 1e016ea2001..17172e44532 100644 --- a/src/intel/vulkan/genX_simple_shader.c +++ b/src/intel/vulkan/genX_simple_shader.c @@ -397,11 +397,14 @@ genX(emit_simpler_shader_init_compute)(struct anv_simple_shader *state) struct anv_shader_internal *cs_bin = state->kernel; const struct brw_cs_prog_data *prog_data = (const struct brw_cs_prog_data *) cs_bin->prog_data; - /* Currently our simple shaders are simple enough that they never spill. */ - assert(prog_data->base.total_scratch == 0); if (state->cmd_buffer != NULL) { - genX(cmd_buffer_ensure_cfe_state)(state->cmd_buffer, 0); + genX(cmd_buffer_ensure_cfe_state)(state->cmd_buffer, + prog_data->base.total_scratch); } else { + /* Currently our simple shaders not in the command buffers are simple + * enough that they never spill. + */ + assert(prog_data->base.total_scratch == 0); anv_batch_emit(state->batch, GENX(CFE_STATE), cfe) { cfe.MaximumNumberofThreads = state->device->info->max_cs_threads *