fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-25 02:10:11 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

nvir: introduce OP_SGXT

Browse source 
Required for SM70 EXTBF lowering.

v2:
- added constant folding

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5377>
This commit is contained in:
Ben Skeggs 2020-06-07 09:51:56 +10:00 • committed by Marge Bot
parent 6fd41da1ef
commit 5c3040e93a
4 changed files with 15 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
src/gallium/drivers/nouveau/codegen/nv50_ir.h
View file

@ -156,6 +156,7 @@ enum operation
OP_BREV, // bitfield reverse
OP_BMSK, // bitfield mask
OP_PERMT, // dst = bytes from src2,src0 selected by src1 (nvc0's src order)
OP_SGXT,
OP_ATOM,
OP_BAR, // execution barrier, sources = { id, thread count, predicate }
OP_VADD, // byte/word vector operations

10
src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
View file

@ -558,6 +558,16 @@ ConstantFolding::expr(Instruction *i,
memset(&res.data, 0, sizeof(res.data));
switch (i->op) {
case OP_SGXT: {
int bits = b->data.u32;
if (bits) {
uint32_t data = a->data.u32 & (0xffffffff >> (32 - bits));
if (bits < 32 && (data & (1 << (bits - 1))))
data = data - (1 << bits);
res.data.u32 = data;
}
break;
}
case OP_BMSK:
res.data.u32 = ((1 << b->data.u32) - 1) << a->data.u32;
break;

1
src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
View file

@ -182,6 +182,7 @@ const char *operationStr[OP_LAST + 1] =
"brev",
"bmsk",
"permt",
"sgxt",
"atom",
"bar",
"vadd",

5
src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp
View file

@ -52,6 +52,7 @@ const uint8_t Target::operationSrcNr[] =
1, 1, // DFDX, DFDY
1, 2, 1, 2, 0, 0, // RDSV, WRSV, PIXLD, QUADOP, QUADON, QUADPOP
2, 3, 2, 1, 1, 2, 3, // POPCNT, INSBF, EXTBF, BFIND, BREV, BMSK, PERMT
2, // SGXT
2, 2, // ATOM, BAR
2, 2, 2, 2, 3, 2, // VADD, VAVG, VMIN, VMAX, VSAD, VSET,
2, 2, 2, 1, // VSHR, VSHL, VSEL, CCTL
@ -120,9 +121,9 @@ const OpClass Target::operationClass[] =
// DFDX, DFDY, RDSV, WRSV; PIXLD, QUADOP, QUADON, QUADPOP
OPCLASS_OTHER, OPCLASS_OTHER, OPCLASS_OTHER, OPCLASS_OTHER,
OPCLASS_OTHER, OPCLASS_OTHER, OPCLASS_CONTROL, OPCLASS_CONTROL,
// POPCNT, INSBF, EXTBF, BFIND, BREV, BMSK; PERMT
// POPCNT, INSBF, EXTBF, BFIND, BREV, BMSK; PERMT, SGXT
OPCLASS_BITFIELD, OPCLASS_BITFIELD, OPCLASS_BITFIELD, OPCLASS_BITFIELD,
OPCLASS_BITFIELD, OPCLASS_BITFIELD, OPCLASS_BITFIELD, OPCLASS_BITFIELD,
OPCLASS_BITFIELD, OPCLASS_BITFIELD, OPCLASS_BITFIELD,
// ATOM, BAR
OPCLASS_ATOMIC, OPCLASS_CONTROL,
// VADD, VAVG, VMIN, VMAX