diff --git a/src/gallium/drivers/radeonsi/si_get.c b/src/gallium/drivers/radeonsi/si_get.c
index 6fe0e9302b5..6ad3ccd6b63 100644
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -495,7 +495,7 @@ static int si_get_shader_param(struct pipe_screen *pscreen, enum pipe_shader_typ
    case PIPE_SHADER_CAP_FP16_DERIVATIVES:
    case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
    case PIPE_SHADER_CAP_INT16:
-      return sscreen->info.gfx_level >= GFX8 && sscreen->options.fp16;
+      return sscreen->nir_options->lower_mediump_io != NULL;
 
    /* Unsupported boolean features. */
    case PIPE_SHADER_CAP_SUBROUTINES:
@@ -1423,6 +1423,8 @@ void si_init_screen_get_functions(struct si_screen *sscreen)
    options->force_f2f16_rtz = true;
    options->io_options = nir_io_has_flexible_input_interpolation_except_flat |
                          nir_io_glsl_lower_derefs;
+   options->lower_mediump_io = sscreen->info.gfx_level >= GFX8 && sscreen->options.fp16 ?
+                                  si_lower_mediump_io : NULL;
    /* HW supports indirect indexing for: | Enabled in driver
     * -------------------------------------------------------
     * TCS inputs                         | Yes
diff --git a/src/gallium/drivers/radeonsi/si_shader.h b/src/gallium/drivers/radeonsi/si_shader.h
index 97b753e5f1b..6fb351fa30d 100644
--- a/src/gallium/drivers/radeonsi/si_shader.h
+++ b/src/gallium/drivers/radeonsi/si_shader.h
@@ -1027,6 +1027,7 @@ void si_nir_scan_shader(struct si_screen *sscreen,  const struct nir_shader *nir
 
 /* si_shader_nir.c */
 extern const struct nir_lower_subgroups_options si_nir_subgroups_options;
+void si_lower_mediump_io(struct nir_shader *nir);
 
 bool si_alu_to_scalar_packed_math_filter(const struct nir_instr *instr, const void *data);
 void si_nir_opts(struct si_screen *sscreen, struct nir_shader *nir, bool first);
diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c b/src/gallium/drivers/radeonsi/si_shader_nir.c
index 4134310457a..e525a36c583 100644
--- a/src/gallium/drivers/radeonsi/si_shader_nir.c
+++ b/src/gallium/drivers/radeonsi/si_shader_nir.c
@@ -270,6 +270,17 @@ const nir_lower_subgroups_options si_nir_subgroups_options = {
    .lower_boolean_shuffle = true,
 };
 
+void si_lower_mediump_io(nir_shader *nir)
+{
+   NIR_PASS_V(nir, nir_lower_mediump_io,
+              /* TODO: LLVM fails to compile this test if VS inputs are 16-bit:
+               * dEQP-GLES31.functional.shaders.builtin_functions.integer.bitfieldinsert.uvec3_lowp_geometry
+               */
+              (nir->info.stage != MESA_SHADER_VERTEX ? nir_var_shader_in : 0) | nir_var_shader_out,
+              BITFIELD64_BIT(VARYING_SLOT_PNTC) | BITFIELD64_RANGE(VARYING_SLOT_VAR0, 32),
+              true);
+}
+
 /**
  * Perform "lowering" operations on the NIR that are run once when the shader
  * selector is created.
@@ -352,16 +363,6 @@ static void si_lower_nir(struct si_screen *sscreen, struct nir_shader *nir)
       }
    }
 
-   if (sscreen->b.get_shader_param(&sscreen->b, PIPE_SHADER_FRAGMENT, PIPE_SHADER_CAP_FP16)) {
-      NIR_PASS_V(nir, nir_lower_mediump_io,
-                 /* TODO: LLVM fails to compile this test if VS inputs are 16-bit:
-                  * dEQP-GLES31.functional.shaders.builtin_functions.integer.bitfieldinsert.uvec3_lowp_geometry
-                  */
-                 (nir->info.stage != MESA_SHADER_VERTEX ? nir_var_shader_in : 0) | nir_var_shader_out,
-                 BITFIELD64_BIT(VARYING_SLOT_PNTC) | BITFIELD64_RANGE(VARYING_SLOT_VAR0, 32),
-                 true);
-   }
-
    si_nir_opts(sscreen, nir, true);
    /* Run late optimizations to fuse ffma and eliminate 16-bit conversions. */
    si_nir_late_opts(nir);