i965: Nuke brw_wm_glsl.c.

It was only used for gen6 fragment programs (not GLSL shaders) at this
point, and it was clearly unsuited to the task -- missing opcodes,
corrupted texturing, and assertion failures hit various applications
of all sorts.  It was easier to patch up the non-glsl for remaining
gen6 changes than to make brw_wm_glsl.c complete.

Bug #30530

src/mesa/drivers/dri/i965/Makefile

@@ -81,7 +81,6 @@ DRIVER_SOURCES = \
 	brw_wm_emit.c \
 	brw_wm_fp.c \
 	brw_wm_iz.c \
-	brw_wm_glsl.c \
 	brw_wm_pass0.c \
 	brw_wm_pass1.c \
 	brw_wm_pass2.c \

src/mesa/drivers/dri/i965/brw_context.h

@@ -171,7 +171,6 @@ struct brw_vertex_program {
 struct brw_fragment_program {
    struct gl_fragment_program program;
    GLuint id;  /**< serial no. to identify frag progs, never re-used */
-   GLboolean isGLSL;  /**< really, any IF/LOOP/CONT/BREAK instructions */
 
    /** for debugging, which texture units are referenced */
    GLbitfield tex_units_used;
@@ -211,6 +210,7 @@ struct brw_wm_prog_data {
    GLuint nr_params;       /**< number of float params/constants */
    GLuint nr_pull_params;
    GLboolean error;
+   int dispatch_width;
 
    /* Pointer to tracked values (only valid once
     * _mesa_load_state_parameters has been called at runtime).

src/mesa/drivers/dri/i965/brw_program.c

@@ -142,7 +142,6 @@ static GLboolean brwProgramStringNotify( struct gl_context *ctx,
       if (newFP == curFP)
 	 brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM;
       newFP->id = brw->program_id++;      
-      newFP->isGLSL = brw_wm_is_glsl(fprog);
 
       /* Don't reject fragment shaders for their Mesa IR state when we're
        * using the new FS backend.

src/mesa/drivers/dri/i965/brw_wm.c

@@ -134,7 +134,7 @@ brw_wm_payload_setup(struct brw_context *brw,
       /* R3-4: perspective pixel location barycentric */
       c->nr_payload_regs += 2;
       /* R5-6: perspective pixel location bary for dispatch width != 8 */
-      if (!c->fp->isGLSL) { /* dispatch_width != 8 */
+      if (c->dispatch_width == 16) {
 	 c->nr_payload_regs += 2;
       }
       /* R7-10: perspective centroid barycentric */
@@ -147,7 +147,7 @@ brw_wm_payload_setup(struct brw_context *brw,
       if (uses_depth) {
 	 c->source_depth_reg = c->nr_payload_regs;
 	 c->nr_payload_regs++;
-	 if (!c->fp->isGLSL) { /* dispatch_width != 8 */
+	 if (c->dispatch_width == 16) {
 	    /* R28: interpolated depth if not 8-wide. */
 	    c->nr_payload_regs++;
 	 }
@@ -157,7 +157,7 @@ brw_wm_payload_setup(struct brw_context *brw,
       if (uses_depth) {
 	 c->source_w_reg = c->nr_payload_regs;
 	 c->nr_payload_regs++;
-	 if (!c->fp->isGLSL) { /* dispatch_width != 8 */
+	 if (c->dispatch_width == 16) {
 	    /* R30: interpolated W if not 8-wide. */
 	    c->nr_payload_regs++;
 	 }
@@ -225,23 +225,16 @@ static void do_wm_prog( struct brw_context *brw,
 
    brw_wm_payload_setup(brw, c);
 
-   /* temporary sanity check assertion */
-   ASSERT(fp->isGLSL == brw_wm_is_glsl(&c->fp->program));
-
    if (!brw_wm_fs_emit(brw, c)) {
       /*
        * Shader which use GLSL features such as flow control are handled
        * differently from "simple" shaders.
        */
-      if (fp->isGLSL) {
-	 c->dispatch_width = 8;
-	 brw_wm_glsl_emit(brw, c);
-      }
-      else {
-	 c->dispatch_width = 16;
-	 brw_wm_non_glsl_emit(brw, c);
-      }
+      c->dispatch_width = 16;
+      brw_wm_payload_setup(brw, c);
+      brw_wm_non_glsl_emit(brw, c);
    }
+   c->prog_data.dispatch_width = c->dispatch_width;
 
    /* Scratch space is used for register spilling */
    if (c->last_scratch) {

src/mesa/drivers/dri/i965/brw_wm.h

@@ -313,8 +313,6 @@ void brw_wm_print_program( struct brw_wm_compile *c,
 void brw_wm_lookup_iz(struct intel_context *intel,
 		      struct brw_wm_compile *c);
 
-GLboolean brw_wm_is_glsl(const struct gl_fragment_program *fp);
-void brw_wm_glsl_emit(struct brw_context *brw, struct brw_wm_compile *c);
 GLboolean brw_wm_fs_emit(struct brw_context *brw, struct brw_wm_compile *c);
 
 /* brw_wm_emit.c */

src/mesa/drivers/dri/i965/brw_wm_state.c

@@ -132,7 +132,6 @@ wm_unit_populate_key(struct brw_context *brw, struct brw_wm_unit_key *key)
 
    /* _NEW_COLOR */
    key->uses_kill = fp->UsesKill || ctx->Color.AlphaEnabled;
-   key->is_glsl = bfp->isGLSL;
 
    /* If using the fragment shader backend, the program is always
     * 8-wide.

src/mesa/drivers/dri/i965/gen6_wm_state.c

@@ -128,8 +128,8 @@ upload_wm_state(struct brw_context *brw)
 
    dw5 |= (40 - 1) << GEN6_WM_MAX_THREADS_SHIFT;
 
-   /* BRW_NEW_FRAGMENT_PROGRAM */
-   if (fp->isGLSL)
+   /* CACHE_NEW_WM_PROG */
+   if (brw->wm.prog_data->dispatch_width == 8)
       dw5 |= GEN6_WM_8_DISPATCH_ENABLE;
    else
       dw5 |= GEN6_WM_16_DISPATCH_ENABLE;