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anv: remove local computation of dynamic states

Browse source 
This bit mask is already computed in
anv_graphics_pipeline::dynamic_states in anv_graphics_pipeline_init().

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17601>
This commit is contained in:
Lionel Landwerlin 2022-01-21 14:35:04 +02:00 • committed by Marge Bot
parent 4c56b535f5
commit 5b561b501a
2 changed files with 32 additions and 46 deletions
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4
src/intel/vulkan/anv_pipeline.c
View file

@ -1345,8 +1345,6 @@ anv_pipeline_compile_graphics(struct anv_graphics_pipeline *pipeline,
const struct brw_compiler *compiler = pipeline->base.device->physical->compiler;
struct anv_pipeline_stage stages[ANV_GRAPHICS_SHADER_STAGE_COUNT] = {};
uint32_t dynamic_states = pipeline->dynamic_states;
VkResult result;
for (uint32_t i = 0; i < info->stageCount; i++) {
const VkPipelineShaderStageCreateInfo *sinfo = &info->pStages[i];
@ -1384,7 +1382,7 @@ anv_pipeline_compile_graphics(struct anv_graphics_pipeline *pipeline,
case MESA_SHADER_FRAGMENT: {
const bool raster_enabled =
!info->pRasterizationState->rasterizerDiscardEnable ||
dynamic_states & ANV_CMD_DIRTY_DYNAMIC_RASTERIZER_DISCARD_ENABLE;
pipeline->dynamic_states & ANV_CMD_DIRTY_DYNAMIC_RASTERIZER_DISCARD_ENABLE;
populate_wm_prog_key(pipeline,
pipeline->base.device->robust_buffer_access,
raster_enabled ? info->pMultisampleState : NULL,

74
src/intel/vulkan/genX_pipeline.c
View file

@ -763,7 +763,6 @@ emit_rs_state(struct anv_graphics_pipeline *pipeline,
const VkPipelineMultisampleStateCreateInfo *ms_info,
const VkPipelineRasterizationLineStateCreateInfoEXT *line_info,
const VkPipelineRenderingCreateInfo *rendering_info,
const anv_cmd_dirty_mask_t dynamic_states,
enum intel_urb_deref_block_size urb_deref_block_size)
{
struct GENX(3DSTATE_SF) sf = {
@ -829,7 +828,7 @@ emit_rs_state(struct anv_graphics_pipeline *pipeline,
VkPolygonMode raster_mode =
genX(raster_polygon_mode)(pipeline, ia_info ? ia_info->topology : VK_PRIMITIVE_TOPOLOGY_MAX_ENUM);
bool dynamic_primitive_topology =
dynamic_states & ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY;
pipeline->dynamic_states & ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY;
/* For details on 3DSTATE_RASTER multisample state, see the BSpec table
* "Multisample Modes State".
@ -861,10 +860,10 @@ emit_rs_state(struct anv_graphics_pipeline *pipeline,
anv_rasterization_aa_mode(raster_mode, pipeline->line_mode);
raster.FrontWinding =
dynamic_states & ANV_CMD_DIRTY_DYNAMIC_FRONT_FACE ?
pipeline->dynamic_states & ANV_CMD_DIRTY_DYNAMIC_FRONT_FACE ?
0 : genX(vk_to_intel_front_face)[rs_info->frontFace];
raster.CullMode =
dynamic_states & ANV_CMD_DIRTY_DYNAMIC_CULL_MODE ?
pipeline->dynamic_states & ANV_CMD_DIRTY_DYNAMIC_CULL_MODE ?
0 : genX(vk_to_intel_cullmode)[rs_info->cullMode];
raster.FrontFaceFillMode = genX(vk_to_intel_fillmode)[rs_info->polygonMode];
@ -886,7 +885,7 @@ emit_rs_state(struct anv_graphics_pipeline *pipeline,
#endif
bool depth_bias_enable =
dynamic_states & ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS_ENABLE ?
pipeline->dynamic_states & ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS_ENABLE ?
0 : rs_info->depthBiasEnable;
raster.GlobalDepthOffsetEnableSolid = depth_bias_enable;
@ -921,8 +920,7 @@ emit_rs_state(struct anv_graphics_pipeline *pipeline,
static void
emit_ms_state(struct anv_graphics_pipeline *pipeline,
const VkPipelineMultisampleStateCreateInfo *info,
const anv_cmd_dirty_mask_t dynamic_states)
const VkPipelineMultisampleStateCreateInfo *info)
{
#if GFX_VER >= 8
/* On Gfx8+ 3DSTATE_MULTISAMPLE only holds the number of samples. */
@ -1169,8 +1167,7 @@ sanitize_ds_state(VkPipelineDepthStencilStateCreateInfo *state,
static void
emit_ds_state(struct anv_graphics_pipeline *pipeline,
const VkPipelineDepthStencilStateCreateInfo *pCreateInfo,
const VkPipelineRenderingCreateInfo *rendering_info,
const anv_cmd_dirty_mask_t dynamic_states)
const VkPipelineRenderingCreateInfo *rendering_info)
{
#if GFX_VER == 7
# define depth_stencil_dw pipeline->gfx7.depth_stencil_state
@ -1209,7 +1206,7 @@ emit_ds_state(struct anv_graphics_pipeline *pipeline,
pipeline->depth_bounds_test_enable = info.depthBoundsTestEnable;
bool dynamic_stencil_op =
dynamic_states & ANV_CMD_DIRTY_DYNAMIC_STENCIL_OP;
pipeline->dynamic_states & ANV_CMD_DIRTY_DYNAMIC_STENCIL_OP;
#if GFX_VER <= 7
struct GENX(DEPTH_STENCIL_STATE) depth_stencil = {
@ -1217,21 +1214,21 @@ emit_ds_state(struct anv_graphics_pipeline *pipeline,
struct GENX(3DSTATE_WM_DEPTH_STENCIL) depth_stencil = {
#endif
.DepthTestEnable =
dynamic_states & ANV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE ?
pipeline->dynamic_states & ANV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE ?
0 : info.depthTestEnable,
.DepthBufferWriteEnable =
dynamic_states & ANV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE ?
pipeline->dynamic_states & ANV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE ?
0 : info.depthWriteEnable,
.DepthTestFunction =
dynamic_states & ANV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP ?
pipeline->dynamic_states & ANV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP ?
0 : genX(vk_to_intel_compare_op)[info.depthCompareOp],
.DoubleSidedStencilEnable = true,
.StencilTestEnable =
dynamic_states & ANV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE ?
pipeline->dynamic_states & ANV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE ?
0 : info.stencilTestEnable,
.StencilFailOp = genX(vk_to_intel_stencil_op)[info.front.failOp],
@ -1287,8 +1284,7 @@ write_disabled_blend(uint32_t *state)
static void
emit_cb_state(struct anv_graphics_pipeline *pipeline,
const VkPipelineColorBlendStateCreateInfo *info,
const VkPipelineMultisampleStateCreateInfo *ms_info,
const anv_cmd_dirty_mask_t dynamic_states)
const VkPipelineMultisampleStateCreateInfo *ms_info)
{
struct anv_device *device = pipeline->base.device;
const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
@ -1447,8 +1443,7 @@ static void
emit_3dstate_clip(struct anv_graphics_pipeline *pipeline,
const VkPipelineInputAssemblyStateCreateInfo *ia_info,
const VkPipelineViewportStateCreateInfo *vp_info,
const VkPipelineRasterizationStateCreateInfo *rs_info,
const anv_cmd_dirty_mask_t dynamic_states)
const VkPipelineRasterizationStateCreateInfo *rs_info)
{
const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
(void) wm_prog_data;
@ -1470,8 +1465,8 @@ emit_3dstate_clip(struct anv_graphics_pipeline *pipeline,
VkPolygonMode raster_mode =
genX(raster_polygon_mode)(pipeline, ia_info ? ia_info->topology : VK_PRIMITIVE_TOPOLOGY_MAX_ENUM);
clip.ViewportXYClipTestEnable =
dynamic_states & ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY ?
0 : (raster_mode == VK_POLYGON_MODE_FILL);
pipeline->dynamic_states & ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY ?
0 : (raster_mode == VK_POLYGON_MODE_FILL);
#if GFX_VER >= 8
clip.VertexSubPixelPrecisionSelect = _8Bit;
@ -1562,8 +1557,7 @@ emit_3dstate_clip(struct anv_graphics_pipeline *pipeline,
static void
emit_3dstate_streamout(struct anv_graphics_pipeline *pipeline,
const VkPipelineRasterizationStateCreateInfo *rs_info,
const anv_cmd_dirty_mask_t dynamic_states)
const VkPipelineRasterizationStateCreateInfo *rs_info)
{
const struct brw_vue_prog_data *prog_data =
anv_pipeline_get_last_vue_prog_data(pipeline);
@ -1698,8 +1692,8 @@ emit_3dstate_streamout(struct anv_graphics_pipeline *pipeline,
struct GENX(3DSTATE_STREAMOUT) so = {
GENX(3DSTATE_STREAMOUT_header),
.RenderingDisable =
(dynamic_states & ANV_CMD_DIRTY_DYNAMIC_RASTERIZER_DISCARD_ENABLE) ?
0 : rs_info->rasterizerDiscardEnable,
(pipeline->dynamic_states & ANV_CMD_DIRTY_DYNAMIC_RASTERIZER_DISCARD_ENABLE) ?
0 : rs_info->rasterizerDiscardEnable,
};
if (xfb_info) {
@ -2168,8 +2162,7 @@ emit_3dstate_wm(struct anv_graphics_pipeline *pipeline,
const VkPipelineColorBlendStateCreateInfo *blend,
const VkPipelineMultisampleStateCreateInfo *multisample,
const VkPipelineRasterizationLineStateCreateInfoEXT *line,
const VkRenderingSelfDependencyInfoMESA *rsd,
const anv_cmd_dirty_mask_t dynamic_states)
const VkRenderingSelfDependencyInfoMESA *rsd)
{
const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
@ -2212,7 +2205,7 @@ emit_3dstate_wm(struct anv_graphics_pipeline *pipeline,
wm_prog_data->uses_kill;
/* Only set this value in non dynamic mode. */
if (!(dynamic_states & ANV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_STATE)) {
if (!(pipeline->dynamic_states & ANV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_STATE)) {
wm.ForceThreadDispatchEnable =
(pipeline->force_fragment_thread_dispatch ||
!has_color_buffer_write_enabled(pipeline, blend)) ? ForceON : 0;
@ -2245,7 +2238,7 @@ emit_3dstate_wm(struct anv_graphics_pipeline *pipeline,
wm.PixelShaderKillsPixel;
/* Only set this value in non dynamic mode. */
if (!(dynamic_states & ANV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_STATE)) {
if (!(pipeline->dynamic_states & ANV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_STATE)) {
wm.ThreadDispatchEnable =
pipeline->force_fragment_thread_dispatch ||
has_color_buffer_write_enabled(pipeline, blend);
@ -2265,8 +2258,8 @@ emit_3dstate_wm(struct anv_graphics_pipeline *pipeline,
genX(raster_polygon_mode)(pipeline, ia ? ia->topology : VK_PRIMITIVE_TOPOLOGY_MAX_ENUM);
wm.MultisampleRasterizationMode =
dynamic_states & ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY ? 0 :
genX(ms_rasterization_mode)(pipeline, raster_mode);
pipeline->dynamic_states & ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY ?
0 : genX(ms_rasterization_mode)(pipeline, raster_mode);
#endif
wm.LineStippleEnable = line && line->stippledLineEnable;
@ -2712,14 +2705,12 @@ genX(graphics_pipeline_create)(
return result;
}
anv_cmd_dirty_mask_t dynamic_states = pipeline->dynamic_states;
/* If rasterization is not enabled, various CreateInfo structs must be
* ignored.
*/
const bool raster_enabled =
!pCreateInfo->pRasterizationState->rasterizerDiscardEnable ||
(dynamic_states & ANV_CMD_DIRTY_DYNAMIC_RASTERIZER_DISCARD_ENABLE);
(pipeline->dynamic_states & ANV_CMD_DIRTY_DYNAMIC_RASTERIZER_DISCARD_ENABLE);
const VkPipelineViewportStateCreateInfo *vp_info =
raster_enabled ? pCreateInfo->pViewportState : NULL;
@ -2744,17 +2735,16 @@ genX(graphics_pipeline_create)(
emit_rs_state(pipeline, pCreateInfo->pInputAssemblyState,
pCreateInfo->pRasterizationState,
ms_info, line_info, rendering_info,
dynamic_states, urb_deref_block_size);
emit_ms_state(pipeline, ms_info, dynamic_states);
emit_ds_state(pipeline, ds_info, rendering_info, dynamic_states);
emit_cb_state(pipeline, cb_info, ms_info, dynamic_states);
urb_deref_block_size);
emit_ms_state(pipeline, ms_info);
emit_ds_state(pipeline, ds_info, rendering_info);
emit_cb_state(pipeline, cb_info, ms_info);
compute_kill_pixel(pipeline, ms_info, rsd_info);
emit_3dstate_clip(pipeline,
pCreateInfo->pInputAssemblyState,
vp_info,
pCreateInfo->pRasterizationState,
dynamic_states);
pCreateInfo->pRasterizationState);
#if GFX_VER == 12
emit_3dstate_primitive_replication(pipeline, rendering_info);
@ -2789,8 +2779,7 @@ genX(graphics_pipeline_create)(
emit_3dstate_vf_statistics(pipeline);
emit_3dstate_streamout(pipeline, pCreateInfo->pRasterizationState,
dynamic_states);
emit_3dstate_streamout(pipeline, pCreateInfo->pRasterizationState);
#if GFX_VERx10 >= 125
/* Disable Mesh. */
if (device->physical->vk.supported_extensions.NV_mesh_shader) {
@ -2816,8 +2805,7 @@ genX(graphics_pipeline_create)(
emit_3dstate_wm(pipeline,
pCreateInfo->pInputAssemblyState,
pCreateInfo->pRasterizationState,
cb_info, ms_info, line_info, rsd_info,
dynamic_states);
cb_info, ms_info, line_info, rsd_info);
emit_3dstate_ps(pipeline, cb_info, ms_info);
#if GFX_VER >= 8
emit_3dstate_ps_extra(pipeline, pCreateInfo->pRasterizationState, rsd_info);