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i965: Fix gl_TessLevelOuter[] for isolines.

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Thanks to James Legg for finding this!

From the ARB_tessellation_shader spec:
"The number of isolines generated is derived from the first outer
 tessellation level; the number of segments in each isoline is
 derived from the second outer tessellation level."

According to the PRM, "TF.LineDensity determines # lines" while
"TF.LineDetail determines # segments".  Line Density is stored at
DWord 6, while Line Detail is at DWord 7.  So, they're not reversed
like they are for triangles and quads.

Fixes Piglit's spec/arb_tessellation_shader/execution/isoline,
and about 24 dEQP isoline tests (with GL_EXT_tessellation_shader
hacked on - it's not normally enabled).

Cc: mesa-stable@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94524
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
This commit is contained in:
Kenneth Graunke 2016-03-14 14:22:39 -07:00
parent 24298b7e2f
commit 5b2d8c2273
2 changed files with 22 additions and 6 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

16
src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp
View file

@ -402,6 +402,7 @@ vec4_tcs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
} }
} else if (imm_offset == 1 && indirect_offset.file == BAD_FILE) { } else if (imm_offset == 1 && indirect_offset.file == BAD_FILE) {
dst.type = BRW_REGISTER_TYPE_F; dst.type = BRW_REGISTER_TYPE_F;
unsigned swiz = BRW_SWIZZLE_WZYX;
/* This is a read of gl_TessLevelOuter[], which lives in the /* This is a read of gl_TessLevelOuter[], which lives in the
* high 4 DWords of the Patch URB header, in reverse order. * high 4 DWords of the Patch URB header, in reverse order.
@ -414,6 +415,8 @@ vec4_tcs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
dst.writemask = WRITEMASK_XYZ; dst.writemask = WRITEMASK_XYZ;
break; break;
case GL_ISOLINES: case GL_ISOLINES:
/* Isolines are not reversed; swizzle .zw -> .xy */
swiz = BRW_SWIZZLE_ZWZW;
dst.writemask = WRITEMASK_XY; dst.writemask = WRITEMASK_XY;
return; return;
default: default:
@ -422,7 +425,7 @@ vec4_tcs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
dst_reg tmp(this, glsl_type::vec4_type); dst_reg tmp(this, glsl_type::vec4_type);
emit_output_urb_read(tmp, 1, src_reg()); emit_output_urb_read(tmp, 1, src_reg());
emit(MOV(dst, swizzle(src_reg(tmp), BRW_SWIZZLE_WZYX))); emit(MOV(dst, swizzle(src_reg(tmp), swiz)));
} else { } else {
emit_output_urb_read(dst, imm_offset, indirect_offset); emit_output_urb_read(dst, imm_offset, indirect_offset);
} }
@ -475,8 +478,15 @@ vec4_tcs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
* Patch URB Header at DWords 4-7. However, it's reversed, so * Patch URB Header at DWords 4-7. However, it's reversed, so
* instead of .xyzw we have .wzyx. * instead of .xyzw we have .wzyx.
*/ */
swiz = BRW_SWIZZLE_WZYX; if (key->tes_primitive_mode == GL_ISOLINES) {
mask = writemask_for_backwards_vector(mask); /* Isolines .xy should be stored in .zw, in order. */
swiz = BRW_SWIZZLE4(0, 0, 0, 1);
mask <<= 2;
} else {
/* Other domains are reversed; store .wzyx instead of .xyzw. */
swiz = BRW_SWIZZLE_WZYX;
mask = writemask_for_backwards_vector(mask);
}
} }
emit_urb_write(swizzle(value, swiz), mask, emit_urb_write(swizzle(value, swiz), mask,

12
src/mesa/drivers/dri/i965/brw_vec4_tes.cpp
View file

@ -149,9 +149,15 @@ vec4_tes_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
src_reg(brw_vec8_grf(1, 0)))); src_reg(brw_vec8_grf(1, 0))));
break; break;
case nir_intrinsic_load_tess_level_outer: case nir_intrinsic_load_tess_level_outer:
emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_F), if (tes_prog_data->domain == BRW_TESS_DOMAIN_ISOLINE) {
swizzle(src_reg(ATTR, 1, glsl_type::vec4_type), emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_F),
BRW_SWIZZLE_WZYX))); swizzle(src_reg(ATTR, 1, glsl_type::vec4_type),
BRW_SWIZZLE_ZWZW)));
} else {
emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_F),
swizzle(src_reg(ATTR, 1, glsl_type::vec4_type),
BRW_SWIZZLE_WZYX)));
}
break; break;
case nir_intrinsic_load_tess_level_inner: case nir_intrinsic_load_tess_level_inner:
if (tes_prog_data->domain == BRW_TESS_DOMAIN_QUAD) { if (tes_prog_data->domain == BRW_TESS_DOMAIN_QUAD) {