fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-02-10 18:20:27 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 9

r600: work out shader export mask at shader build time (v1.1)

Browse source 
Since enhanced layouts allows setting specific MRT outputs, we
can get sparse outputs, so we have to calculate the shader
mask earlier.

v1.1: update checks for state update (Roland)

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Dave Airlie 2018-02-05 13:46:23 +10:00
parent f292eceae1
commit 5b14e06d8b
6 changed files with 13 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
src/gallium/drivers/r600/evergreen_state.c
View file

@ -2026,7 +2026,7 @@ static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_
struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
unsigned ps_colormask = a->ps_color_export_mask;
unsigned rat_colormask = evergreen_construct_rat_mask(rctx, a, a->nr_cbufs);
radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
radeon_emit(cs, (a->blend_colormask & fb_colormask) | rat_colormask); /* R_028238_CB_TARGET_MASK */
@ -3373,6 +3373,7 @@ void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader
exports_ps = 2;
}
shader->nr_ps_color_outputs = num_cout;
shader->ps_color_export_mask = rshader->ps_color_export_mask;
if (ninterp == 0) {
ninterp = 1;
have_perspective = TRUE;

1
src/gallium/drivers/r600/r600_pipe.h
View file

@ -153,6 +153,7 @@ struct r600_cb_misc_state {
unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
unsigned nr_cbufs;
unsigned nr_ps_color_outputs;
unsigned ps_color_export_mask;
unsigned image_rat_enabled_mask;
unsigned buffer_rat_enabled_mask;
bool multiwrite;

3
src/gallium/drivers/r600/r600_shader.c
View file

@ -3875,6 +3875,7 @@ static int r600_shader_from_tgsi(struct r600_context *rctx,
output[j].array_base = shader->output[i].sid;
output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
shader->nr_ps_color_exports++;
shader->ps_color_export_mask |= (0xf << (shader->output[i].sid * 4));
if (shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN)) {
for (k = 1; k < max_color_exports; k++) {
j++;
@ -3890,6 +3891,7 @@ static int r600_shader_from_tgsi(struct r600_context *rctx,
output[j].op = CF_OP_EXPORT;
output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
shader->nr_ps_color_exports++;
shader->ps_color_export_mask |= (0xf << (j * 4));
}
}
} else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
@ -3978,6 +3980,7 @@ static int r600_shader_from_tgsi(struct r600_context *rctx,
output[j].op = CF_OP_EXPORT;
j++;
shader->nr_ps_color_exports++;
shader->ps_color_export_mask = 0xf;
}
noutput = j;

3
src/gallium/drivers/r600/r600_shader.h
View file

@ -84,6 +84,7 @@ struct r600_shader {
unsigned nr_ps_max_color_exports;
/* Real number of ps color exports compiled in the bytecode */
unsigned nr_ps_color_exports;
unsigned ps_color_export_mask;
/* bit n is set if the shader writes gl_ClipDistance[n] */
unsigned cc_dist_mask;
unsigned clip_dist_write;
@ -172,6 +173,8 @@ struct r600_pipe_shader {
unsigned flatshade;
unsigned pa_cl_vs_out_cntl;
unsigned nr_ps_color_outputs;
unsigned ps_color_export_mask;
union r600_shader_key key;
unsigned db_shader_control;
unsigned ps_depth_export;

2
src/gallium/drivers/r600/r600_state.c
View file

@ -1526,7 +1526,7 @@ static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom
radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
} else {
unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
unsigned ps_colormask = a->ps_color_export_mask;
unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);

4
src/gallium/drivers/r600/r600_state_common.c
View file

@ -1749,8 +1749,10 @@ static bool r600_update_derived_state(struct r600_context *rctx)
rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable ||
rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade)) {
if (rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
if (rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs ||
rctx->cb_misc_state.ps_color_export_mask != rctx->ps_shader->current->ps_color_export_mask) {
rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
rctx->cb_misc_state.ps_color_export_mask = rctx->ps_shader->current->ps_color_export_mask;
r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
}