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etnaviv: isa: Do src swizzle with isaspec
Remove this logic from the gallium driver and just use the src's as provided by nir. The special cases, where there is no 1:1 mapping, do still exist. Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28922>
This commit is contained in:
Christian Gmeiner
Marge Bot
parent
894f7f4387
commit
5aede1a157
3 changed files with 118 additions and 90 deletions
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@ -484,6 +484,14 @@ SPDX-License-Identifier: MIT
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</field>
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<field name="SRC2_AMODE" low="121" high="123" type="#reg_addressing_mode"/>
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<field name="SRC2_RGROUP" low="124" high="126" type="#reg_group"/>
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<encode type="struct etna_inst *" case-prefix="ISA_OPC_">
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<map name="SRC2">&src->src[0]</map>
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<map name="SRC2_USE">rc->src[0].use</map>
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<map name="SRC2_REG">src->src[0].reg</map>
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<map name="SRC2_RGROUP">src->src[0].rgroup</map>
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<map name="SRC2_AMODE">src->src[0].amode</map>
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</encode>
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</bitset>
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<bitset name="#instruction-alu-src0-src1" extends="#instruction-alu">
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@ -558,6 +566,14 @@ SPDX-License-Identifier: MIT
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</field>
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<field name="SRC2_AMODE" low="121" high="123" type="#reg_addressing_mode"/>
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<field name="SRC2_RGROUP" low="124" high="126" type="#reg_group"/>
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<encode type="struct etna_inst *" case-prefix="ISA_OPC_">
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<map name="SRC2">&src->src[1]</map>
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<map name="SRC2_USE">rc->src[1].use</map>
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<map name="SRC2_REG">src->src[1].reg</map>
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<map name="SRC2_RGROUP">src->src[1].rgroup</map>
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<map name="SRC2_AMODE">src->src[1].amode</map>
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</encode>
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</bitset>
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<bitset name="#instruction-alu-src1-src2" extends="#instruction-alu">
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@ -595,6 +611,19 @@ SPDX-License-Identifier: MIT
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</field>
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<field name="SRC2_AMODE" low="121" high="123" type="#reg_addressing_mode"/>
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<field name="SRC2_RGROUP" low="124" high="126" type="#reg_group"/>
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<encode type="struct etna_inst *" case-prefix="ISA_OPC_">
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<map name="SRC1">&src->src[0]</map>
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<map name="SRC1_USE">rc->src[0].use</map>
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<map name="SRC1_REG">src->src[0].reg</map>
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<map name="SRC1_RGROUP">src->src[0].rgroup</map>
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<map name="SRC1_AMODE">src->src[0].amode</map>
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<map name="SRC2">&src->src[1]</map>
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<map name="SRC2_USE">rc->src[1].use</map>
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<map name="SRC2_REG">src->src[1].reg</map>
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<map name="SRC2_RGROUP">src->src[1].rgroup</map>
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<map name="SRC2_AMODE">src->src[1].amode</map>
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</encode>
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</bitset>
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<bitset name="#instruction-alu-src0-src1-src2" extends="#instruction-alu">
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@ -576,12 +576,12 @@ emit_intrinsic(struct etna_compile *c, nir_intrinsic_instr * intr)
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.opcode = ISA_OPC_MOVAR,
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.dst.use = 1,
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.dst.write_mask = ISA_WRMASK_X___,
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.src[2] = get_src(c, &intr->src[0]),
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.src[0] = get_src(c, &intr->src[0]),
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});
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emit_inst(c, &(struct etna_inst) {
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.opcode = ISA_OPC_MOV,
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.dst = dst,
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.src[2] = {
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.src[0] = {
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.use = 1,
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.rgroup = ISA_REG_GROUP_UNIFORM_0,
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.reg = nir_intrinsic_base(intr),
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@ -27,21 +27,9 @@
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#include "etnaviv_compiler_nir.h"
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#include "util/compiler.h"
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/* to map nir srcs should to etna_inst srcs */
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enum {
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SRC_0_1_2 = (0 << 0) | (1 << 2) | (2 << 4),
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SRC_0_1_X = (0 << 0) | (1 << 2) | (3 << 4),
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SRC_0_X_X = (0 << 0) | (3 << 2) | (3 << 4),
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SRC_0_X_1 = (0 << 0) | (3 << 2) | (1 << 4),
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SRC_0_1_0 = (0 << 0) | (1 << 2) | (0 << 4),
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SRC_X_X_0 = (3 << 0) | (3 << 2) | (0 << 4),
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SRC_0_X_0 = (0 << 0) | (3 << 2) | (0 << 4),
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};
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/* info to translate a nir op to etna_inst */
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struct etna_op_info {
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enum isa_opc opcode;
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uint8_t src; /* SRC_ enum */
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enum isa_cond cond;
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enum isa_type type;
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};
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@ -50,85 +38,84 @@ static const struct etna_op_info etna_ops[] = {
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[0 ... nir_num_opcodes - 1] = {0xff},
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#undef TRUE
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#undef FALSE
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#define OPCT(nir, op, src, cond, type) [nir_op_##nir] = { \
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#define OPCT(nir, op, cond, type) [nir_op_##nir] = { \
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ISA_OPC_##op, \
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SRC_##src, \
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ISA_COND_##cond, \
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ISA_TYPE_##type \
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}
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#define OPC(nir, op, src, cond) OPCT(nir, op, src, cond, F32)
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#define IOPC(nir, op, src, cond) OPCT(nir, op, src, cond, S32)
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#define UOPC(nir, op, src, cond) OPCT(nir, op, src, cond, U32)
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#define OP(nir, op, src) OPC(nir, op, src, TRUE)
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#define IOP(nir, op, src) IOPC(nir, op, src, TRUE)
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#define UOP(nir, op, src) UOPC(nir, op, src, TRUE)
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OP(mov, MOV, X_X_0), OP(fneg, MOV, X_X_0), OP(fabs, MOV, X_X_0), OP(fsat, MOV, X_X_0),
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OP(fmul, MUL, 0_1_X), OP(fadd, ADD, 0_X_1), OP(ffma, MAD, 0_1_2),
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OP(fdot2, DP2, 0_1_X), OP(fdot3, DP3, 0_1_X), OP(fdot4, DP4, 0_1_X),
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OPC(fmin, SELECT, 0_1_0, GT), OPC(fmax, SELECT, 0_1_0, LT),
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OP(ffract, FRC, X_X_0), OP(frcp, RCP, X_X_0), OP(frsq, RSQ, X_X_0),
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OP(fsqrt, SQRT, X_X_0), OP(fsin, SIN, X_X_0), OP(fcos, COS, X_X_0),
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OP(fsign, SIGN, X_X_0), OP(ffloor, FLOOR, X_X_0), OP(fceil, CEIL, X_X_0),
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OP(flog2, LOG, X_X_0), OP(fexp2, EXP, X_X_0),
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OPC(seq, SET, 0_1_X, EQ), OPC(sne, SET, 0_1_X, NE), OPC(sge, SET, 0_1_X, GE), OPC(slt, SET, 0_1_X, LT),
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OPC(fcsel, SELECT, 0_1_2, NZ),
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OP(fdiv, DIV, 0_1_X),
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OP(fddx, DSX, 0_X_0), OP(fddy, DSY, 0_X_0),
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#define OPC(nir, op, cond) OPCT(nir, op, cond, F32)
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#define IOPC(nir, op, cond) OPCT(nir, op, cond, S32)
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#define UOPC(nir, op, cond) OPCT(nir, op, cond, U32)
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#define OP(nir, op) OPC(nir, op, TRUE)
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#define IOP(nir, op) IOPC(nir, op, TRUE)
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#define UOP(nir, op) UOPC(nir, op, TRUE)
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OP(mov, MOV), OP(fneg, MOV), OP(fabs, MOV), OP(fsat, MOV),
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OP(fmul, MUL), OP(fadd, ADD), OP(ffma, MAD),
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OP(fdot2, DP2), OP(fdot3, DP3), OP(fdot4, DP4),
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OPC(fmin, SELECT, GT), OPC(fmax, SELECT, LT),
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OP(ffract, FRC), OP(frcp, RCP), OP(frsq, RSQ),
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OP(fsqrt, SQRT), OP(fsin, SIN), OP(fcos, COS),
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OP(fsign, SIGN), OP(ffloor, FLOOR), OP(fceil, CEIL),
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OP(flog2, LOG), OP(fexp2, EXP),
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OPC(seq, SET, EQ), OPC(sne, SET, NE), OPC(sge, SET, GE), OPC(slt, SET, LT),
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OPC(fcsel, SELECT, NZ),
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OP(fdiv, DIV),
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OP(fddx, DSX), OP(fddy, DSY),
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/* type convert */
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IOP(i2f32, I2F, 0_X_X),
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IOP(i2i32, I2I, 0_X_X),
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OPCT(i2i16, I2I, 0_X_X, TRUE, S16),
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OPCT(i2i8, I2I, 0_X_X, TRUE, S8),
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UOP(u2f32, I2F, 0_X_X),
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UOP(u2u32, I2I, 0_X_X),
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OPCT(u2u16, I2I, 0_X_X, TRUE, U16),
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OPCT(u2u8, I2I, 0_X_X, TRUE, U8),
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IOP(f2i32, F2I, 0_X_X),
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OPCT(f2i16, F2I, 0_X_X, TRUE, S16),
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OPCT(f2i8, F2I, 0_X_X, TRUE, S8),
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UOP(f2u32, F2I, 0_X_X),
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OPCT(f2u16, F2I, 0_X_X, TRUE, U16),
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OPCT(f2u8, F2I, 0_X_X, TRUE, U8),
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UOP(b2f32, AND, 0_X_X), /* AND with fui(1.0f) */
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UOP(b2i32, AND, 0_X_X), /* AND with 1 */
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IOP(i2f32, I2F),
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IOP(i2i32, I2I),
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OPCT(i2i16, I2I, TRUE, S16),
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OPCT(i2i8, I2I, TRUE, S8),
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UOP(u2f32, I2F),
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UOP(u2u32, I2I),
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OPCT(u2u16, I2I, TRUE, U16),
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OPCT(u2u8, I2I, TRUE, U8),
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IOP(f2i32, F2I),
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OPCT(f2i16, F2I, TRUE, S16),
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OPCT(f2i8, F2I, TRUE, S8),
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UOP(f2u32, F2I),
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OPCT(f2u16, F2I, TRUE, U16),
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OPCT(f2u8, F2I, TRUE, U8),
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UOP(b2f32, AND), /* AND with fui(1.0f) */
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UOP(b2i32, AND), /* AND with 1 */
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/* arithmetic */
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IOP(iadd, ADD, 0_X_1),
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IOP(imul, IMULLO0, 0_1_X),
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/* IOP(imad, IMADLO0, 0_1_2), */
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IOP(ineg, ADD, X_X_0), /* ADD 0, -x */
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IOP(iabs, IABS, X_X_0),
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IOP(isign, SIGN, X_X_0),
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IOPC(imin, SELECT, 0_1_0, GT),
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IOPC(imax, SELECT, 0_1_0, LT),
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UOPC(umin, SELECT, 0_1_0, GT),
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UOPC(umax, SELECT, 0_1_0, LT),
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IOP(iadd, ADD),
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IOP(imul, IMULLO0),
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/* IOP(imad, IMADLO0), */
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IOP(ineg, ADD), /* ADD 0, -x */
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IOP(iabs, IABS),
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IOP(isign, SIGN),
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IOPC(imin, SELECT, GT),
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IOPC(imax, SELECT, LT),
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UOPC(umin, SELECT, GT),
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UOPC(umax, SELECT, LT),
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/* select */
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UOPC(b32csel, SELECT, 0_1_2, NZ),
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UOPC(b32csel, SELECT, NZ),
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/* compare with int result */
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OPC(feq32, CMP, 0_1_X, EQ),
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OPC(fneu32, CMP, 0_1_X, NE),
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OPC(fge32, CMP, 0_1_X, GE),
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OPC(flt32, CMP, 0_1_X, LT),
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IOPC(ieq32, CMP, 0_1_X, EQ),
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IOPC(ine32, CMP, 0_1_X, NE),
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IOPC(ige32, CMP, 0_1_X, GE),
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IOPC(ilt32, CMP, 0_1_X, LT),
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UOPC(uge32, CMP, 0_1_X, GE),
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UOPC(ult32, CMP, 0_1_X, LT),
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OPC(feq32, CMP, EQ),
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OPC(fneu32, CMP, NE),
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OPC(fge32, CMP, GE),
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OPC(flt32, CMP, LT),
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IOPC(ieq32, CMP, EQ),
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IOPC(ine32, CMP, NE),
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IOPC(ige32, CMP, GE),
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IOPC(ilt32, CMP, LT),
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UOPC(uge32, CMP, GE),
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UOPC(ult32, CMP, LT),
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/* bit ops */
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IOP(ior, OR, 0_X_1),
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IOP(iand, AND, 0_X_1),
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IOP(ixor, XOR, 0_X_1),
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IOP(inot, NOT, X_X_0),
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IOP(ishl, LSHIFT, 0_X_1),
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IOP(ishr, RSHIFT, 0_X_1),
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UOP(ushr, RSHIFT, 0_X_1),
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UOP(uclz, LEADZERO, 0_X_X),
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IOP(ior, OR),
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IOP(iand, AND),
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IOP(ixor, XOR),
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IOP(inot, NOT),
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IOP(ishl, LSHIFT),
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IOP(ishr, RSHIFT),
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UOP(ushr, RSHIFT),
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UOP(uclz, LEADZERO),
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};
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void
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@ -147,6 +134,10 @@ etna_emit_alu(struct etna_compile *c, nir_op op, struct etna_inst_dst dst,
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.cond = ei.cond,
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.dst = dst,
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.sat = saturate,
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.src[0] = src[0],
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.src[1] = src[1],
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.src[2] = src[2],
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};
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switch (op) {
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@ -163,19 +154,33 @@ etna_emit_alu(struct etna_compile *c, nir_op op, struct etna_inst_dst dst,
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case nir_op_fsqrt:
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case nir_op_imul:
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/* scalar instructions we want src to be in x component */
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src[0].swiz = inst_swiz_compose(src[0].swiz, swiz_scalar);
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src[1].swiz = inst_swiz_compose(src[1].swiz, swiz_scalar);
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inst.src[0].swiz = inst_swiz_compose(src[0].swiz, swiz_scalar);
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inst.src[1].swiz = inst_swiz_compose(src[1].swiz, swiz_scalar);
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break;
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/* deal with instructions which don't have 1:1 mapping */
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case nir_op_fddx:
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case nir_op_fddy:
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inst.src[1] = src[0];
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break;
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case nir_op_fmin:
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case nir_op_fmax:
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case nir_op_imin:
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case nir_op_imax:
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case nir_op_umin:
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case nir_op_umax:
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inst.src[2] = src[0];
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break;
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case nir_op_b2f32:
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inst.src[2] = etna_immediate_float(1.0f);
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inst.src[1] = etna_immediate_float(1.0f);
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break;
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case nir_op_b2i32:
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inst.src[2] = etna_immediate_int(1);
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inst.src[1] = etna_immediate_int(1);
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break;
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case nir_op_ineg:
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/* ADD 0, -x */
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inst.src[0] = etna_immediate_int(0);
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src[0].neg = 1;
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inst.src[1] = src[0];
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inst.src[1].neg = 1;
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break;
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default:
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break;
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@ -185,12 +190,6 @@ etna_emit_alu(struct etna_compile *c, nir_op op, struct etna_inst_dst dst,
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if (inst.opcode == ISA_OPC_CMP)
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inst.src[2] = etna_immediate_int(-1);
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for (unsigned j = 0; j < 3; j++) {
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unsigned i = ((ei.src >> j*2) & 3);
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if (i < 3)
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inst.src[j] = src[i];
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}
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emit_inst(c, &inst);
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}
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