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panfrost: invert and rename no_ubo_to_push flag
only the GL driver actually wants this, neither panvk nor internal shaders do.
Cc'd as a prereq to the next patch
Cc: mesa-stable
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34193>
(cherry picked from commit f179f6952f)
This commit is contained in:
parent
4fde719367
commit
5ad25a98ef
10 changed files with 7 additions and 11 deletions
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@ -2424,7 +2424,7 @@
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"description": "panfrost: invert and rename no_ubo_to_push flag",
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"nominated": true,
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"nomination_type": 1,
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"resolution": 0,
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"resolution": 1,
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"main_sha": null,
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"because_sha": null,
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"notes": null
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@ -130,6 +130,7 @@ panfrost_shader_compile(struct panfrost_screen *screen, const nir_shader *ir,
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struct panfrost_compile_inputs inputs = {
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.debug = dbg,
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.gpu_id = panfrost_device_gpu_id(dev),
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.push_uniforms = true,
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};
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if (dev->arch >= 9)
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@ -1229,7 +1229,7 @@ bi_emit_load_ubo(bi_builder *b, nir_intrinsic_instr *instr)
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static void
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bi_emit_load_push_constant(bi_builder *b, nir_intrinsic_instr *instr)
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{
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assert(b->shader->inputs->no_ubo_to_push && "can't mix push constant forms");
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assert(!b->shader->inputs->push_uniforms && "can't mix push constant forms");
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nir_src *offset = &instr->src[0];
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assert(!nir_intrinsic_base(instr) && "base must be zero");
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@ -5571,7 +5571,7 @@ bi_compile_variant_nir(nir_shader *nir,
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bi_validate(ctx, "Early lowering");
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/* Runs before copy prop */
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if (optimize && !ctx->inputs->no_ubo_to_push) {
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if (optimize && ctx->inputs->push_uniforms) {
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bi_opt_push_ubo(ctx);
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}
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@ -5596,7 +5596,7 @@ bi_compile_variant_nir(nir_shader *nir,
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bi_opt_dce(ctx, false);
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bi_opt_cse(ctx);
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bi_opt_dce(ctx, false);
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if (!ctx->inputs->no_ubo_to_push)
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if (ctx->inputs->push_uniforms)
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bi_opt_reorder_push(ctx);
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bi_validate(ctx, "Optimization passes");
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}
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@ -108,7 +108,6 @@ pan_indirect_dispatch_init(struct pan_indirect_dispatch_meta *meta)
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struct panfrost_compile_inputs inputs = {
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.gpu_id = meta->gpu_id,
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.no_ubo_to_push = true,
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};
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struct pan_shader_info shader_info;
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struct util_dynarray binary;
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@ -265,7 +265,7 @@ mir_special_indices(compiler_context *ctx)
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void
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midgard_promote_uniforms(compiler_context *ctx)
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{
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if (ctx->inputs->no_ubo_to_push) {
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if (!ctx->inputs->push_uniforms) {
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/* If nothing is pushed, all UBOs need to be uploaded
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* conventionally */
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ctx->ubo_mask = ~0;
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@ -104,7 +104,7 @@ struct panfrost_compile_inputs {
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uint64_t bifrost_blend_desc;
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} blend;
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bool no_idvs;
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bool no_ubo_to_push;
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bool push_uniforms;
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uint32_t view_mask;
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/* Used on Valhall.
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@ -294,7 +294,6 @@ panvk_meta_desc_copy_rsd(struct panvk_device *dev)
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struct panfrost_compile_inputs inputs = {
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.gpu_id = phys_dev->kmod.props.gpu_prod_id,
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.no_ubo_to_push = true,
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};
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pan_shader_preprocess(b.shader, inputs.gpu_id);
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@ -89,7 +89,6 @@ get_blend_shader(struct panvk_device *dev,
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/* Compile the NIR shader */
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struct panfrost_compile_inputs inputs = {
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.gpu_id = pdev->kmod.props.gpu_prod_id,
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.no_ubo_to_push = true,
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.is_blend = true,
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.blend = {
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.nr_samples = key.info.nr_samples,
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@ -171,7 +171,6 @@ get_preload_shader(struct panvk_device *dev,
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struct panfrost_compile_inputs inputs = {
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.gpu_id = phys_dev->kmod.props.gpu_prod_id,
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.no_ubo_to_push = true,
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.is_blit = true,
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};
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@ -1050,7 +1050,6 @@ panvk_compile_shader(struct panvk_device *dev,
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struct panfrost_compile_inputs inputs = {
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.gpu_id = phys_dev->kmod.props.gpu_prod_id,
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.no_ubo_to_push = true,
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.view_mask = (state && state->rp) ? state->rp->view_mask : 0,
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};
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