From 5ac82efd3513cc4b580ce11fdbdffda5c430cf8e Mon Sep 17 00:00:00 2001 From: Caio Oliveira Date: Sun, 29 Dec 2024 15:41:04 -0800 Subject: [PATCH] intel/brw: Rename fs_builder to brw_builder Reviewed-by: Lionel Landwerlin Part-of: --- src/intel/compiler/brw_builder.h | 50 +-- src/intel/compiler/brw_compile_cs.cpp | 4 +- src/intel/compiler/brw_compile_fs.cpp | 26 +- src/intel/compiler/brw_compile_gs.cpp | 6 +- src/intel/compiler/brw_compile_mesh.cpp | 2 +- src/intel/compiler/brw_compile_tcs.cpp | 6 +- src/intel/compiler/brw_fs.cpp | 20 +- src/intel/compiler/brw_fs.h | 18 +- src/intel/compiler/brw_fs_nir.cpp | 300 +++++++++--------- src/intel/compiler/brw_fs_reg_allocate.cpp | 38 +-- src/intel/compiler/brw_fs_thread_payload.cpp | 8 +- src/intel/compiler/brw_fs_visitor.cpp | 6 +- src/intel/compiler/brw_lower.cpp | 34 +- src/intel/compiler/brw_lower_dpas.cpp | 8 +- .../brw_lower_integer_multiplication.cpp | 6 +- .../compiler/brw_lower_logical_sends.cpp | 98 +++--- src/intel/compiler/brw_lower_pack.cpp | 2 +- src/intel/compiler/brw_lower_regioning.cpp | 12 +- src/intel/compiler/brw_lower_scoreboard.cpp | 8 +- src/intel/compiler/brw_lower_simd_width.cpp | 16 +- src/intel/compiler/brw_lower_subgroup_ops.cpp | 50 +-- src/intel/compiler/brw_opt.cpp | 2 +- .../compiler/brw_opt_address_reg_load.cpp | 2 +- .../compiler/brw_opt_combine_constants.cpp | 2 +- src/intel/compiler/brw_opt_cse.cpp | 4 +- src/intel/compiler/brw_opt_txf_combiner.cpp | 8 +- src/intel/compiler/brw_opt_virtual_grfs.cpp | 2 +- src/intel/compiler/brw_workaround.cpp | 14 +- src/intel/compiler/test_lower_scoreboard.cpp | 6 +- .../compiler/test_opt_cmod_propagation.cpp | 4 +- .../compiler/test_opt_combine_constants.cpp | 8 +- .../compiler/test_opt_copy_propagation.cpp | 4 +- src/intel/compiler/test_opt_cse.cpp | 4 +- .../test_opt_saturate_propagation.cpp | 4 +- 34 files changed, 391 insertions(+), 391 deletions(-) diff --git a/src/intel/compiler/brw_builder.h b/src/intel/compiler/brw_builder.h index a51d867895c..e830ad6494c 100644 --- a/src/intel/compiler/brw_builder.h +++ b/src/intel/compiler/brw_builder.h @@ -28,21 +28,21 @@ #include "brw_eu.h" #include "brw_fs.h" -static inline brw_reg offset(const brw_reg &, const brw::fs_builder &, +static inline brw_reg offset(const brw_reg &, const brw::brw_builder &, unsigned); namespace brw { /** - * Toolbox to assemble an FS IR program out of individual instructions. + * Toolbox to assemble an BRW IR program out of individual instructions. */ - class fs_builder { + class brw_builder { public: /** - * Construct an fs_builder that inserts instructions into \p shader. + * Construct an brw_builder that inserts instructions into \p shader. * \p dispatch_width gives the native execution width of the program. */ - fs_builder(fs_visitor *shader, - unsigned dispatch_width) : + brw_builder(fs_visitor *shader, + unsigned dispatch_width) : shader(shader), block(NULL), cursor(NULL), _dispatch_width(dispatch_width), _group(0), @@ -51,15 +51,15 @@ namespace brw { { } - explicit fs_builder(fs_visitor *s) : fs_builder(s, s->dispatch_width) {} + explicit brw_builder(fs_visitor *s) : brw_builder(s, s->dispatch_width) {} /** - * Construct an fs_builder that inserts instructions into \p shader + * Construct an brw_builder that inserts instructions into \p shader * before instruction \p inst in basic block \p block. The default * execution controls and debug annotation are initialized from the * instruction passed as argument. */ - fs_builder(fs_visitor *shader, bblock_t *block, fs_inst *inst) : + brw_builder(fs_visitor *shader, bblock_t *block, fs_inst *inst) : shader(shader), block(block), cursor(inst), _dispatch_width(inst->exec_size), _group(inst->group), @@ -73,25 +73,25 @@ namespace brw { } /** - * Construct an fs_builder that inserts instructions before \p cursor in + * Construct an brw_builder that inserts instructions before \p cursor in * basic block \p block, inheriting other code generation parameters * from this. */ - fs_builder + brw_builder at(bblock_t *block, exec_node *cursor) const { - fs_builder bld = *this; + brw_builder bld = *this; bld.block = block; bld.cursor = cursor; return bld; } /** - * Construct an fs_builder appending instructions at the end of the + * Construct an brw_builder appending instructions at the end of the * instruction list of the shader, inheriting other code generation * parameters from this. */ - fs_builder + brw_builder at_end() const { return at(NULL, (exec_node *)&shader->instructions.tail_sentinel); @@ -105,10 +105,10 @@ namespace brw { * \p n gives the default SIMD width, \p i gives the slot group used for * predication and control flow masking in multiples of \p n channels. */ - fs_builder + brw_builder group(unsigned n, unsigned i) const { - fs_builder bld = *this; + brw_builder bld = *this; if (n <= dispatch_width() && i < dispatch_width() / n) { bld._group += i * n; @@ -133,7 +133,7 @@ namespace brw { /** * Alias for group() with width equal to eight. */ - fs_builder + brw_builder quarter(unsigned i) const { return group(8, i); @@ -144,10 +144,10 @@ namespace brw { * disabled if \p b is true. If control flow execution masking is * already disabled this has no effect. */ - fs_builder + brw_builder exec_all(bool b = true) const { - fs_builder bld = *this; + brw_builder bld = *this; if (b) bld.force_writemask_all = true; return bld; @@ -156,7 +156,7 @@ namespace brw { /** * Construct a builder for SIMD8-as-scalar */ - fs_builder + brw_builder scalar_group() const { return exec_all().group(8 * reg_unit(shader->devinfo), 0); @@ -165,10 +165,10 @@ namespace brw { /** * Construct a builder with the given debug annotation info. */ - fs_builder + brw_builder annotate(const char *str) const { - fs_builder bld = *this; + brw_builder bld = *this; bld.annotation.str = str; return bld; } @@ -400,7 +400,7 @@ namespace brw { * send). Once we teach const/copy propagation about scalars we * should go back to scalar destinations here. */ - const fs_builder xbld = scalar_group(); + const brw_builder xbld = scalar_group(); const brw_reg chan_index = xbld.vgrf(BRW_TYPE_UD); /* FIND_LIVE_CHANNEL will only write a single component after @@ -813,7 +813,7 @@ namespace brw { brw_reg BROADCAST(brw_reg value, brw_reg index) const { - const fs_builder xbld = scalar_group(); + const brw_builder xbld = scalar_group(); const brw_reg dst = xbld.vgrf(value.type); assert(is_uniform(index)); @@ -931,7 +931,7 @@ namespace brw { * stored differently, so care must be taken to offset properly. */ static inline brw_reg -offset(const brw_reg ®, const brw::fs_builder &bld, unsigned delta) +offset(const brw_reg ®, const brw::brw_builder &bld, unsigned delta) { /* If the value is convergent (stored as one or more SIMD8), offset using * SIMD8 and select component 0. diff --git a/src/intel/compiler/brw_compile_cs.cpp b/src/intel/compiler/brw_compile_cs.cpp index db898524629..4b1fe6ae974 100644 --- a/src/intel/compiler/brw_compile_cs.cpp +++ b/src/intel/compiler/brw_compile_cs.cpp @@ -64,13 +64,13 @@ static bool run_cs(fs_visitor &s, bool allow_spilling) { assert(gl_shader_stage_is_compute(s.stage)); - const fs_builder bld = fs_builder(&s).at_end(); + const brw_builder bld = brw_builder(&s).at_end(); s.payload_ = new cs_thread_payload(s); if (s.devinfo->platform == INTEL_PLATFORM_HSW && s.prog_data->total_shared > 0) { /* Move SLM index from g0.0[27:24] to sr0.1[11:8] */ - const fs_builder abld = bld.exec_all().group(1, 0); + const brw_builder abld = bld.exec_all().group(1, 0); abld.MOV(retype(brw_sr0_reg(1), BRW_TYPE_UW), suboffset(retype(brw_vec1_grf(0, 0), BRW_TYPE_UW), 1)); } diff --git a/src/intel/compiler/brw_compile_fs.cpp b/src/intel/compiler/brw_compile_fs.cpp index 3b7c965f878..f4b1fd71ce5 100644 --- a/src/intel/compiler/brw_compile_fs.cpp +++ b/src/intel/compiler/brw_compile_fs.cpp @@ -21,7 +21,7 @@ using namespace brw; static fs_inst * -brw_emit_single_fb_write(fs_visitor &s, const fs_builder &bld, +brw_emit_single_fb_write(fs_visitor &s, const brw_builder &bld, brw_reg color0, brw_reg color1, brw_reg src0_alpha, unsigned components, bool null_rt) @@ -61,7 +61,7 @@ brw_emit_single_fb_write(fs_visitor &s, const fs_builder &bld, static void brw_do_emit_fb_writes(fs_visitor &s, int nr_color_regions, bool replicate_alpha) { - const fs_builder bld = fs_builder(&s).at_end(); + const brw_builder bld = brw_builder(&s).at_end(); fs_inst *inst = NULL; for (int target = 0; target < nr_color_regions; target++) { @@ -69,7 +69,7 @@ brw_do_emit_fb_writes(fs_visitor &s, int nr_color_regions, bool replicate_alpha) if (s.outputs[target].file == BAD_FILE) continue; - const fs_builder abld = bld.annotate( + const brw_builder abld = bld.annotate( ralloc_asprintf(s.mem_ctx, "FB write target %d", target)); brw_reg src0_alpha; @@ -184,8 +184,8 @@ static void brw_emit_interpolation_setup(fs_visitor &s) { const struct intel_device_info *devinfo = s.devinfo; - const fs_builder bld = fs_builder(&s).at_end(); - fs_builder abld = bld.annotate("compute pixel centers"); + const brw_builder bld = brw_builder(&s).at_end(); + brw_builder abld = bld.annotate("compute pixel centers"); s.pixel_x = bld.vgrf(BRW_TYPE_F); s.pixel_y = bld.vgrf(BRW_TYPE_F); @@ -255,7 +255,7 @@ brw_emit_interpolation_setup(fs_visitor &s) */ struct brw_reg r1_0 = retype(brw_vec1_reg(FIXED_GRF, 1, 0), BRW_TYPE_UB); - const fs_builder dbld = + const brw_builder dbld = abld.exec_all().group(MIN2(16, s.dispatch_width) * 2, 0); if (devinfo->verx10 >= 125) { @@ -305,7 +305,7 @@ brw_emit_interpolation_setup(fs_visitor &s) break; case INTEL_SOMETIMES: { - const fs_builder dbld = + const brw_builder dbld = abld.exec_all().group(MIN2(16, s.dispatch_width) * 2, 0); check_dynamic_msaa_flag(dbld, wm_prog_data, @@ -353,7 +353,7 @@ brw_emit_interpolation_setup(fs_visitor &s) } for (unsigned i = 0; i < DIV_ROUND_UP(s.dispatch_width, 16); i++) { - const fs_builder hbld = abld.group(MIN2(16, s.dispatch_width), i); + const brw_builder hbld = abld.group(MIN2(16, s.dispatch_width), i); /* According to the "PS Thread Payload for Normal Dispatch" * pages on the BSpec, subspan X/Y coordinates are stored in * R1.2-R1.5/R2.2-R2.5 on gfx6+, and on R0.10-R0.13/R1.10-R1.13 @@ -365,7 +365,7 @@ brw_emit_interpolation_setup(fs_visitor &s) const struct brw_reg gi_uw = retype(gi_reg, BRW_TYPE_UW); if (devinfo->verx10 >= 125) { - const fs_builder dbld = + const brw_builder dbld = abld.exec_all().group(hbld.dispatch_width() * 2, 0); const brw_reg int_pixel_x = dbld.vgrf(BRW_TYPE_UW); const brw_reg int_pixel_y = dbld.vgrf(BRW_TYPE_UW); @@ -402,7 +402,7 @@ brw_emit_interpolation_setup(fs_visitor &s) * Thus we can do a single add(16) in SIMD8 or an add(32) in SIMD16 * to compute our pixel centers. */ - const fs_builder dbld = + const brw_builder dbld = abld.exec_all().group(hbld.dispatch_width() * 2, 0); brw_reg int_pixel_xy = dbld.vgrf(BRW_TYPE_UW); @@ -511,7 +511,7 @@ brw_emit_interpolation_setup(fs_visitor &s) if (wm_key->persample_interp == INTEL_SOMETIMES) { assert(!devinfo->needs_unlit_centroid_workaround); - const fs_builder ubld = bld.exec_all().group(16, 0); + const brw_builder ubld = bld.exec_all().group(16, 0); bool loaded_flag = false; for (int i = 0; i < INTEL_BARYCENTRIC_MODE_COUNT; ++i) { @@ -623,7 +623,7 @@ brw_emit_repclear_shader(fs_visitor &s) BRW_VERTICAL_STRIDE_8, BRW_WIDTH_2, BRW_HORIZONTAL_STRIDE_4, BRW_SWIZZLE_XYZW, WRITEMASK_XYZW); - const fs_builder bld = fs_builder(&s).at_end(); + const brw_builder bld = brw_builder(&s).at_end(); bld.exec_all().group(4, 0).MOV(color_output, color_input); if (key->nr_color_regions > 1) { @@ -1460,7 +1460,7 @@ run_fs(fs_visitor &s, bool allow_spilling, bool do_rep_send) const struct intel_device_info *devinfo = s.devinfo; struct brw_wm_prog_data *wm_prog_data = brw_wm_prog_data(s.prog_data); brw_wm_prog_key *wm_key = (brw_wm_prog_key *) s.key; - const fs_builder bld = fs_builder(&s).at_end(); + const brw_builder bld = brw_builder(&s).at_end(); const nir_shader *nir = s.nir; assert(s.stage == MESA_SHADER_FRAGMENT); diff --git a/src/intel/compiler/brw_compile_gs.cpp b/src/intel/compiler/brw_compile_gs.cpp index a312f9d0e3c..e496221b2b6 100644 --- a/src/intel/compiler/brw_compile_gs.cpp +++ b/src/intel/compiler/brw_compile_gs.cpp @@ -42,7 +42,7 @@ brw_emit_gs_thread_end(fs_visitor &s) s.emit_gs_control_data_bits(s.final_gs_vertex_count); } - const fs_builder abld = fs_builder(&s).at_end().annotate("thread end"); + const brw_builder abld = brw_builder(&s).at_end().annotate("thread end"); fs_inst *inst; if (gs_prog_data->static_vertex_count != -1) { @@ -92,7 +92,7 @@ run_gs(fs_visitor &s) s.payload_ = new gs_thread_payload(s); - const fs_builder bld = fs_builder(&s).at_end(); + const brw_builder bld = brw_builder(&s).at_end(); s.final_gs_vertex_count = bld.vgrf(BRW_TYPE_UD); @@ -105,7 +105,7 @@ run_gs(fs_visitor &s) * Otherwise, we need to initialize it to 0 here. */ if (s.gs_compile->control_data_header_size_bits <= 32) { - const fs_builder abld = bld.annotate("initialize control data bits"); + const brw_builder abld = bld.annotate("initialize control data bits"); abld.MOV(s.control_data_bits, brw_imm_ud(0u)); } } diff --git a/src/intel/compiler/brw_compile_mesh.cpp b/src/intel/compiler/brw_compile_mesh.cpp index e9030159dc8..0356852941c 100644 --- a/src/intel/compiler/brw_compile_mesh.cpp +++ b/src/intel/compiler/brw_compile_mesh.cpp @@ -268,7 +268,7 @@ brw_nir_align_launch_mesh_workgroups(nir_shader *nir) static void brw_emit_urb_fence(fs_visitor &s) { - const fs_builder bld1 = fs_builder(&s).at_end().exec_all().group(1, 0); + const brw_builder bld1 = brw_builder(&s).at_end().exec_all().group(1, 0); brw_reg dst = bld1.vgrf(BRW_TYPE_UD); fs_inst *fence = bld1.emit(SHADER_OPCODE_MEMORY_FENCE, dst, brw_vec8_grf(0, 0), diff --git a/src/intel/compiler/brw_compile_tcs.cpp b/src/intel/compiler/brw_compile_tcs.cpp index 7ff8576e111..6348920e734 100644 --- a/src/intel/compiler/brw_compile_tcs.cpp +++ b/src/intel/compiler/brw_compile_tcs.cpp @@ -49,7 +49,7 @@ brw_set_tcs_invocation_id(fs_visitor &s) const struct intel_device_info *devinfo = s.devinfo; struct brw_tcs_prog_data *tcs_prog_data = brw_tcs_prog_data(s.prog_data); struct brw_vue_prog_data *vue_prog_data = &tcs_prog_data->base; - const fs_builder bld = fs_builder(&s).at_end(); + const brw_builder bld = brw_builder(&s).at_end(); const unsigned instance_id_mask = (devinfo->verx10 >= 125) ? INTEL_MASK(7, 0) : @@ -99,7 +99,7 @@ brw_emit_tcs_thread_end(fs_visitor &s) if (s.mark_last_urb_write_with_eot()) return; - const fs_builder bld = fs_builder(&s).at_end(); + const brw_builder bld = brw_builder(&s).at_end(); /* Emit a URB write to end the thread. On Broadwell, we use this to write * zero to the "TR DS Cache Disable" bit (we haven't implemented a fancy @@ -133,7 +133,7 @@ run_tcs(fs_visitor &s) assert(s.stage == MESA_SHADER_TESS_CTRL); struct brw_vue_prog_data *vue_prog_data = brw_vue_prog_data(s.prog_data); - const fs_builder bld = fs_builder(&s).at_end(); + const brw_builder bld = brw_builder(&s).at_end(); assert(vue_prog_data->dispatch_mode == INTEL_DISPATCH_MODE_TCS_SINGLE_PATCH || vue_prog_data->dispatch_mode == INTEL_DISPATCH_MODE_TCS_MULTI_PATCH); diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 2fb6ec8428d..28a736ec909 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -925,7 +925,7 @@ fs_visitor::assign_curb_setup() if (is_compute && devinfo->verx10 >= 125 && uniform_push_length > 0) { assert(devinfo->has_lsc); - fs_builder ubld = fs_builder(this, 1).exec_all().at( + brw_builder ubld = brw_builder(this, 1).exec_all().at( cfg->first_block(), cfg->first_block()->start()); /* The base offset for our push data is passed in as R0.0[31:6]. We have @@ -1031,7 +1031,7 @@ fs_visitor::assign_curb_setup() uint64_t want_zero = used & prog_data->zero_push_reg; if (want_zero) { - fs_builder ubld = fs_builder(this, 8).exec_all().at( + brw_builder ubld = brw_builder(this, 8).exec_all().at( cfg->first_block(), cfg->first_block()->start()); /* push_reg_mask_param is in 32-bit units */ @@ -1048,7 +1048,7 @@ fs_visitor::assign_curb_setup() brw_imm_v(0x01234567)); ubld.SHL(shifted, horiz_offset(shifted, 8), brw_imm_w(8)); - fs_builder ubld16 = ubld.group(16, 0); + brw_builder ubld16 = ubld.group(16, 0); b32 = ubld16.vgrf(BRW_TYPE_D); ubld16.group(16, 0).ASR(b32, shifted, brw_imm_w(15)); } @@ -1159,7 +1159,7 @@ brw_get_subgroup_id_param_index(const intel_device_info *devinfo, * than 16 for fragment shaders. */ brw_reg -brw_sample_mask_reg(const fs_builder &bld) +brw_sample_mask_reg(const brw_builder &bld) { const fs_visitor &s = *bld.shader; @@ -1211,7 +1211,7 @@ brw_fb_write_msg_control(const fs_inst *inst, * Predicate the specified instruction on the sample mask. */ void -brw_emit_predicate_on_sample_mask(const fs_builder &bld, fs_inst *inst) +brw_emit_predicate_on_sample_mask(const brw_builder &bld, fs_inst *inst) { assert(bld.shader->stage == MESA_SHADER_FRAGMENT && bld.group() == inst->group && @@ -1602,7 +1602,7 @@ bool brw_should_print_shader(const nir_shader *shader, uint64_t debug_flag) namespace brw { brw_reg - fetch_payload_reg(const brw::fs_builder &bld, uint8_t regs[2], + fetch_payload_reg(const brw::brw_builder &bld, uint8_t regs[2], brw_reg_type type, unsigned n) { if (!regs[0]) @@ -1610,7 +1610,7 @@ namespace brw { if (bld.dispatch_width() > 16) { const brw_reg tmp = bld.vgrf(type, n); - const brw::fs_builder hbld = bld.exec_all().group(16, 0); + const brw::brw_builder hbld = bld.exec_all().group(16, 0); const unsigned m = bld.dispatch_width() / hbld.dispatch_width(); brw_reg *const components = new brw_reg[m * n]; @@ -1631,7 +1631,7 @@ namespace brw { } brw_reg - fetch_barycentric_reg(const brw::fs_builder &bld, uint8_t regs[2]) + fetch_barycentric_reg(const brw::brw_builder &bld, uint8_t regs[2]) { if (!regs[0]) return brw_reg(); @@ -1639,7 +1639,7 @@ namespace brw { return fetch_payload_reg(bld, regs, BRW_TYPE_F, 2); const brw_reg tmp = bld.vgrf(BRW_TYPE_F, 2); - const brw::fs_builder hbld = bld.exec_all().group(8, 0); + const brw::brw_builder hbld = bld.exec_all().group(8, 0); const unsigned m = bld.dispatch_width() / hbld.dispatch_width(); brw_reg *const components = new brw_reg[2 * m]; @@ -1656,7 +1656,7 @@ namespace brw { } void - check_dynamic_msaa_flag(const fs_builder &bld, + check_dynamic_msaa_flag(const brw_builder &bld, const struct brw_wm_prog_data *wm_prog_data, enum intel_msaa_flags flag) { diff --git a/src/intel/compiler/brw_fs.h b/src/intel/compiler/brw_fs.h index 6cf590ebb19..f282ebe8245 100644 --- a/src/intel/compiler/brw_fs.h +++ b/src/intel/compiler/brw_fs.h @@ -139,7 +139,7 @@ struct brw_gs_compile }; namespace brw { -class fs_builder; +class brw_builder; } struct brw_shader_stats { @@ -216,7 +216,7 @@ struct fs_thread_payload : public thread_payload { struct cs_thread_payload : public thread_payload { cs_thread_payload(const fs_visitor &v); - void load_subgroup_id(const brw::fs_builder &bld, brw_reg &dest) const; + void load_subgroup_id(const brw::brw_builder &bld, brw_reg &dest) const; brw_reg local_invocation_id[3]; @@ -244,7 +244,7 @@ struct bs_thread_payload : public thread_payload { brw_reg global_arg_ptr; brw_reg local_arg_ptr; - void load_shader_type(const brw::fs_builder &bld, brw_reg &dest) const; + void load_shader_type(const brw::brw_builder &bld, brw_reg &dest) const; }; enum instruction_scheduler_mode { @@ -479,12 +479,12 @@ sample_mask_flag_subreg(const fs_visitor &s) namespace brw { brw_reg - fetch_payload_reg(const brw::fs_builder &bld, uint8_t regs[2], + fetch_payload_reg(const brw::brw_builder &bld, uint8_t regs[2], brw_reg_type type = BRW_TYPE_F, unsigned n = 1); brw_reg - fetch_barycentric_reg(const brw::fs_builder &bld, uint8_t regs[2]); + fetch_barycentric_reg(const brw::brw_builder &bld, uint8_t regs[2]); inline brw_reg dynamic_msaa_flags(const struct brw_wm_prog_data *wm_prog_data) @@ -493,7 +493,7 @@ namespace brw { } void - check_dynamic_msaa_flag(const fs_builder &bld, + check_dynamic_msaa_flag(const brw_builder &bld, const struct brw_wm_prog_data *wm_prog_data, enum intel_msaa_flags flag); @@ -501,7 +501,7 @@ namespace brw { lower_src_modifiers(fs_visitor *v, bblock_t *block, fs_inst *inst, unsigned i); } -void shuffle_from_32bit_read(const brw::fs_builder &bld, +void shuffle_from_32bit_read(const brw::brw_builder &bld, const brw_reg &dst, const brw_reg &src, uint32_t first_component, @@ -515,8 +515,8 @@ uint32_t brw_fb_write_msg_control(const fs_inst *inst, void brw_compute_urb_setup_index(struct brw_wm_prog_data *wm_prog_data); -brw_reg brw_sample_mask_reg(const brw::fs_builder &bld); -void brw_emit_predicate_on_sample_mask(const brw::fs_builder &bld, fs_inst *inst); +brw_reg brw_sample_mask_reg(const brw::brw_builder &bld); +void brw_emit_predicate_on_sample_mask(const brw::brw_builder &bld, fs_inst *inst); int brw_get_subgroup_id_param_index(const intel_device_info *devinfo, const brw_stage_prog_data *prog_data); diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 650c4baa849..d1ef8ff45f5 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -53,7 +53,7 @@ struct nir_to_brw_state { /* Points to the end of the program. Annotated with the current NIR * instruction when applicable. */ - fs_builder bld; + brw_builder bld; brw_reg *ssa_values; struct brw_fs_bind_info *ssa_bind_infos; @@ -66,7 +66,7 @@ static brw_reg get_nir_src(nir_to_brw_state &ntb, const nir_src &src, int channe static brw_reg get_nir_def(nir_to_brw_state &ntb, const nir_def &def, bool all_sources_uniform = false); static nir_component_mask_t get_nir_write_mask(const nir_def &def); -static void fs_nir_emit_intrinsic(nir_to_brw_state &ntb, const fs_builder &bld, nir_intrinsic_instr *instr); +static void fs_nir_emit_intrinsic(nir_to_brw_state &ntb, const brw_builder &bld, nir_intrinsic_instr *instr); static brw_reg emit_samplepos_setup(nir_to_brw_state &ntb); static brw_reg emit_sampleid_setup(nir_to_brw_state &ntb); static brw_reg emit_samplemaskin_setup(nir_to_brw_state &ntb); @@ -80,11 +80,11 @@ static void fs_nir_emit_block(nir_to_brw_state &ntb, nir_block *block); static void fs_nir_emit_instr(nir_to_brw_state &ntb, nir_instr *instr); static void fs_nir_emit_memory_access(nir_to_brw_state &ntb, - const fs_builder &bld, - const fs_builder &xbld, + const brw_builder &bld, + const brw_builder &xbld, nir_intrinsic_instr *instr); -static void brw_combine_with_vec(const fs_builder &bld, const brw_reg &dst, +static void brw_combine_with_vec(const brw_builder &bld, const brw_reg &dst, const brw_reg &src, unsigned n); static bool @@ -120,7 +120,7 @@ brw_texture_offset(const nir_tex_instr *tex, unsigned src, } static brw_reg -setup_imm_b(const fs_builder &bld, int8_t v) +setup_imm_b(const brw_builder &bld, int8_t v) { const brw_reg tmp = bld.vgrf(BRW_TYPE_B); bld.MOV(tmp, brw_imm_w(v)); @@ -206,7 +206,7 @@ static brw_reg emit_work_group_id_setup(nir_to_brw_state &ntb) { fs_visitor &s = ntb.s; - const fs_builder &bld = ntb.bld.scalar_group(); + const brw_builder &bld = ntb.bld.scalar_group(); assert(gl_shader_stage_is_compute(s.stage)); @@ -302,7 +302,7 @@ emit_system_values_block(nir_to_brw_state &ntb, nir_block *block) assert(s.stage == MESA_SHADER_FRAGMENT); reg = &ntb.system_values[SYSTEM_VALUE_HELPER_INVOCATION]; if (reg->file == BAD_FILE) { - const fs_builder abld = + const brw_builder abld = ntb.bld.annotate("gl_HelperInvocation"); /* On Gfx6+ (gl_HelperInvocation is only exposed on Gfx7+) the @@ -319,7 +319,7 @@ emit_system_values_block(nir_to_brw_state &ntb, nir_block *block) brw_reg shifted = abld.vgrf(BRW_TYPE_UW); for (unsigned i = 0; i < DIV_ROUND_UP(s.dispatch_width, 16); i++) { - const fs_builder hbld = abld.group(MIN2(16, s.dispatch_width), i); + const brw_builder hbld = abld.group(MIN2(16, s.dispatch_width), i); /* According to the "PS Thread Payload for Normal * Dispatch" pages on the BSpec, the dispatch mask is * stored in R0.15/R1.15 on gfx20+ and in R1.7/R2.7 on @@ -417,7 +417,7 @@ fs_nir_emit_cf_list(nir_to_brw_state &ntb, exec_list *list) static void fs_nir_emit_if(nir_to_brw_state &ntb, nir_if *if_stmt) { - const fs_builder &bld = ntb.bld; + const brw_builder &bld = ntb.bld; bool invert; brw_reg cond_reg; @@ -468,7 +468,7 @@ fs_nir_emit_if(nir_to_brw_state &ntb, nir_if *if_stmt) static void fs_nir_emit_loop(nir_to_brw_state &ntb, nir_loop *loop) { - const fs_builder &bld = ntb.bld; + const brw_builder &bld = ntb.bld; assert(!nir_loop_has_continue_construct(loop)); bld.emit(BRW_OPCODE_DO); @@ -491,7 +491,7 @@ fs_nir_emit_loop(nir_to_brw_state &ntb, nir_loop *loop) static void fs_nir_emit_block(nir_to_brw_state &ntb, nir_block *block) { - fs_builder bld = ntb.bld; + brw_builder bld = ntb.bld; nir_foreach_instr(instr, block) { fs_nir_emit_instr(ntb, instr); @@ -505,7 +505,7 @@ fs_nir_emit_block(nir_to_brw_state &ntb, nir_block *block) * match instr. */ static bool -optimize_extract_to_float(nir_to_brw_state &ntb, const fs_builder &bld, +optimize_extract_to_float(nir_to_brw_state &ntb, const brw_builder &bld, nir_alu_instr *instr, const brw_reg &result) { const intel_device_info *devinfo = ntb.devinfo; @@ -663,7 +663,7 @@ optimize_frontfacing_ternary(nir_to_brw_state &ntb, brw_reg ff = ntb.bld.vgrf(BRW_TYPE_UW); for (unsigned i = 0; i < DIV_ROUND_UP(s.dispatch_width, 16); i++) { - const fs_builder hbld = ntb.bld.group(16, i); + const brw_builder hbld = ntb.bld.group(16, i); const struct brw_reg gi_uw = retype(xe2_vec1_grf(i, 9), BRW_TYPE_UW); hbld.SHL(offset(ff, hbld, i), stride(gi_uw, 1, 8, 0), brw_imm_ud(4)); @@ -685,7 +685,7 @@ optimize_frontfacing_ternary(nir_to_brw_state &ntb, assert(s.dispatch_width == 16); for (unsigned i = 0; i < s.max_polygons; i++) { - const fs_builder hbld = ntb.bld.group(8, i); + const brw_builder hbld = ntb.bld.group(8, i); struct brw_reg g1 = retype(brw_vec1_grf(1, 1 + 5 * i), BRW_TYPE_UW); @@ -763,7 +763,7 @@ brw_rnd_mode_from_execution_mode(unsigned execution_mode) static brw_reg prepare_alu_destination_and_sources(nir_to_brw_state &ntb, - const fs_builder &bld, + const brw_builder &bld, nir_alu_instr *instr, brw_reg *op, bool need_dest) @@ -809,7 +809,7 @@ prepare_alu_destination_and_sources(nir_to_brw_state &ntb, } const bool is_scalar = result.is_scalar || (!need_dest && all_sources_uniform); - const fs_builder xbld = is_scalar ? bld.scalar_group() : bld; + const brw_builder xbld = is_scalar ? bld.scalar_group() : bld; /* At this point, we have dealt with any instruction that operates on * more than a single channel. Therefore, we can just adjust the source @@ -842,13 +842,13 @@ prepare_alu_destination_and_sources(nir_to_brw_state &ntb, } static brw_reg -resolve_source_modifiers(const fs_builder &bld, const brw_reg &src) +resolve_source_modifiers(const brw_builder &bld, const brw_reg &src) { return (src.abs || src.negate) ? bld.MOV(src) : src; } static void -resolve_inot_sources(nir_to_brw_state &ntb, const fs_builder &bld, nir_alu_instr *instr, +resolve_inot_sources(nir_to_brw_state &ntb, const brw_builder &bld, nir_alu_instr *instr, brw_reg *op) { for (unsigned i = 0; i < 2; i++) { @@ -867,7 +867,7 @@ resolve_inot_sources(nir_to_brw_state &ntb, const fs_builder &bld, nir_alu_instr } static bool -try_emit_b2fi_of_inot(nir_to_brw_state &ntb, const fs_builder &bld, +try_emit_b2fi_of_inot(nir_to_brw_state &ntb, const brw_builder &bld, brw_reg result, nir_alu_instr *instr) { @@ -958,7 +958,7 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, } #endif - const fs_builder &bld = result.is_scalar ? ntb.bld.scalar_group() : ntb.bld; + const brw_builder &bld = result.is_scalar ? ntb.bld.scalar_group() : ntb.bld; switch (instr->op) { case nir_op_mov: @@ -1872,7 +1872,7 @@ fs_nir_emit_load_const(nir_to_brw_state &ntb, nir_load_const_instr *instr) { const intel_device_info *devinfo = ntb.devinfo; - const fs_builder &bld = ntb.bld.scalar_group(); + const brw_builder &bld = ntb.bld.scalar_group(); const brw_reg_type reg_type = brw_type_with_size(BRW_TYPE_D, instr->def.bit_size); @@ -2025,7 +2025,7 @@ get_nir_def(nir_to_brw_state &ntb, const nir_def &def, bool all_sources_uniform) is_scalar = store_reg == NULL && all_sources_uniform && !def.divergent; } - const fs_builder &bld = is_scalar ? ntb.bld.scalar_group() : ntb.bld; + const brw_builder &bld = is_scalar ? ntb.bld.scalar_group() : ntb.bld; if (!store_reg) { const brw_reg_type reg_type = @@ -2063,7 +2063,7 @@ get_nir_write_mask(const nir_def &def) } static fs_inst * -emit_pixel_interpolater_send(const fs_builder &bld, +emit_pixel_interpolater_send(const brw_builder &bld, enum opcode opcode, const brw_reg &dst, const brw_reg &src, @@ -2120,7 +2120,7 @@ emit_pixel_interpolater_send(const fs_builder &bld, * multiple polygons as a single brw_reg. */ static brw_reg -fetch_polygon_reg(const fs_builder &bld, unsigned reg, unsigned subreg) +fetch_polygon_reg(const brw_builder &bld, unsigned reg, unsigned subreg) { const fs_visitor *shader = bld.shader; assert(shader->stage == MESA_SHADER_FRAGMENT); @@ -2151,7 +2151,7 @@ fetch_polygon_reg(const fs_builder &bld, unsigned reg, unsigned subreg) * from the thread payload as far back as ICL. */ static void -emit_pixel_interpolater_alu_at_offset(const fs_builder &bld, +emit_pixel_interpolater_alu_at_offset(const brw_builder &bld, const brw_reg &dst, const brw_reg &offs, glsl_interp_mode interpolation) @@ -2188,7 +2188,7 @@ emit_pixel_interpolater_alu_at_offset(const fs_builder &bld, const unsigned poly_width = shader->dispatch_width / shader->max_polygons; for (unsigned i = 0; i < DIV_ROUND_UP(shader->max_polygons, 2); i++) { - const fs_builder ibld = bld.group(MIN2(bld.dispatch_width(), 2 * poly_width), i); + const brw_builder ibld = bld.group(MIN2(bld.dispatch_width(), 2 * poly_width), i); /* Fetch needed parameters from the thread payload. */ const unsigned bary_coef_reg = interpolation == INTERP_MODE_NOPERSPECTIVE ? @@ -2242,7 +2242,7 @@ emit_pixel_interpolater_alu_at_offset(const fs_builder &bld, const brw_reg bary2 = ibld.vgrf(BRW_TYPE_F); for (unsigned j = 0; j < DIV_ROUND_UP(ibld.dispatch_width(), acc_width); j++) { - const fs_builder jbld = ibld.group(MIN2(ibld.dispatch_width(), acc_width), j); + const brw_builder jbld = ibld.group(MIN2(ibld.dispatch_width(), acc_width), j); const brw_reg acc = suboffset(brw_acc_reg(16), jbld.group() % acc_width); if (interpolation != INTERP_MODE_NOPERSPECTIVE) { @@ -2287,7 +2287,7 @@ emit_pixel_interpolater_alu_at_offset(const fs_builder &bld, * information from the thread payload as far back as ICL. */ static void -emit_pixel_interpolater_alu_at_sample(const fs_builder &bld, +emit_pixel_interpolater_alu_at_sample(const brw_builder &bld, const brw_reg &dst, const brw_reg &idx, glsl_interp_mode interpolation) @@ -2295,7 +2295,7 @@ emit_pixel_interpolater_alu_at_sample(const fs_builder &bld, const fs_thread_payload &payload = bld.shader->fs_payload(); const struct brw_wm_prog_data *wm_prog_data = brw_wm_prog_data(bld.shader->prog_data); - const fs_builder ubld = bld.exec_all().group(16, 0); + const brw_builder ubld = bld.exec_all().group(16, 0); const brw_reg sample_offs_xy = ubld.vgrf(BRW_TYPE_UD); assert(wm_prog_data->uses_sample_offsets); @@ -2339,7 +2339,7 @@ emit_pixel_interpolater_alu_at_sample(const fs_builder &bld, * Computes 1 << x, given a D/UD register containing some value x. */ static brw_reg -intexp2(const fs_builder &bld, const brw_reg &x) +intexp2(const brw_builder &bld, const brw_reg &x) { assert(x.type == BRW_TYPE_UD || x.type == BRW_TYPE_D); @@ -2393,7 +2393,7 @@ emit_gs_end_primitive(nir_to_brw_state &ntb, const nir_src &vertex_count_nir_src * control_data_bits register to 0 when the first vertex is emitted. */ - const fs_builder abld = ntb.bld.annotate("end primitive"); + const brw_builder abld = ntb.bld.annotate("end primitive"); /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */ brw_reg prev_count = abld.ADD(vertex_count, brw_imm_ud(0xffffffffu)); @@ -2435,8 +2435,8 @@ fs_visitor::gs_urb_per_slot_dword_index(const brw_reg &vertex_count) * Similarly, if the control data header is <= 32 bits, there is only one * DWord, so we can skip channel masks. */ - const fs_builder bld = fs_builder(this).at_end(); - const fs_builder abld = bld.annotate("urb per slot offset"); + const brw_builder bld = brw_builder(this).at_end(); + const brw_builder abld = bld.annotate("urb per slot offset"); /* Figure out which DWord we're trying to write to using the formula: * @@ -2480,8 +2480,8 @@ fs_visitor::gs_urb_channel_mask(const brw_reg &dword_index) if (gs_compile->control_data_header_size_bits <= 32) return channel_mask; - const fs_builder bld = fs_builder(this).at_end(); - const fs_builder ubld = bld.exec_all(); + const brw_builder bld = brw_builder(this).at_end(); + const brw_builder ubld = bld.exec_all(); /* Set the channel masks to 1 << (dword_index % 4), so that we'll * write to the appropriate DWORD within the OWORD. @@ -2499,8 +2499,8 @@ fs_visitor::emit_gs_control_data_bits(const brw_reg &vertex_count) const struct brw_gs_prog_data *gs_prog_data = brw_gs_prog_data(prog_data); - const fs_builder bld = fs_builder(this).at_end(); - const fs_builder abld = bld.annotate("emit control data bits"); + const brw_builder bld = brw_builder(this).at_end(); + const brw_builder abld = bld.annotate("emit control data bits"); brw_reg dword_index = gs_urb_per_slot_dword_index(vertex_count); brw_reg channel_mask = gs_urb_channel_mask(dword_index); @@ -2575,7 +2575,7 @@ set_gs_stream_control_data_bits(nir_to_brw_state &ntb, const brw_reg &vertex_cou if (stream_id == 0) return; - const fs_builder abld = ntb.bld.annotate("set stream control data bits"); + const brw_builder abld = ntb.bld.annotate("set stream control data bits"); /* reg::sid = stream_id */ brw_reg sid = abld.MOV(brw_imm_ud(stream_id)); @@ -2626,7 +2626,7 @@ emit_gs_vertex(nir_to_brw_state &ntb, const nir_src &vertex_count_nir_src, * correct. */ if (s.gs_compile->control_data_header_size_bits > 32) { - const fs_builder abld = + const brw_builder abld = ntb.bld.annotate("emit vertex: emit control data bits"); /* Only emit control data bits if we've finished accumulating a batch @@ -2690,7 +2690,7 @@ emit_gs_vertex(nir_to_brw_state &ntb, const nir_src &vertex_count_nir_src, } static void -brw_combine_with_vec(const fs_builder &bld, const brw_reg &dst, +brw_combine_with_vec(const brw_builder &bld, const brw_reg &dst, const brw_reg &src, unsigned n) { assert(n <= NIR_MAX_VEC_COMPONENTS); @@ -2708,7 +2708,7 @@ emit_gs_input_load(nir_to_brw_state &ntb, const brw_reg &dst, unsigned num_components, unsigned first_component) { - const fs_builder &bld = ntb.bld; + const brw_builder &bld = ntb.bld; const struct intel_device_info *devinfo = ntb.devinfo; fs_visitor &s = ntb.s; @@ -2883,7 +2883,7 @@ static void fs_nir_emit_vs_intrinsic(nir_to_brw_state &ntb, nir_intrinsic_instr *instr) { - const fs_builder &bld = ntb.bld; + const brw_builder &bld = ntb.bld; fs_visitor &s = ntb.s; assert(s.stage == MESA_SHADER_VERTEX); @@ -2921,7 +2921,7 @@ fs_nir_emit_vs_intrinsic(nir_to_brw_state &ntb, } static brw_reg -get_tcs_single_patch_icp_handle(nir_to_brw_state &ntb, const fs_builder &bld, +get_tcs_single_patch_icp_handle(nir_to_brw_state &ntb, const brw_builder &bld, nir_intrinsic_instr *instr) { fs_visitor &s = ntb.s; @@ -2966,7 +2966,7 @@ get_tcs_single_patch_icp_handle(nir_to_brw_state &ntb, const fs_builder &bld, } static brw_reg -get_tcs_multi_patch_icp_handle(nir_to_brw_state &ntb, const fs_builder &bld, +get_tcs_multi_patch_icp_handle(nir_to_brw_state &ntb, const brw_builder &bld, nir_intrinsic_instr *instr) { fs_visitor &s = ntb.s; @@ -3018,10 +3018,10 @@ get_tcs_multi_patch_icp_handle(nir_to_brw_state &ntb, const fs_builder &bld, } static void -setup_barrier_message_payload_gfx125(const fs_builder &bld, +setup_barrier_message_payload_gfx125(const brw_builder &bld, const brw_reg &msg_payload) { - const fs_builder ubld = bld.exec_all().group(1, 0); + const brw_builder ubld = bld.exec_all().group(1, 0); const struct intel_device_info *devinfo = bld.shader->devinfo; assert(devinfo->verx10 >= 125); @@ -3043,9 +3043,9 @@ static void emit_barrier(nir_to_brw_state &ntb) { const intel_device_info *devinfo = ntb.devinfo; - const fs_builder &bld = ntb.bld; - const fs_builder ubld = bld.exec_all(); - const fs_builder hbld = ubld.group(8 * reg_unit(devinfo), 0); + const brw_builder &bld = ntb.bld; + const brw_builder ubld = bld.exec_all(); + const brw_builder hbld = ubld.group(8 * reg_unit(devinfo), 0); fs_visitor &s = ntb.s; /* We are getting the barrier ID from the compute shader header */ @@ -3077,7 +3077,7 @@ static void emit_tcs_barrier(nir_to_brw_state &ntb) { const intel_device_info *devinfo = ntb.devinfo; - const fs_builder &bld = ntb.bld; + const brw_builder &bld = ntb.bld; fs_visitor &s = ntb.s; assert(s.stage == MESA_SHADER_TESS_CTRL); @@ -3086,7 +3086,7 @@ emit_tcs_barrier(nir_to_brw_state &ntb) brw_reg m0 = bld.vgrf(BRW_TYPE_UD); brw_reg m0_2 = component(m0, 2); - const fs_builder chanbld = bld.exec_all().group(1, 0); + const brw_builder chanbld = bld.exec_all().group(1, 0); /* Zero the message header */ bld.exec_all().MOV(m0, brw_imm_ud(0u)); @@ -3121,7 +3121,7 @@ fs_nir_emit_tcs_intrinsic(nir_to_brw_state &ntb, nir_intrinsic_instr *instr) { const intel_device_info *devinfo = ntb.devinfo; - const fs_builder &bld = ntb.bld; + const brw_builder &bld = ntb.bld; fs_visitor &s = ntb.s; assert(s.stage == MESA_SHADER_TESS_CTRL); @@ -3344,7 +3344,7 @@ fs_nir_emit_tes_intrinsic(nir_to_brw_state &ntb, nir_intrinsic_instr *instr) { const intel_device_info *devinfo = ntb.devinfo; - const fs_builder &bld = ntb.bld; + const brw_builder &bld = ntb.bld; fs_visitor &s = ntb.s; assert(s.stage == MESA_SHADER_TESS_EVAL); @@ -3451,7 +3451,7 @@ static void fs_nir_emit_gs_intrinsic(nir_to_brw_state &ntb, nir_intrinsic_instr *instr) { - const fs_builder &bld = ntb.bld; + const brw_builder &bld = ntb.bld; fs_visitor &s = ntb.s; assert(s.stage == MESA_SHADER_GEOMETRY); @@ -3513,7 +3513,7 @@ fs_nir_emit_gs_intrinsic(nir_to_brw_state &ntb, * Fetch the current render target layer index. */ static brw_reg -fetch_render_target_array_index(const fs_builder &bld) +fetch_render_target_array_index(const brw_builder &bld) { const fs_visitor *v = bld.shader; @@ -3526,7 +3526,7 @@ fetch_render_target_array_index(const fs_builder &bld) const brw_reg idx = bld.vgrf(BRW_TYPE_UD); for (unsigned i = 0; i < DIV_ROUND_UP(bld.dispatch_width(), 16); i++) { - const fs_builder hbld = bld.group(16, i); + const brw_builder hbld = bld.group(16, i); const struct brw_reg reg = retype(brw_vec1_grf(2 * i + 1, 1), BRW_TYPE_UW); hbld.AND(offset(idx, hbld, i), stride(reg, 1, 8, 0), @@ -3545,7 +3545,7 @@ fetch_render_target_array_index(const fs_builder &bld) const brw_reg idx = bld.vgrf(BRW_TYPE_UD); for (unsigned i = 0; i < v->max_polygons; i++) { - const fs_builder hbld = bld.group(8, i); + const brw_builder hbld = bld.group(8, i); const struct brw_reg g1 = brw_uw1_reg(FIXED_GRF, 1, 3 + 10 * i); hbld.AND(offset(idx, hbld, i), g1, brw_imm_uw(0x7ff)); } @@ -3571,7 +3571,7 @@ fetch_render_target_array_index(const fs_builder &bld) } static brw_reg -fetch_viewport_index(const fs_builder &bld) +fetch_viewport_index(const brw_builder &bld) { const fs_visitor *v = bld.shader; @@ -3584,7 +3584,7 @@ fetch_viewport_index(const fs_builder &bld) const brw_reg idx = bld.vgrf(BRW_TYPE_UD); for (unsigned i = 0; i < DIV_ROUND_UP(bld.dispatch_width(), 16); i++) { - const fs_builder hbld = bld.group(16, i); + const brw_builder hbld = bld.group(16, i); const struct brw_reg reg = retype(xe2_vec1_grf(i, 9), BRW_TYPE_UW); hbld.AND(offset(idx, hbld, i), stride(reg, 1, 8, 0), @@ -3608,7 +3608,7 @@ fetch_viewport_index(const fs_builder &bld) }; for (unsigned i = 0; i < v->max_polygons; i++) { - const fs_builder hbld = bld.group(8, i); + const brw_builder hbld = bld.group(8, i); hbld.SHR(offset(idx, hbld, i), vp_idx_per_poly_dw[i], brw_imm_ud(27)); } @@ -3642,7 +3642,7 @@ emit_mcs_fetch(nir_to_brw_state &ntb, const brw_reg &coordinate, unsigned compon const brw_reg &texture, const brw_reg &texture_handle) { - const fs_builder &bld = ntb.bld; + const brw_builder &bld = ntb.bld; const brw_reg dest = bld.vgrf(BRW_TYPE_UD, 4); @@ -3671,7 +3671,7 @@ emit_mcs_fetch(nir_to_brw_state &ntb, const brw_reg &coordinate, unsigned compon * framebuffer at the current fragment coordinates and sample index. */ static fs_inst * -emit_non_coherent_fb_read(nir_to_brw_state &ntb, const fs_builder &bld, const brw_reg &dst, +emit_non_coherent_fb_read(nir_to_brw_state &ntb, const brw_builder &bld, const brw_reg &dst, unsigned target) { fs_visitor &s = ntb.s; @@ -3747,7 +3747,7 @@ emit_non_coherent_fb_read(nir_to_brw_state &ntb, const fs_builder &bld, const br * read message. Requires SKL+. */ static fs_inst * -emit_coherent_fb_read(const fs_builder &bld, const brw_reg &dst, unsigned target) +emit_coherent_fb_read(const brw_builder &bld, const brw_reg &dst, unsigned target) { fs_inst *inst = bld.emit(FS_OPCODE_FB_READ_LOGICAL, dst); inst->target = target; @@ -3757,7 +3757,7 @@ emit_coherent_fb_read(const fs_builder &bld, const brw_reg &dst, unsigned target } static brw_reg -alloc_temporary(const fs_builder &bld, unsigned size, brw_reg *regs, unsigned n) +alloc_temporary(const brw_builder &bld, unsigned size, brw_reg *regs, unsigned n) { if (n && regs[0].file != BAD_FILE) { return regs[0]; @@ -3811,7 +3811,7 @@ alloc_frag_output(nir_to_brw_state &ntb, unsigned location) static void emit_is_helper_invocation(nir_to_brw_state &ntb, brw_reg result) { - const fs_builder &bld = ntb.bld; + const brw_builder &bld = ntb.bld; /* Unlike the regular gl_HelperInvocation, that is defined at dispatch, * the helperInvocationEXT() (aka SpvOpIsHelperInvocationEXT) takes into @@ -3824,7 +3824,7 @@ emit_is_helper_invocation(nir_to_brw_state &ntb, brw_reg result) /* See brw_sample_mask_reg() for why we split SIMD32 into SIMD16 here. */ unsigned width = bld.dispatch_width(); for (unsigned i = 0; i < DIV_ROUND_UP(width, 16); i++) { - const fs_builder b = bld.group(MIN2(width, 16), i); + const brw_builder b = bld.group(MIN2(width, 16), i); fs_inst *mov = b.MOV(offset(result, b, i), brw_imm_ud(~0)); @@ -3841,7 +3841,7 @@ static brw_reg emit_frontfacing_interpolation(nir_to_brw_state &ntb) { const intel_device_info *devinfo = ntb.devinfo; - const fs_builder &bld = ntb.bld; + const brw_builder &bld = ntb.bld; fs_visitor &s = ntb.s; brw_reg ff = bld.vgrf(BRW_TYPE_D); @@ -3855,7 +3855,7 @@ emit_frontfacing_interpolation(nir_to_brw_state &ntb) const brw_reg tmp = bld.vgrf(BRW_TYPE_UW); for (unsigned i = 0; i < DIV_ROUND_UP(s.dispatch_width, 16); i++) { - const fs_builder hbld = bld.group(16, i); + const brw_builder hbld = bld.group(16, i); const struct brw_reg gi_uw = retype(xe2_vec1_grf(i, 9), BRW_TYPE_UW); hbld.AND(offset(tmp, hbld, i), gi_uw, brw_imm_uw(0x800)); @@ -3874,7 +3874,7 @@ emit_frontfacing_interpolation(nir_to_brw_state &ntb) brw_reg tmp = bld.vgrf(BRW_TYPE_W); for (unsigned i = 0; i < s.max_polygons; i++) { - const fs_builder hbld = bld.group(8, i); + const brw_builder hbld = bld.group(8, i); const struct brw_reg g1 = retype(brw_vec1_grf(1, 1 + 5 * i), BRW_TYPE_W); hbld.ASR(offset(tmp, hbld, i), g1, brw_imm_d(15)); @@ -3911,13 +3911,13 @@ emit_frontfacing_interpolation(nir_to_brw_state &ntb) static brw_reg emit_samplepos_setup(nir_to_brw_state &ntb) { - const fs_builder &bld = ntb.bld; + const brw_builder &bld = ntb.bld; fs_visitor &s = ntb.s; assert(s.stage == MESA_SHADER_FRAGMENT); struct brw_wm_prog_data *wm_prog_data = brw_wm_prog_data(s.prog_data); - const fs_builder abld = bld.annotate("compute sample position"); + const brw_builder abld = bld.annotate("compute sample position"); brw_reg pos = abld.vgrf(BRW_TYPE_F, 2); if (wm_prog_data->persample_dispatch == INTEL_NEVER) { @@ -3972,14 +3972,14 @@ static brw_reg emit_sampleid_setup(nir_to_brw_state &ntb) { const intel_device_info *devinfo = ntb.devinfo; - const fs_builder &bld = ntb.bld; + const brw_builder &bld = ntb.bld; fs_visitor &s = ntb.s; assert(s.stage == MESA_SHADER_FRAGMENT); ASSERTED brw_wm_prog_key *key = (brw_wm_prog_key*) s.key; struct brw_wm_prog_data *wm_prog_data = brw_wm_prog_data(s.prog_data); - const fs_builder abld = bld.annotate("compute sample id"); + const brw_builder abld = bld.annotate("compute sample id"); brw_reg sample_id = abld.vgrf(BRW_TYPE_UD); assert(key->multisample_fbo != INTEL_NEVER); @@ -4015,7 +4015,7 @@ emit_sampleid_setup(nir_to_brw_state &ntb) const brw_reg tmp = abld.vgrf(BRW_TYPE_UW); for (unsigned i = 0; i < DIV_ROUND_UP(s.dispatch_width, 16); i++) { - const fs_builder hbld = abld.group(MIN2(16, s.dispatch_width), i); + const brw_builder hbld = abld.group(MIN2(16, s.dispatch_width), i); /* According to the "PS Thread Payload for Normal Dispatch" * pages on the BSpec, the sample ids are stored in R0.8/R1.8 * on gfx20+ and in R1.0/R2.0 on gfx8+. @@ -4042,7 +4042,7 @@ emit_sampleid_setup(nir_to_brw_state &ntb) static brw_reg emit_samplemaskin_setup(nir_to_brw_state &ntb) { - const fs_builder &bld = ntb.bld; + const brw_builder &bld = ntb.bld; fs_visitor &s = ntb.s; assert(s.stage == MESA_SHADER_FRAGMENT); @@ -4067,7 +4067,7 @@ emit_samplemaskin_setup(nir_to_brw_state &ntb) * gl_SamplePosition variables, only the bit for the current sample is * set in gl_SampleMaskIn." */ - const fs_builder abld = bld.annotate("compute gl_SampleMaskIn"); + const brw_builder abld = bld.annotate("compute gl_SampleMaskIn"); if (ntb.system_values[SYSTEM_VALUE_SAMPLE_ID].file == BAD_FILE) ntb.system_values[SYSTEM_VALUE_SAMPLE_ID] = emit_sampleid_setup(ntb); @@ -4090,7 +4090,7 @@ static brw_reg emit_shading_rate_setup(nir_to_brw_state &ntb) { const intel_device_info *devinfo = ntb.devinfo; - const fs_builder &bld = ntb.bld; + const brw_builder &bld = ntb.bld; assert(devinfo->ver >= 11); @@ -4103,7 +4103,7 @@ emit_shading_rate_setup(nir_to_brw_state &ntb) if (wm_prog_data->coarse_pixel_dispatch == INTEL_NEVER) return brw_imm_ud(0); - const fs_builder abld = bld.annotate("compute fragment shading rate"); + const brw_builder abld = bld.annotate("compute fragment shading rate"); /* The shading rates provided in the shader are the actual 2D shading * rate while the SPIR-V built-in is the enum value that has the shading @@ -4141,7 +4141,7 @@ emit_shading_rate_setup(nir_to_brw_state &ntb) * generate_code() time. */ static brw_reg -brw_interp_reg(const fs_builder &bld, unsigned location, +brw_interp_reg(const brw_builder &bld, unsigned location, unsigned channel, unsigned comp) { fs_visitor &s = *bld.shader; @@ -4181,7 +4181,7 @@ brw_interp_reg(const fs_builder &bld, unsigned location, * generate_code() time. */ static brw_reg -brw_per_primitive_reg(const fs_builder &bld, int location, unsigned comp) +brw_per_primitive_reg(const brw_builder &bld, int location, unsigned comp) { fs_visitor &s = *bld.shader; assert(s.stage == MESA_SHADER_FRAGMENT); @@ -4217,7 +4217,7 @@ fs_nir_emit_fs_intrinsic(nir_to_brw_state &ntb, nir_intrinsic_instr *instr) { const intel_device_info *devinfo = ntb.devinfo; - const fs_builder &bld = ntb.bld; + const brw_builder &bld = ntb.bld; fs_visitor &s = ntb.s; assert(s.stage == MESA_SHADER_FRAGMENT); @@ -4601,7 +4601,7 @@ fs_nir_emit_cs_intrinsic(nir_to_brw_state &ntb, nir_intrinsic_instr *instr) { const intel_device_info *devinfo = ntb.devinfo; - const fs_builder &bld = ntb.bld; + const brw_builder &bld = ntb.bld; fs_visitor &s = ntb.s; assert(gl_shader_stage_uses_workgroup(s.stage)); @@ -4611,7 +4611,7 @@ fs_nir_emit_cs_intrinsic(nir_to_brw_state &ntb, if (nir_intrinsic_infos[instr->intrinsic].has_dest) dest = get_nir_def(ntb, instr->def); - const fs_builder xbld = dest.is_scalar ? bld.scalar_group() : bld; + const brw_builder xbld = dest.is_scalar ? bld.scalar_group() : bld; switch (instr->intrinsic) { case nir_intrinsic_barrier: @@ -4663,7 +4663,7 @@ fs_nir_emit_cs_intrinsic(nir_to_brw_state &ntb, case nir_intrinsic_load_workgroup_id: { brw_reg val = ntb.system_values[SYSTEM_VALUE_WORKGROUP_ID]; - const fs_builder ubld = bld.scalar_group(); + const brw_builder ubld = bld.scalar_group(); assert(val.file != BAD_FILE); assert(val.is_scalar); @@ -4718,8 +4718,8 @@ fs_nir_emit_cs_intrinsic(nir_to_brw_state &ntb, dest = retype(dest, dest_type); brw_reg src0 = retype(get_nir_src(ntb, instr->src[0]), dest_type); - fs_builder bld16 = bld.exec_all().group(16, 0); - fs_builder bldn = devinfo->ver >= 20 ? bld16 : bld.exec_all().group(8, 0); + brw_builder bld16 = bld.exec_all().group(16, 0); + brw_builder bldn = devinfo->ver >= 20 ? bld16 : bld.exec_all().group(8, 0); bldn.DPAS(dest, src0, @@ -4740,13 +4740,13 @@ fs_nir_emit_cs_intrinsic(nir_to_brw_state &ntb, } static void -emit_rt_lsc_fence(const fs_builder &bld, +emit_rt_lsc_fence(const brw_builder &bld, enum lsc_fence_scope scope, enum lsc_flush_type flush_type) { const intel_device_info *devinfo = bld.shader->devinfo; - const fs_builder ubld = bld.exec_all().group(8, 0); + const brw_builder ubld = bld.exec_all().group(8, 0); brw_reg tmp = ubld.vgrf(BRW_TYPE_UD); fs_inst *send = ubld.emit(SHADER_OPCODE_SEND, tmp, brw_imm_ud(0) /* desc */, @@ -4768,7 +4768,7 @@ static void fs_nir_emit_bs_intrinsic(nir_to_brw_state &ntb, nir_intrinsic_instr *instr) { - const fs_builder &bld = ntb.bld; + const brw_builder &bld = ntb.bld; fs_visitor &s = ntb.s; assert(brw_shader_stage_is_bindless(s.stage)); @@ -4778,7 +4778,7 @@ fs_nir_emit_bs_intrinsic(nir_to_brw_state &ntb, if (nir_intrinsic_infos[instr->intrinsic].has_dest) dest = get_nir_def(ntb, instr->def); - const fs_builder xbld = dest.is_scalar ? bld.scalar_group() : bld; + const brw_builder xbld = dest.is_scalar ? bld.scalar_group() : bld; switch (instr->intrinsic) { case nir_intrinsic_load_btd_global_arg_addr_intel: @@ -4822,7 +4822,7 @@ brw_reduce_op_for_nir_reduction_op(nir_op op) } static brw_reg -get_nir_image_intrinsic_image(nir_to_brw_state &ntb, const brw::fs_builder &bld, +get_nir_image_intrinsic_image(nir_to_brw_state &ntb, const brw::brw_builder &bld, nir_intrinsic_instr *instr) { brw_reg surf_index = get_nir_src_imm(ntb, instr->src[0]); @@ -4833,7 +4833,7 @@ get_nir_image_intrinsic_image(nir_to_brw_state &ntb, const brw::fs_builder &bld, } static brw_reg -get_nir_buffer_intrinsic_index(nir_to_brw_state &ntb, const brw::fs_builder &bld, +get_nir_buffer_intrinsic_index(nir_to_brw_state &ntb, const brw::brw_builder &bld, nir_intrinsic_instr *instr, bool *no_mask_handle = NULL) { /* SSBO stores are weird in that their index is in src[1] */ @@ -4878,7 +4878,7 @@ get_nir_buffer_intrinsic_index(nir_to_brw_state &ntb, const brw::fs_builder &bld */ static brw_reg swizzle_nir_scratch_addr(nir_to_brw_state &ntb, - const brw::fs_builder &bld, + const brw::brw_builder &bld, const nir_src &nir_addr_src, bool in_dwords) { @@ -4941,9 +4941,9 @@ choose_block_size_dwords(const intel_device_info *devinfo, unsigned dwords) } static brw_reg -increment_a64_address(const fs_builder &_bld, brw_reg address, uint32_t v, bool use_no_mask) +increment_a64_address(const brw_builder &_bld, brw_reg address, uint32_t v, bool use_no_mask) { - const fs_builder bld = use_no_mask ? _bld.exec_all().group(8, 0) : _bld; + const brw_builder bld = use_no_mask ? _bld.exec_all().group(8, 0) : _bld; if (bld.shader->devinfo->has_64bit_int) { struct brw_reg imm = brw_imm_reg(address.type); @@ -4964,7 +4964,7 @@ increment_a64_address(const fs_builder &_bld, brw_reg address, uint32_t v, bool } static brw_reg -emit_fence(const fs_builder &bld, enum opcode opcode, +emit_fence(const brw_builder &bld, enum opcode opcode, uint8_t sfid, uint32_t desc, bool commit_enable, uint8_t bti) { @@ -5018,7 +5018,7 @@ lsc_fence_descriptor_for_intrinsic(const struct intel_device_info *devinfo, * Create a MOV to read the timestamp register. */ static brw_reg -get_timestamp(const fs_builder &bld) +get_timestamp(const brw_builder &bld) { fs_visitor &s = *bld.shader; @@ -5045,7 +5045,7 @@ component_from_intrinsic(nir_intrinsic_instr *instr) } static void -adjust_handle_and_offset(const fs_builder &bld, +adjust_handle_and_offset(const brw_builder &bld, brw_reg &urb_handle, unsigned &urb_global_offset) { @@ -5055,7 +5055,7 @@ adjust_handle_and_offset(const fs_builder &bld, unsigned adjustment = (urb_global_offset >> 11) << 11; if (adjustment) { - fs_builder ubld8 = bld.group(8, 0).exec_all(); + brw_builder ubld8 = bld.group(8, 0).exec_all(); /* Allocate new register to not overwrite the shared URB handle. */ urb_handle = ubld8.ADD(urb_handle, brw_imm_ud(adjustment)); urb_global_offset -= adjustment; @@ -5063,7 +5063,7 @@ adjust_handle_and_offset(const fs_builder &bld, } static void -emit_urb_direct_vec4_write(const fs_builder &bld, +emit_urb_direct_vec4_write(const brw_builder &bld, unsigned urb_global_offset, const brw_reg &src, brw_reg urb_handle, @@ -5072,7 +5072,7 @@ emit_urb_direct_vec4_write(const fs_builder &bld, unsigned mask) { for (unsigned q = 0; q < bld.dispatch_width() / 8; q++) { - fs_builder bld8 = bld.group(8, q); + brw_builder bld8 = bld.group(8, q); brw_reg payload_srcs[8]; unsigned length = 0; @@ -5099,7 +5099,7 @@ emit_urb_direct_vec4_write(const fs_builder &bld, } static void -emit_urb_direct_writes(const fs_builder &bld, nir_intrinsic_instr *instr, +emit_urb_direct_writes(const brw_builder &bld, nir_intrinsic_instr *instr, const brw_reg &src, brw_reg urb_handle) { assert(nir_src_bit_size(instr->src[0]) == 32); @@ -5128,7 +5128,7 @@ emit_urb_direct_writes(const fs_builder &bld, nir_intrinsic_instr *instr, } static void -emit_urb_direct_vec4_write_xe2(const fs_builder &bld, +emit_urb_direct_vec4_write_xe2(const brw_builder &bld, unsigned offset_in_bytes, const brw_reg &src, brw_reg urb_handle, @@ -5140,12 +5140,12 @@ emit_urb_direct_vec4_write_xe2(const fs_builder &bld, const unsigned write_size = 8 * runit; if (offset_in_bytes > 0) { - fs_builder bldall = bld.group(write_size, 0).exec_all(); + brw_builder bldall = bld.group(write_size, 0).exec_all(); urb_handle = bldall.ADD(urb_handle, brw_imm_ud(offset_in_bytes)); } for (unsigned q = 0; q < bld.dispatch_width() / write_size; q++) { - fs_builder hbld = bld.group(write_size, q); + brw_builder hbld = bld.group(write_size, q); assert(comps <= 4); brw_reg payload_srcs[4]; @@ -5167,7 +5167,7 @@ emit_urb_direct_vec4_write_xe2(const fs_builder &bld, } static void -emit_urb_direct_writes_xe2(const fs_builder &bld, nir_intrinsic_instr *instr, +emit_urb_direct_writes_xe2(const brw_builder &bld, nir_intrinsic_instr *instr, const brw_reg &src, brw_reg urb_handle) { assert(nir_src_bit_size(instr->src[0]) == 32); @@ -5189,7 +5189,7 @@ emit_urb_direct_writes_xe2(const fs_builder &bld, nir_intrinsic_instr *instr, } static void -emit_urb_indirect_vec4_write(const fs_builder &bld, +emit_urb_indirect_vec4_write(const brw_builder &bld, const brw_reg &offset_src, unsigned base, const brw_reg &src, @@ -5199,7 +5199,7 @@ emit_urb_indirect_vec4_write(const fs_builder &bld, unsigned mask) { for (unsigned q = 0; q < bld.dispatch_width() / 8; q++) { - fs_builder bld8 = bld.group(8, q); + brw_builder bld8 = bld.group(8, q); /* offset is always positive, so signedness doesn't matter */ assert(offset_src.type == BRW_TYPE_D || offset_src.type == BRW_TYPE_UD); @@ -5231,7 +5231,7 @@ emit_urb_indirect_vec4_write(const fs_builder &bld, } static void -emit_urb_indirect_writes_mod(const fs_builder &bld, nir_intrinsic_instr *instr, +emit_urb_indirect_writes_mod(const brw_builder &bld, nir_intrinsic_instr *instr, const brw_reg &src, const brw_reg &offset_src, brw_reg urb_handle, unsigned mod) { @@ -5251,7 +5251,7 @@ emit_urb_indirect_writes_mod(const fs_builder &bld, nir_intrinsic_instr *instr, } static void -emit_urb_indirect_writes_xe2(const fs_builder &bld, nir_intrinsic_instr *instr, +emit_urb_indirect_writes_xe2(const brw_builder &bld, nir_intrinsic_instr *instr, const brw_reg &src, const brw_reg &offset_src, brw_reg urb_handle) { @@ -5268,14 +5268,14 @@ emit_urb_indirect_writes_xe2(const fs_builder &bld, nir_intrinsic_instr *instr, component_from_intrinsic(instr); if (base_in_dwords > 0) { - fs_builder bldall = bld.group(write_size, 0).exec_all(); + brw_builder bldall = bld.group(write_size, 0).exec_all(); urb_handle = bldall.ADD(urb_handle, brw_imm_ud(base_in_dwords * 4)); } const unsigned mask = nir_intrinsic_write_mask(instr); for (unsigned q = 0; q < bld.dispatch_width() / write_size; q++) { - fs_builder wbld = bld.group(write_size, q); + brw_builder wbld = bld.group(write_size, q); brw_reg payload_srcs[4]; @@ -5301,7 +5301,7 @@ emit_urb_indirect_writes_xe2(const fs_builder &bld, nir_intrinsic_instr *instr, } static void -emit_urb_indirect_writes(const fs_builder &bld, nir_intrinsic_instr *instr, +emit_urb_indirect_writes(const brw_builder &bld, nir_intrinsic_instr *instr, const brw_reg &src, const brw_reg &offset_src, brw_reg urb_handle) { @@ -5326,7 +5326,7 @@ emit_urb_indirect_writes(const fs_builder &bld, nir_intrinsic_instr *instr, brw_reg src_comp = offset(src, bld, c); for (unsigned q = 0; q < bld.dispatch_width() / 8; q++) { - fs_builder bld8 = bld.group(8, q); + brw_builder bld8 = bld.group(8, q); /* offset is always positive, so signedness doesn't matter */ assert(offset_src.type == BRW_TYPE_D || @@ -5363,7 +5363,7 @@ emit_urb_indirect_writes(const fs_builder &bld, nir_intrinsic_instr *instr, } static void -emit_urb_direct_reads(const fs_builder &bld, nir_intrinsic_instr *instr, +emit_urb_direct_reads(const brw_builder &bld, nir_intrinsic_instr *instr, const brw_reg &dest, brw_reg urb_handle) { assert(instr->def.bit_size == 32); @@ -5385,7 +5385,7 @@ emit_urb_direct_reads(const fs_builder &bld, nir_intrinsic_instr *instr, const unsigned comp_offset = offset_in_dwords % 4; const unsigned num_regs = comp_offset + comps; - fs_builder ubld8 = bld.group(8, 0).exec_all(); + brw_builder ubld8 = bld.group(8, 0).exec_all(); brw_reg data = ubld8.vgrf(BRW_TYPE_UD, num_regs); brw_reg srcs[URB_LOGICAL_NUM_SRCS]; srcs[URB_LOGICAL_SRC_HANDLE] = urb_handle; @@ -5404,7 +5404,7 @@ emit_urb_direct_reads(const fs_builder &bld, nir_intrinsic_instr *instr, } static void -emit_urb_direct_reads_xe2(const fs_builder &bld, nir_intrinsic_instr *instr, +emit_urb_direct_reads_xe2(const brw_builder &bld, nir_intrinsic_instr *instr, const brw_reg &dest, brw_reg urb_handle) { assert(instr->def.bit_size == 32); @@ -5416,7 +5416,7 @@ emit_urb_direct_reads_xe2(const fs_builder &bld, nir_intrinsic_instr *instr, nir_src *offset_nir_src = nir_get_io_offset_src(instr); assert(nir_src_is_const(*offset_nir_src)); - fs_builder ubld16 = bld.group(16, 0).exec_all(); + brw_builder ubld16 = bld.group(16, 0).exec_all(); const unsigned offset_in_dwords = nir_intrinsic_base(instr) + nir_src_as_uint(*offset_nir_src) + @@ -5441,7 +5441,7 @@ emit_urb_direct_reads_xe2(const fs_builder &bld, nir_intrinsic_instr *instr, } static void -emit_urb_indirect_reads(const fs_builder &bld, nir_intrinsic_instr *instr, +emit_urb_indirect_reads(const brw_builder &bld, nir_intrinsic_instr *instr, const brw_reg &dest, const brw_reg &offset_src, brw_reg urb_handle) { assert(instr->def.bit_size == 32); @@ -5452,7 +5452,7 @@ emit_urb_indirect_reads(const fs_builder &bld, nir_intrinsic_instr *instr, brw_reg seq_ud; { - fs_builder ubld8 = bld.group(8, 0).exec_all(); + brw_builder ubld8 = bld.group(8, 0).exec_all(); seq_ud = ubld8.vgrf(BRW_TYPE_UD, 1); brw_reg seq_uw = ubld8.vgrf(BRW_TYPE_UW, 1); ubld8.MOV(seq_uw, brw_reg(brw_imm_v(0x76543210))); @@ -5465,7 +5465,7 @@ emit_urb_indirect_reads(const fs_builder &bld, nir_intrinsic_instr *instr, for (unsigned c = 0; c < comps; c++) { for (unsigned q = 0; q < bld.dispatch_width() / 8; q++) { - fs_builder bld8 = bld.group(8, q); + brw_builder bld8 = bld.group(8, q); /* offset is always positive, so signedness doesn't matter */ assert(offset_src.type == BRW_TYPE_D || @@ -5505,7 +5505,7 @@ emit_urb_indirect_reads(const fs_builder &bld, nir_intrinsic_instr *instr, } static void -emit_urb_indirect_reads_xe2(const fs_builder &bld, nir_intrinsic_instr *instr, +emit_urb_indirect_reads_xe2(const brw_builder &bld, nir_intrinsic_instr *instr, const brw_reg &dest, const brw_reg &offset_src, brw_reg urb_handle) { @@ -5515,7 +5515,7 @@ emit_urb_indirect_reads_xe2(const fs_builder &bld, nir_intrinsic_instr *instr, if (comps == 0) return; - fs_builder ubld16 = bld.group(16, 0).exec_all(); + brw_builder ubld16 = bld.group(16, 0).exec_all(); const unsigned offset_in_dwords = nir_intrinsic_base(instr) + component_from_intrinsic(instr); @@ -5526,7 +5526,7 @@ emit_urb_indirect_reads_xe2(const fs_builder &bld, nir_intrinsic_instr *instr, brw_reg data = ubld16.vgrf(BRW_TYPE_UD, comps); for (unsigned q = 0; q < bld.dispatch_width() / 16; q++) { - fs_builder wbld = bld.group(16, q); + brw_builder wbld = bld.group(16, q); brw_reg addr = wbld.SHL(retype(horiz_offset(offset_src, 16 * q), BRW_TYPE_UD), @@ -5549,7 +5549,7 @@ emit_urb_indirect_reads_xe2(const fs_builder &bld, nir_intrinsic_instr *instr, static void emit_task_mesh_store(nir_to_brw_state &ntb, - const fs_builder &bld, nir_intrinsic_instr *instr, + const brw_builder &bld, nir_intrinsic_instr *instr, const brw_reg &urb_handle) { brw_reg src = get_nir_src(ntb, instr->src[0], -1); @@ -5587,7 +5587,7 @@ emit_task_mesh_store(nir_to_brw_state &ntb, static void emit_task_mesh_load(nir_to_brw_state &ntb, - const fs_builder &bld, nir_intrinsic_instr *instr, + const brw_builder &bld, nir_intrinsic_instr *instr, const brw_reg &urb_handle) { brw_reg dest = get_nir_def(ntb, instr->def); @@ -5612,7 +5612,7 @@ emit_task_mesh_load(nir_to_brw_state &ntb, } static void -fs_nir_emit_task_mesh_intrinsic(nir_to_brw_state &ntb, const fs_builder &bld, +fs_nir_emit_task_mesh_intrinsic(nir_to_brw_state &ntb, const brw_builder &bld, nir_intrinsic_instr *instr) { fs_visitor &s = ntb.s; @@ -5661,7 +5661,7 @@ static void fs_nir_emit_task_intrinsic(nir_to_brw_state &ntb, nir_intrinsic_instr *instr) { - const fs_builder &bld = ntb.bld; + const brw_builder &bld = ntb.bld; fs_visitor &s = ntb.s; assert(s.stage == MESA_SHADER_TASK); @@ -5688,7 +5688,7 @@ static void fs_nir_emit_mesh_intrinsic(nir_to_brw_state &ntb, nir_intrinsic_instr *instr) { - const fs_builder &bld = ntb.bld; + const brw_builder &bld = ntb.bld; fs_visitor &s = ntb.s; assert(s.stage == MESA_SHADER_MESH); @@ -5719,7 +5719,7 @@ fs_nir_emit_mesh_intrinsic(nir_to_brw_state &ntb, static void fs_nir_emit_intrinsic(nir_to_brw_state &ntb, - const fs_builder &bld, nir_intrinsic_instr *instr) + const brw_builder &bld, nir_intrinsic_instr *instr) { const intel_device_info *devinfo = ntb.devinfo; fs_visitor &s = ntb.s; @@ -5743,7 +5743,7 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, if (nir_intrinsic_infos[instr->intrinsic].has_dest) dest = get_nir_def(ntb, instr->def); - const fs_builder xbld = dest.is_scalar ? bld.scalar_group() : bld; + const brw_builder xbld = dest.is_scalar ? bld.scalar_group() : bld; switch (instr->intrinsic) { case nir_intrinsic_resource_intel: { @@ -5834,7 +5834,7 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, /* Since the image size is always uniform, we can just emit a SIMD8 * query instruction and splat the result out. */ - const fs_builder ubld = bld.scalar_group(); + const brw_builder ubld = bld.scalar_group(); brw_reg tmp = ubld.vgrf(BRW_TYPE_UD, 4); fs_inst *inst = ubld.emit(SHADER_OPCODE_IMAGE_SIZE_LOGICAL, @@ -5937,7 +5937,7 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, unsigned fence_regs_count = 0; brw_reg fence_regs[4] = {}; - const fs_builder ubld = bld.group(8, 0); + const brw_builder ubld = bld.group(8, 0); /* A memory barrier with acquire semantics requires us to * guarantee that memory operations of the specified storage @@ -6269,7 +6269,7 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, } const unsigned block_sz = 64; /* Fetch one cacheline at a time. */ - const fs_builder ubld = bld.exec_all().group(block_sz / 4, 0); + const brw_builder ubld = bld.exec_all().group(block_sz / 4, 0); for (unsigned c = 0; c < num_components;) { const unsigned base = load_offset + c * type_size; @@ -6329,7 +6329,7 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of * the dispatch width. */ - const fs_builder ubld = bld.scalar_group(); + const brw_builder ubld = bld.scalar_group(); brw_reg ret_payload = ubld.vgrf(BRW_TYPE_UD, 4); /* Set LOD = 0 */ @@ -6860,8 +6860,8 @@ lsc_bits_to_data_size(unsigned bit_size) */ static void fs_nir_emit_memory_access(nir_to_brw_state &ntb, - const fs_builder &bld, - const fs_builder &xbld, + const brw_builder &bld, + const brw_builder &xbld, nir_intrinsic_instr *instr) { const intel_device_info *devinfo = ntb.devinfo; @@ -6949,7 +6949,7 @@ fs_nir_emit_memory_access(nir_to_brw_state &ntb, srcs[MEMORY_LOGICAL_BINDING_TYPE] = brw_imm_ud(LSC_ADDR_SURFTYPE_FLAT); const brw_reg nir_src = get_nir_src(ntb, instr->src[is_store ? 1 : 0]); - const fs_builder ubld = nir_src.is_scalar ? bld.scalar_group() : bld; + const brw_builder ubld = nir_src.is_scalar ? bld.scalar_group() : bld; /* If the logical address is not uniform, a call to emit_uniformize * below will fix it up. @@ -6980,7 +6980,7 @@ fs_nir_emit_memory_access(nir_to_brw_state &ntb, if (devinfo->verx10 >= 125) { srcs[MEMORY_LOGICAL_BINDING_TYPE] = brw_imm_ud(LSC_ADDR_SURFTYPE_SS); - const fs_builder ubld = bld.exec_all().group(8 * reg_unit(devinfo), 0); + const brw_builder ubld = bld.exec_all().group(8 * reg_unit(devinfo), 0); brw_reg bind = ubld.AND(retype(brw_vec1_grf(0, 5), BRW_TYPE_UD), brw_imm_ud(INTEL_MASK(31, 10))); if (devinfo->ver >= 20) @@ -7118,7 +7118,7 @@ fs_nir_emit_memory_access(nir_to_brw_state &ntb, srcs[MEMORY_LOGICAL_ADDRESS] = bld.emit_uniformize(srcs[MEMORY_LOGICAL_ADDRESS]); - const fs_builder ubld = bld.exec_all().group(1, 0); + const brw_builder ubld = bld.exec_all().group(1, 0); unsigned total, done; unsigned first_read_component = 0; @@ -7195,7 +7195,7 @@ fs_nir_emit_texture(nir_to_brw_state &ntb, nir_tex_instr *instr) { const intel_device_info *devinfo = ntb.devinfo; - const fs_builder &bld = ntb.bld; + const brw_builder &bld = ntb.bld; brw_reg srcs[TEX_LOGICAL_NUM_SRCS]; @@ -7669,7 +7669,7 @@ fs_nir_emit_jump(nir_to_brw_state &ntb, nir_jump_instr *instr) * - first_component parameter allows skipping source components. */ void -shuffle_src_to_dst(const fs_builder &bld, +shuffle_src_to_dst(const brw_builder &bld, const brw_reg &dst, const brw_reg &src, uint32_t first_component, @@ -7725,7 +7725,7 @@ shuffle_src_to_dst(const fs_builder &bld, } void -shuffle_from_32bit_read(const fs_builder &bld, +shuffle_from_32bit_read(const brw_builder &bld, const brw_reg &dst, const brw_reg &src, uint32_t first_component, @@ -7878,15 +7878,15 @@ brw_rnd_mode_from_nir(unsigned mode, unsigned *mask) static void emit_shader_float_controls_execution_mode(nir_to_brw_state &ntb) { - const fs_builder &bld = ntb.bld; + const brw_builder &bld = ntb.bld; fs_visitor &s = ntb.s; unsigned execution_mode = s.nir->info.float_controls_execution_mode; if (execution_mode == FLOAT_CONTROLS_DEFAULT_FLOAT_CONTROL_MODE) return; - fs_builder ubld = bld.exec_all().group(1, 0); - fs_builder abld = ubld.annotate("shader floats control execution mode"); + brw_builder ubld = bld.exec_all().group(1, 0); + brw_builder abld = ubld.annotate("shader floats control execution mode"); unsigned mask, mode = brw_rnd_mode_from_nir(execution_mode, &mask); if (mask == 0) @@ -7903,7 +7903,7 @@ emit_shader_float_controls_execution_mode(nir_to_brw_state &ntb) * executed with an unexpected dispatch mask. */ static UNUSED void -brw_fs_test_dispatch_packing(const fs_builder &bld) +brw_fs_test_dispatch_packing(const brw_builder &bld) { const fs_visitor *shader = bld.shader; const gl_shader_stage stage = shader->stage; @@ -7914,7 +7914,7 @@ brw_fs_test_dispatch_packing(const fs_builder &bld) if (brw_stage_has_packed_dispatch(shader->devinfo, stage, shader->max_polygons, shader->prog_data)) { - const fs_builder ubld = bld.exec_all().group(1, 0); + const brw_builder ubld = bld.exec_all().group(1, 0); const brw_reg tmp = component(bld.vgrf(BRW_TYPE_UD), 0); const brw_reg mask = uses_vmask ? brw_vmask_reg() : brw_dmask_reg(); @@ -7938,7 +7938,7 @@ nir_to_brw(fs_visitor *s) .nir = s->nir, .devinfo = s->devinfo, .mem_ctx = ralloc_context(NULL), - .bld = fs_builder(s).at_end(), + .bld = brw_builder(s).at_end(), }; if (INTEL_DEBUG(DEBUG_ANNOTATION)) diff --git a/src/intel/compiler/brw_fs_reg_allocate.cpp b/src/intel/compiler/brw_fs_reg_allocate.cpp index 50077f8a71a..bd97605240b 100644 --- a/src/intel/compiler/brw_fs_reg_allocate.cpp +++ b/src/intel/compiler/brw_fs_reg_allocate.cpp @@ -288,18 +288,18 @@ private: void build_interference_graph(bool allow_spilling); - brw_reg build_ex_desc(const fs_builder &bld, unsigned reg_size, bool unspill); + brw_reg build_ex_desc(const brw_builder &bld, unsigned reg_size, bool unspill); - brw_reg build_lane_offsets(const fs_builder &bld, - uint32_t spill_offset, int ip); - brw_reg build_single_offset(const fs_builder &bld, + brw_reg build_lane_offsets(const brw_builder &bld, uint32_t spill_offset, int ip); - brw_reg build_legacy_scratch_header(const fs_builder &bld, + brw_reg build_single_offset(const brw_builder &bld, + uint32_t spill_offset, int ip); + brw_reg build_legacy_scratch_header(const brw_builder &bld, uint32_t spill_offset, int ip); - void emit_unspill(const fs_builder &bld, struct brw_shader_stats *stats, + void emit_unspill(const brw_builder &bld, struct brw_shader_stats *stats, brw_reg dst, uint32_t spill_offset, unsigned count, int ip); - void emit_spill(const fs_builder &bld, struct brw_shader_stats *stats, + void emit_spill(const brw_builder &bld, struct brw_shader_stats *stats, brw_reg src, uint32_t spill_offset, unsigned count, int ip); void set_spill_costs(); @@ -677,7 +677,7 @@ fs_reg_alloc::build_interference_graph(bool allow_spilling) } brw_reg -fs_reg_alloc::build_single_offset(const fs_builder &bld, uint32_t spill_offset, int ip) +fs_reg_alloc::build_single_offset(const brw_builder &bld, uint32_t spill_offset, int ip) { brw_reg offset = retype(alloc_spill_reg(1, ip), BRW_TYPE_UD); fs_inst *inst = bld.MOV(offset, brw_imm_ud(spill_offset)); @@ -686,7 +686,7 @@ fs_reg_alloc::build_single_offset(const fs_builder &bld, uint32_t spill_offset, } brw_reg -fs_reg_alloc::build_ex_desc(const fs_builder &bld, unsigned reg_size, bool unspill) +fs_reg_alloc::build_ex_desc(const brw_builder &bld, unsigned reg_size, bool unspill) { /* Use a different area of the address register than what is used in * brw_lower_logical_sends.c (brw_address_reg(2)) so we don't have @@ -724,11 +724,11 @@ fs_reg_alloc::build_ex_desc(const fs_builder &bld, unsigned reg_size, bool unspi } brw_reg -fs_reg_alloc::build_lane_offsets(const fs_builder &bld, uint32_t spill_offset, int ip) +fs_reg_alloc::build_lane_offsets(const brw_builder &bld, uint32_t spill_offset, int ip) { assert(bld.dispatch_width() <= 16 * reg_unit(bld.shader->devinfo)); - const fs_builder ubld = bld.exec_all(); + const brw_builder ubld = bld.exec_all(); const unsigned reg_count = ubld.dispatch_width() / 8; brw_reg offset = retype(alloc_spill_reg(reg_count, ip), BRW_TYPE_UD); @@ -776,11 +776,11 @@ fs_reg_alloc::build_lane_offsets(const fs_builder &bld, uint32_t spill_offset, i * Generate a scratch header for pre-LSC platforms. */ brw_reg -fs_reg_alloc::build_legacy_scratch_header(const fs_builder &bld, +fs_reg_alloc::build_legacy_scratch_header(const brw_builder &bld, uint32_t spill_offset, int ip) { - const fs_builder ubld8 = bld.exec_all().group(8, 0); - const fs_builder ubld1 = bld.exec_all().group(1, 0); + const brw_builder ubld8 = bld.exec_all().group(8, 0); + const brw_builder ubld1 = bld.exec_all().group(1, 0); /* Allocate a spill header and make it interfere with g0 */ brw_reg header = retype(alloc_spill_reg(1, ip), BRW_TYPE_UD); @@ -799,7 +799,7 @@ fs_reg_alloc::build_legacy_scratch_header(const fs_builder &bld, } void -fs_reg_alloc::emit_unspill(const fs_builder &bld, +fs_reg_alloc::emit_unspill(const brw_builder &bld, struct brw_shader_stats *stats, brw_reg dst, uint32_t spill_offset, unsigned count, int ip) @@ -819,7 +819,7 @@ fs_reg_alloc::emit_unspill(const fs_builder &bld, const bool use_transpose = bld.dispatch_width() > 16 * reg_unit(devinfo) || bld.has_writemask_all(); - const fs_builder ubld = use_transpose ? bld.exec_all().group(1, 0) : bld; + const brw_builder ubld = use_transpose ? bld.exec_all().group(1, 0) : bld; brw_reg offset; if (use_transpose) { offset = build_single_offset(ubld, spill_offset, ip); @@ -898,7 +898,7 @@ fs_reg_alloc::emit_unspill(const fs_builder &bld, } void -fs_reg_alloc::emit_spill(const fs_builder &bld, +fs_reg_alloc::emit_spill(const brw_builder &bld, struct brw_shader_stats *stats, brw_reg src, uint32_t spill_offset, unsigned count, int ip) @@ -1136,7 +1136,7 @@ fs_reg_alloc::spill_reg(unsigned spill_reg) */ int ip = 0; foreach_block_and_inst (block, fs_inst, inst, fs->cfg) { - const fs_builder ibld = fs_builder(fs, block, inst); + const brw_builder ibld = brw_builder(fs, block, inst); exec_node *before = inst->prev; exec_node *after = inst->next; @@ -1223,7 +1223,7 @@ fs_reg_alloc::spill_reg(unsigned spill_reg) inst->exec_size == width; /* Builder used to emit the scratch messages. */ - const fs_builder ubld = ibld.exec_all(!per_channel).group(width, 0); + const brw_builder ubld = ibld.exec_all(!per_channel).group(width, 0); /* If our write is going to affect just part of the * regs_written(inst), then we need to unspill the destination since diff --git a/src/intel/compiler/brw_fs_thread_payload.cpp b/src/intel/compiler/brw_fs_thread_payload.cpp index 05a37caaab3..7857d18bbdc 100644 --- a/src/intel/compiler/brw_fs_thread_payload.cpp +++ b/src/intel/compiler/brw_fs_thread_payload.cpp @@ -104,7 +104,7 @@ gs_thread_payload::gs_thread_payload(fs_visitor &v) { struct brw_vue_prog_data *vue_prog_data = brw_vue_prog_data(v.prog_data); struct brw_gs_prog_data *gs_prog_data = brw_gs_prog_data(v.prog_data); - const fs_builder bld = fs_builder(&v).at_end(); + const brw_builder bld = brw_builder(&v).at_end(); /* R0: thread header. */ unsigned r = reg_unit(v.devinfo); @@ -390,7 +390,7 @@ cs_thread_payload::cs_thread_payload(const fs_visitor &v) } void -cs_thread_payload::load_subgroup_id(const fs_builder &bld, +cs_thread_payload::load_subgroup_id(const brw_builder &bld, brw_reg &dest) const { auto devinfo = bld.shader->devinfo; @@ -430,7 +430,7 @@ task_mesh_thread_payload::task_mesh_thread_payload(fs_visitor &v) * the address to descriptors. */ - const fs_builder bld = fs_builder(&v).at_end(); + const brw_builder bld = brw_builder(&v).at_end(); unsigned r = 0; assert(subgroup_id_.file != BAD_FILE); @@ -491,7 +491,7 @@ bs_thread_payload::bs_thread_payload(const fs_visitor &v) } void -bs_thread_payload::load_shader_type(const fs_builder &bld, brw_reg &dest) const +bs_thread_payload::load_shader_type(const brw_builder &bld, brw_reg &dest) const { brw_reg ud_dest = retype(dest, BRW_TYPE_UD); bld.MOV(ud_dest, retype(brw_vec1_grf(0, 3), ud_dest.type)); diff --git a/src/intel/compiler/brw_fs_visitor.cpp b/src/intel/compiler/brw_fs_visitor.cpp index d1ddb8bea8b..7427f93a9fa 100644 --- a/src/intel/compiler/brw_fs_visitor.cpp +++ b/src/intel/compiler/brw_fs_visitor.cpp @@ -64,7 +64,7 @@ fs_visitor::emit_urb_writes(const brw_reg &gs_vertex_count) unreachable("invalid stage"); } - const fs_builder bld = fs_builder(this).at_end(); + const brw_builder bld = brw_builder(this).at_end(); brw_reg per_slot_offsets; @@ -202,7 +202,7 @@ fs_visitor::emit_urb_writes(const brw_reg &gs_vertex_count) break; } - const fs_builder abld = bld.annotate("URB write"); + const brw_builder abld = bld.annotate("URB write"); /* If we've queued up 8 registers of payload (2 VUE slots), if this is * the last slot or if we need to flush (see BAD_FILE varying case @@ -329,7 +329,7 @@ fs_visitor::emit_urb_writes(const brw_reg &gs_vertex_count) void fs_visitor::emit_cs_terminate() { - const fs_builder ubld = fs_builder(this).at_end().exec_all(); + const brw_builder ubld = brw_builder(this).at_end().exec_all(); /* We can't directly send from g0, since sends with EOT have to use * g112-127. So, copy it to a virtual register, The register allocator will diff --git a/src/intel/compiler/brw_lower.cpp b/src/intel/compiler/brw_lower.cpp index bb6dc735887..41f629e4c0e 100644 --- a/src/intel/compiler/brw_lower.cpp +++ b/src/intel/compiler/brw_lower.cpp @@ -62,8 +62,8 @@ brw_lower_load_payload(fs_visitor &s) assert(inst->saturate == false); brw_reg dst = inst->dst; - const fs_builder ibld(&s, block, inst); - const fs_builder ubld = ibld.exec_all(); + const brw_builder ibld(&s, block, inst); + const brw_builder ubld = ibld.exec_all(); for (uint8_t i = 0; i < inst->header_size;) { /* Number of header GRFs to initialize at once with a single MOV @@ -155,7 +155,7 @@ brw_lower_csel(fs_visitor &s) } if (!supported) { - const fs_builder ibld(&s, block, inst); + const brw_builder ibld(&s, block, inst); /* CSEL: dst = src2 0 ? src0 : src1 */ brw_reg zero = brw_imm_reg(orig_type); @@ -187,7 +187,7 @@ brw_lower_sub_sat(fs_visitor &s) bool progress = false; foreach_block_and_inst_safe(block, fs_inst, inst, s.cfg) { - const fs_builder ibld(&s, block, inst); + const brw_builder ibld(&s, block, inst); if (inst->opcode == SHADER_OPCODE_USUB_SAT || inst->opcode == SHADER_OPCODE_ISUB_SAT) { @@ -295,8 +295,8 @@ brw_lower_barycentrics(fs_visitor &s) if (inst->exec_size < 16) continue; - const fs_builder ibld(&s, block, inst); - const fs_builder ubld = ibld.exec_all().group(8, 0); + const brw_builder ibld(&s, block, inst); + const brw_builder ubld = ibld.exec_all().group(8, 0); switch (inst->opcode) { case BRW_OPCODE_PLN: { @@ -355,7 +355,7 @@ static bool lower_derivative(fs_visitor &s, bblock_t *block, fs_inst *inst, unsigned swz0, unsigned swz1) { - const fs_builder ubld = fs_builder(&s, block, inst).exec_all(); + const brw_builder ubld = brw_builder(&s, block, inst).exec_all(); const brw_reg tmp0 = ubld.vgrf(inst->src[0].type); const brw_reg tmp1 = ubld.vgrf(inst->src[0].type); @@ -433,11 +433,11 @@ brw_lower_find_live_channel(fs_visitor &s) * useless there. */ - const fs_builder ibld(&s, block, inst); + const brw_builder ibld(&s, block, inst); if (!inst->is_partial_write()) ibld.emit_undef_for_dst(inst); - const fs_builder ubld = fs_builder(&s, block, inst).exec_all().group(1, 0); + const brw_builder ubld = brw_builder(&s, block, inst).exec_all().group(1, 0); brw_reg exec_mask = ubld.vgrf(BRW_TYPE_UD); ubld.UNDEF(exec_mask); @@ -529,7 +529,7 @@ brw_lower_sends_overlapping_payload(fs_visitor &s) /* Sadly, we've lost all notion of channels and bit sizes at this * point. Just WE_all it. */ - const fs_builder ibld = fs_builder(&s, block, inst).exec_all().group(16, 0); + const brw_builder ibld = brw_builder(&s, block, inst).exec_all().group(16, 0); brw_reg copy_src = retype(inst->src[arg], BRW_TYPE_UD); brw_reg copy_dst = tmp; for (unsigned i = 0; i < len; i += 2) { @@ -606,7 +606,7 @@ brw_lower_alu_restrictions(fs_visitor &s) assert(!inst->saturate); assert(!inst->src[0].abs); assert(!inst->src[0].negate); - const brw::fs_builder ibld(&s, block, inst); + const brw::brw_builder ibld(&s, block, inst); enum brw_reg_type type = brw_type_with_size(inst->dst.type, 32); @@ -630,7 +630,7 @@ brw_lower_alu_restrictions(fs_visitor &s) assert(!inst->src[0].abs && !inst->src[0].negate); assert(!inst->src[1].abs && !inst->src[1].negate); assert(inst->conditional_mod == BRW_CONDITIONAL_NONE); - const brw::fs_builder ibld(&s, block, inst); + const brw::brw_builder ibld(&s, block, inst); enum brw_reg_type type = brw_type_with_size(inst->dst.type, 32); @@ -766,9 +766,9 @@ brw_lower_load_subgroup_invocation(fs_visitor &s) if (inst->opcode != SHADER_OPCODE_LOAD_SUBGROUP_INVOCATION) continue; - const fs_builder abld = - fs_builder(&s, block, inst).annotate("SubgroupInvocation"); - const fs_builder ubld8 = abld.group(8, 0).exec_all(); + const brw_builder abld = + brw_builder(&s, block, inst).annotate("SubgroupInvocation"); + const brw_builder ubld8 = abld.group(8, 0).exec_all(); ubld8.UNDEF(inst->dst); if (inst->exec_size == 8) { @@ -781,7 +781,7 @@ brw_lower_load_subgroup_invocation(fs_visitor &s) ubld8.MOV(inst->dst, brw_imm_v(0x76543210)); ubld8.ADD(byte_offset(inst->dst, 16), inst->dst, brw_imm_uw(8u)); if (inst->exec_size > 16) { - const fs_builder ubld16 = abld.group(16, 0).exec_all(); + const brw_builder ubld16 = abld.group(16, 0).exec_all(); ubld16.ADD(byte_offset(inst->dst, 32), inst->dst, brw_imm_uw(16u)); } } @@ -814,7 +814,7 @@ brw_lower_indirect_mov(fs_visitor &s) assert(brw_type_size_bytes(inst->src[0].type) == brw_type_size_bytes(inst->dst.type)); - const fs_builder ibld(&s, block, inst); + const brw_builder ibld(&s, block, inst); /* Extract unaligned part */ uint16_t extra_offset = inst->src[0].offset & 0x1; diff --git a/src/intel/compiler/brw_lower_dpas.cpp b/src/intel/compiler/brw_lower_dpas.cpp index 77d08721049..0a247f6f573 100644 --- a/src/intel/compiler/brw_lower_dpas.cpp +++ b/src/intel/compiler/brw_lower_dpas.cpp @@ -9,7 +9,7 @@ using namespace brw; static void -f16_using_mac(const fs_builder &bld, fs_inst *inst) +f16_using_mac(const brw_builder &bld, fs_inst *inst) { /* We only intend to support configurations where the destination and * accumulator have the same type. @@ -115,7 +115,7 @@ f16_using_mac(const fs_builder &bld, fs_inst *inst) } static void -int8_using_dp4a(const fs_builder &bld, fs_inst *inst) +int8_using_dp4a(const brw_builder &bld, fs_inst *inst) { /* We only intend to support configurations where the destination and * accumulator have the same type. @@ -162,7 +162,7 @@ int8_using_dp4a(const fs_builder &bld, fs_inst *inst) } static void -int8_using_mul_add(const fs_builder &bld, fs_inst *inst) +int8_using_mul_add(const brw_builder &bld, fs_inst *inst) { /* We only intend to support configurations where the destination and * accumulator have the same type. @@ -280,7 +280,7 @@ brw_lower_dpas(fs_visitor &v) continue; const unsigned exec_size = v.devinfo->ver >= 20 ? 16 : 8; - const fs_builder bld = fs_builder(&v, block, inst).group(exec_size, 0).exec_all(); + const brw_builder bld = brw_builder(&v, block, inst).group(exec_size, 0).exec_all(); if (brw_type_is_float(inst->dst.type)) { f16_using_mac(bld, inst); diff --git a/src/intel/compiler/brw_lower_integer_multiplication.cpp b/src/intel/compiler/brw_lower_integer_multiplication.cpp index 0597c05579e..46b8a4e6b73 100644 --- a/src/intel/compiler/brw_lower_integer_multiplication.cpp +++ b/src/intel/compiler/brw_lower_integer_multiplication.cpp @@ -142,7 +142,7 @@ static void brw_lower_mul_dword_inst(fs_visitor &s, fs_inst *inst, bblock_t *block) { const intel_device_info *devinfo = s.devinfo; - const fs_builder ibld(&s, block, inst); + const brw_builder ibld(&s, block, inst); /* It is correct to use inst->src[1].d in both end of the comparison. * Using .ud in the UINT16_MAX comparison would cause any negative value to @@ -304,7 +304,7 @@ static void brw_lower_mul_qword_inst(fs_visitor &s, fs_inst *inst, bblock_t *block) { const intel_device_info *devinfo = s.devinfo; - const fs_builder ibld(&s, block, inst); + const brw_builder ibld(&s, block, inst); /* Considering two 64-bit integers ab and cd where each letter ab * corresponds to 32 bits, we get a 128-bit result WXYZ. We * cd @@ -373,7 +373,7 @@ static void brw_lower_mulh_inst(fs_visitor &s, fs_inst *inst, bblock_t *block) { const intel_device_info *devinfo = s.devinfo; - const fs_builder ibld(&s, block, inst); + const brw_builder ibld(&s, block, inst); /* According to the BDW+ BSpec page for the "Multiply Accumulate * High" instruction: diff --git a/src/intel/compiler/brw_lower_logical_sends.cpp b/src/intel/compiler/brw_lower_logical_sends.cpp index 821c5ea2cc2..268ded3227f 100644 --- a/src/intel/compiler/brw_lower_logical_sends.cpp +++ b/src/intel/compiler/brw_lower_logical_sends.cpp @@ -32,7 +32,7 @@ using namespace brw; static void -lower_urb_read_logical_send(const fs_builder &bld, fs_inst *inst) +lower_urb_read_logical_send(const brw_builder &bld, fs_inst *inst) { const intel_device_info *devinfo = bld.shader->devinfo; const bool per_slot_present = @@ -75,7 +75,7 @@ lower_urb_read_logical_send(const fs_builder &bld, fs_inst *inst) } static void -lower_urb_read_logical_send_xe2(const fs_builder &bld, fs_inst *inst) +lower_urb_read_logical_send_xe2(const brw_builder &bld, fs_inst *inst) { const intel_device_info *devinfo = bld.shader->devinfo; assert(devinfo->has_lsc); @@ -134,7 +134,7 @@ lower_urb_read_logical_send_xe2(const fs_builder &bld, fs_inst *inst) } static void -lower_urb_write_logical_send(const fs_builder &bld, fs_inst *inst) +lower_urb_write_logical_send(const brw_builder &bld, fs_inst *inst) { const intel_device_info *devinfo = bld.shader->devinfo; const bool per_slot_present = @@ -191,7 +191,7 @@ lower_urb_write_logical_send(const fs_builder &bld, fs_inst *inst) } static void -lower_urb_write_logical_send_xe2(const fs_builder &bld, fs_inst *inst) +lower_urb_write_logical_send_xe2(const brw_builder &bld, fs_inst *inst) { const intel_device_info *devinfo = bld.shader->devinfo; assert(devinfo->has_lsc); @@ -264,7 +264,7 @@ lower_urb_write_logical_send_xe2(const fs_builder &bld, fs_inst *inst) } static void -setup_color_payload(const fs_builder &bld, const brw_wm_prog_key *key, +setup_color_payload(const brw_builder &bld, const brw_wm_prog_key *key, brw_reg *dst, brw_reg color, unsigned components) { if (key->clamp_fragment_color) { @@ -283,7 +283,7 @@ setup_color_payload(const fs_builder &bld, const brw_wm_prog_key *key, } static void -lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst, +lower_fb_write_logical_send(const brw_builder &bld, fs_inst *inst, const struct brw_wm_prog_data *prog_data, const brw_wm_prog_key *key, const fs_thread_payload &fs_payload) @@ -318,7 +318,7 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst, * dispatched. This field is only required for the end-of- * thread message and on all dual-source messages." */ - const fs_builder ubld = bld.exec_all().group(8, 0); + const brw_builder ubld = bld.exec_all().group(8, 0); brw_reg header = ubld.vgrf(BRW_TYPE_UD, 2); if (bld.group() < 16) { @@ -386,8 +386,8 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst, if (src0_alpha.file != BAD_FILE) { for (unsigned i = 0; i < bld.dispatch_width() / 8; i++) { - const fs_builder &ubld = bld.exec_all().group(8, i) - .annotate("FB write src0 alpha"); + const brw_builder &ubld = bld.exec_all().group(8, i) + .annotate("FB write src0 alpha"); const brw_reg tmp = ubld.vgrf(BRW_TYPE_F); ubld.MOV(tmp, horiz_offset(src0_alpha, i * 8)); setup_color_payload(ubld, key, &sources[length], tmp, 1); @@ -474,7 +474,7 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst, inst->desc |= (1 << 18); } else if (prog_data->coarse_pixel_dispatch == INTEL_SOMETIMES) { STATIC_ASSERT(INTEL_MSAA_FLAG_COARSE_RT_WRITES == (1 << 18)); - const fs_builder &ubld = bld.exec_all().group(8, 0); + const brw_builder &ubld = bld.exec_all().group(8, 0); desc = ubld.vgrf(BRW_TYPE_UD); ubld.AND(desc, dynamic_msaa_flags(prog_data), brw_imm_ud(INTEL_MSAA_FLAG_COARSE_RT_WRITES)); @@ -513,11 +513,11 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst, } static void -lower_fb_read_logical_send(const fs_builder &bld, fs_inst *inst, +lower_fb_read_logical_send(const brw_builder &bld, fs_inst *inst, const struct brw_wm_prog_data *wm_prog_data) { const intel_device_info *devinfo = bld.shader->devinfo; - const fs_builder &ubld = bld.exec_all().group(8, 0); + const brw_builder &ubld = bld.exec_all().group(8, 0); const unsigned length = 2; const brw_reg header = ubld.vgrf(BRW_TYPE_UD, length); @@ -676,7 +676,7 @@ sampler_msg_type(const intel_device_info *devinfo, * the given requested_alignment_sz. */ static fs_inst * -emit_load_payload_with_padding(const fs_builder &bld, const brw_reg &dst, +emit_load_payload_with_padding(const brw_builder &bld, const brw_reg &dst, const brw_reg *src, unsigned sources, unsigned header_size, unsigned requested_alignment_sz) @@ -734,7 +734,7 @@ shader_opcode_needs_header(opcode op) } static void -lower_sampler_logical_send(const fs_builder &bld, fs_inst *inst, +lower_sampler_logical_send(const brw_builder &bld, fs_inst *inst, const brw_reg &coordinate, const brw_reg &shadow_c, brw_reg lod, const brw_reg &lod2, @@ -808,8 +808,8 @@ lower_sampler_logical_send(const fs_builder &bld, fs_inst *inst, inst->offset |= 1 << 23; /* g0.2 bit23 : Pixel Null Mask Enable */ /* Build the actual header */ - const fs_builder ubld = bld.exec_all().group(8 * reg_unit(devinfo), 0); - const fs_builder ubld1 = ubld.group(1, 0); + const brw_builder ubld = bld.exec_all().group(8 * reg_unit(devinfo), 0); + const brw_builder ubld1 = ubld.group(1, 0); if (devinfo->ver >= 11) ubld.MOV(header, brw_imm_ud(0)); else @@ -1158,7 +1158,7 @@ lower_sampler_logical_send(const fs_builder &bld, fs_inst *inst, if (sampler_handle.file != BAD_FILE || sampler.file == IMM) { inst->src[0] = brw_imm_ud(0); } else { - const fs_builder ubld = bld.group(1, 0).exec_all(); + const brw_builder ubld = bld.group(1, 0).exec_all(); brw_reg desc = ubld.vgrf(BRW_TYPE_UD); ubld.SHL(desc, sampler, brw_imm_ud(8)); inst->src[0] = component(desc, 0); @@ -1177,7 +1177,7 @@ lower_sampler_logical_send(const fs_builder &bld, fs_inst *inst, msg_type, simd_mode, sampler_ret_type); - const fs_builder ubld = bld.group(1, 0).exec_all(); + const brw_builder ubld = bld.group(1, 0).exec_all(); brw_reg desc = ubld.vgrf(BRW_TYPE_UD); if (surface.equals(sampler)) { /* This case is common in GL */ @@ -1260,7 +1260,7 @@ get_sampler_msg_payload_type_bit_size(const intel_device_info *devinfo, } static void -lower_sampler_logical_send(const fs_builder &bld, fs_inst *inst) +lower_sampler_logical_send(const brw_builder &bld, fs_inst *inst) { const intel_device_info *devinfo = bld.shader->devinfo; const brw_reg coordinate = inst->src[TEX_LOGICAL_SRC_COORDINATE]; @@ -1303,13 +1303,13 @@ lower_sampler_logical_send(const fs_builder &bld, fs_inst *inst) * Predicate the specified instruction on the vector mask. */ static void -emit_predicate_on_vector_mask(const fs_builder &bld, fs_inst *inst) +emit_predicate_on_vector_mask(const brw_builder &bld, fs_inst *inst) { assert(bld.shader->stage == MESA_SHADER_FRAGMENT && bld.group() == inst->group && bld.dispatch_width() == inst->exec_size); - const fs_builder ubld = bld.exec_all().group(1, 0); + const brw_builder ubld = bld.exec_all().group(1, 0); const fs_visitor &s = *bld.shader; const brw_reg vector_mask = ubld.vgrf(BRW_TYPE_UW); @@ -1337,7 +1337,7 @@ emit_predicate_on_vector_mask(const fs_builder &bld, fs_inst *inst) } static void -setup_surface_descriptors(const fs_builder &bld, fs_inst *inst, uint32_t desc, +setup_surface_descriptors(const brw_builder &bld, fs_inst *inst, uint32_t desc, const brw_reg &surface, const brw_reg &surface_handle) { const brw_compiler *compiler = bld.shader->compiler; @@ -1361,7 +1361,7 @@ setup_surface_descriptors(const fs_builder &bld, fs_inst *inst, uint32_t desc, inst->send_ex_bso = compiler->extended_bindless_surface_offset; } else { inst->desc = desc; - const fs_builder ubld = bld.exec_all().group(1, 0); + const brw_builder ubld = bld.exec_all().group(1, 0); brw_reg tmp = ubld.vgrf(BRW_TYPE_UD); ubld.AND(tmp, surface, brw_imm_ud(0xff)); inst->src[0] = component(tmp, 0); @@ -1370,7 +1370,7 @@ setup_surface_descriptors(const fs_builder &bld, fs_inst *inst, uint32_t desc, } static void -setup_lsc_surface_descriptors(const fs_builder &bld, fs_inst *inst, +setup_lsc_surface_descriptors(const brw_builder &bld, fs_inst *inst, uint32_t desc, const brw_reg &surface) { const ASSERTED intel_device_info *devinfo = bld.shader->devinfo; @@ -1399,7 +1399,7 @@ setup_lsc_surface_descriptors(const fs_builder &bld, fs_inst *inst, if (surface.file == IMM) { inst->src[1] = brw_imm_ud(lsc_bti_ex_desc(devinfo, surface.ud)); } else { - const fs_builder ubld = bld.exec_all().group(1, 0); + const brw_builder ubld = bld.exec_all().group(1, 0); brw_reg tmp = ubld.vgrf(BRW_TYPE_UD); ubld.SHL(tmp, surface, brw_imm_ud(24)); inst->src[1] = component(tmp, 0); @@ -1427,7 +1427,7 @@ lsc_addr_size_for_type(enum brw_reg_type type) } static void -lower_lsc_memory_logical_send(const fs_builder &bld, fs_inst *inst) +lower_lsc_memory_logical_send(const brw_builder &bld, fs_inst *inst) { const intel_device_info *devinfo = bld.shader->devinfo; assert(devinfo->has_lsc); @@ -1470,7 +1470,7 @@ lower_lsc_memory_logical_send(const fs_builder &bld, fs_inst *inst) if (addr.file != VGRF || !addr.is_contiguous()) { if (inst->force_writemask_all) { - const fs_builder dbld = bld.group(bld.shader->dispatch_width, 0); + const brw_builder dbld = bld.group(bld.shader->dispatch_width, 0); payload = dbld.move_to_vgrf(addr, coord_components); } else { payload = bld.move_to_vgrf(addr, coord_components); @@ -1584,16 +1584,16 @@ lower_lsc_memory_logical_send(const fs_builder &bld, fs_inst *inst) } static brw_reg -emit_a64_oword_block_header(const fs_builder &bld, const brw_reg &addr) +emit_a64_oword_block_header(const brw_builder &bld, const brw_reg &addr) { - const fs_builder ubld = bld.exec_all().group(8, 0); + const brw_builder ubld = bld.exec_all().group(8, 0); assert(brw_type_size_bytes(addr.type) == 8 && addr.stride == 0); brw_reg expanded_addr = addr; if (addr.file == UNIFORM) { /* We can't do stride 1 with the UNIFORM file, it requires stride 0 */ - fs_builder ubld1 = ubld.group(1, 0); + brw_builder ubld1 = ubld.group(1, 0); brw_reg tmp = ubld1.vgrf(BRW_TYPE_UQ); ubld1.UNDEF(tmp); @@ -1615,7 +1615,7 @@ emit_a64_oword_block_header(const fs_builder &bld, const brw_reg &addr) } static void -lower_hdc_memory_logical_send(const fs_builder &bld, fs_inst *inst) +lower_hdc_memory_logical_send(const brw_builder &bld, fs_inst *inst) { const intel_device_info *devinfo = bld.shader->devinfo; const brw_compiler *compiler = bld.shader->compiler; @@ -1681,8 +1681,8 @@ lower_hdc_memory_logical_send(const fs_builder &bld, fs_inst *inst) unsigned addr_size_B = coord_components * lsc_addr_size_bytes(addr_size); brw_reg header; - fs_builder ubld8 = bld.exec_all().group(8, 0); - fs_builder ubld1 = ubld8.group(1, 0); + brw_builder ubld8 = bld.exec_all().group(8, 0); + brw_builder ubld1 = ubld8.group(1, 0); if (mode == MEMORY_MODE_SCRATCH) { header = ubld8.vgrf(BRW_TYPE_UD); ubld8.emit(SHADER_OPCODE_SCRATCH_HEADER, header, brw_ud8_grf(0, 0)); @@ -1906,7 +1906,7 @@ lower_hdc_memory_logical_send(const fs_builder &bld, fs_inst *inst) } static void -lower_lsc_varying_pull_constant_logical_send(const fs_builder &bld, +lower_lsc_varying_pull_constant_logical_send(const brw_builder &bld, fs_inst *inst) { const intel_device_info *devinfo = bld.shader->devinfo; @@ -1993,7 +1993,7 @@ lower_lsc_varying_pull_constant_logical_send(const fs_builder &bld, } static void -lower_varying_pull_constant_logical_send(const fs_builder &bld, fs_inst *inst) +lower_varying_pull_constant_logical_send(const brw_builder &bld, fs_inst *inst) { const intel_device_info *devinfo = bld.shader->devinfo; const brw_compiler *compiler = bld.shader->compiler; @@ -2071,7 +2071,7 @@ lower_varying_pull_constant_logical_send(const fs_builder &bld, fs_inst *inst) } static void -lower_interpolator_logical_send(const fs_builder &bld, fs_inst *inst, +lower_interpolator_logical_send(const brw_builder &bld, fs_inst *inst, const struct brw_wm_prog_key *wm_prog_key, const struct brw_wm_prog_data *wm_prog_data) { @@ -2122,7 +2122,7 @@ lower_interpolator_logical_send(const fs_builder &bld, fs_inst *inst, } else if (wm_prog_data->coarse_pixel_dispatch == INTEL_SOMETIMES) { STATIC_ASSERT(INTEL_MSAA_FLAG_COARSE_PI_MSG == (1 << 15)); brw_reg orig_desc = desc; - const fs_builder &ubld = bld.exec_all().group(8, 0); + const brw_builder &ubld = bld.exec_all().group(8, 0); desc = ubld.vgrf(BRW_TYPE_UD); ubld.AND(desc, dynamic_msaa_flags(wm_prog_data), brw_imm_ud(INTEL_MSAA_FLAG_COARSE_PI_MSG)); @@ -2152,7 +2152,7 @@ lower_interpolator_logical_send(const fs_builder &bld, fs_inst *inst, */ if (dynamic_mode) { brw_reg orig_desc = desc; - const fs_builder &ubld = bld.exec_all().group(8, 0); + const brw_builder &ubld = bld.exec_all().group(8, 0); desc = ubld.vgrf(BRW_TYPE_UD); /* The predicate should have been built in brw_fs_nir.cpp when emitting @@ -2195,7 +2195,7 @@ lower_interpolator_logical_send(const fs_builder &bld, fs_inst *inst, } static void -lower_btd_logical_send(const fs_builder &bld, fs_inst *inst) +lower_btd_logical_send(const brw_builder &bld, fs_inst *inst) { const intel_device_info *devinfo = bld.shader->devinfo; brw_reg global_addr = inst->src[0]; @@ -2203,7 +2203,7 @@ lower_btd_logical_send(const fs_builder &bld, fs_inst *inst) const unsigned unit = reg_unit(devinfo); const unsigned mlen = 2 * unit; - const fs_builder ubld = bld.exec_all(); + const brw_builder ubld = bld.exec_all(); brw_reg header = ubld.vgrf(BRW_TYPE_UD, 2 * unit); ubld.MOV(header, brw_imm_ud(0)); @@ -2267,7 +2267,7 @@ lower_btd_logical_send(const fs_builder &bld, fs_inst *inst) } static void -lower_trace_ray_logical_send(const fs_builder &bld, fs_inst *inst) +lower_trace_ray_logical_send(const brw_builder &bld, fs_inst *inst) { const intel_device_info *devinfo = bld.shader->devinfo; /* The emit_uniformize() in brw_fs_nir.cpp will generate an horizontal @@ -2292,7 +2292,7 @@ lower_trace_ray_logical_send(const fs_builder &bld, fs_inst *inst) const unsigned unit = reg_unit(devinfo); const unsigned mlen = unit; - const fs_builder ubld = bld.exec_all(); + const brw_builder ubld = bld.exec_all(); brw_reg header = ubld.vgrf(BRW_TYPE_UD); ubld.MOV(header, brw_imm_ud(0)); @@ -2364,7 +2364,7 @@ lower_trace_ray_logical_send(const fs_builder &bld, fs_inst *inst) } static void -lower_get_buffer_size(const fs_builder &bld, fs_inst *inst) +lower_get_buffer_size(const brw_builder &bld, fs_inst *inst) { const intel_device_info *devinfo = bld.shader->devinfo; /* Since we can only execute this instruction on uniform bti/surface @@ -2404,7 +2404,7 @@ brw_lower_logical_sends(fs_visitor &s) bool progress = false; foreach_block_and_inst_safe(block, fs_inst, inst, s.cfg) { - const fs_builder ibld(&s, block, inst); + const brw_builder ibld(&s, block, inst); switch (inst->opcode) { case FS_OPCODE_FB_WRITE_LOGICAL: @@ -2543,8 +2543,8 @@ brw_lower_uniform_pull_constant_loads(fs_visitor &s) assert(size_B.file == IMM); if (devinfo->has_lsc) { - const fs_builder ubld = - fs_builder(&s, block, inst).group(8, 0).exec_all(); + const brw_builder ubld = + brw_builder(&s, block, inst).group(8, 0).exec_all(); const brw_reg payload = ubld.vgrf(BRW_TYPE_UD); ubld.MOV(payload, offset_B); @@ -2581,8 +2581,8 @@ brw_lower_uniform_pull_constant_loads(fs_visitor &s) s.invalidate_analysis(DEPENDENCY_INSTRUCTIONS | DEPENDENCY_VARIABLES); } else { - const fs_builder ubld = fs_builder(&s, block, inst).exec_all(); - brw_reg header = fs_builder(&s, 8).exec_all().vgrf(BRW_TYPE_UD); + const brw_builder ubld = brw_builder(&s, block, inst).exec_all(); + brw_reg header = brw_builder(&s, 8).exec_all().vgrf(BRW_TYPE_UD); ubld.group(8, 0).MOV(header, retype(brw_vec8_grf(0, 0), BRW_TYPE_UD)); @@ -2624,7 +2624,7 @@ brw_lower_send_descriptors(fs_visitor &s) if (inst->opcode != SHADER_OPCODE_SEND) continue; - const fs_builder ubld = fs_builder(&s, block, inst).exec_all().group(1, 0); + const brw_builder ubld = brw_builder(&s, block, inst).exec_all().group(1, 0); /* Descriptor */ const unsigned rlen = inst->dst.is_null() ? 0 : inst->size_written / REG_SIZE; diff --git a/src/intel/compiler/brw_lower_pack.cpp b/src/intel/compiler/brw_lower_pack.cpp index 8b9fa3f6539..805046f323f 100644 --- a/src/intel/compiler/brw_lower_pack.cpp +++ b/src/intel/compiler/brw_lower_pack.cpp @@ -42,7 +42,7 @@ brw_lower_pack(fs_visitor &s) assert(inst->saturate == false); brw_reg dst = inst->dst; - const fs_builder ibld(&s, block, inst); + const brw_builder ibld(&s, block, inst); /* The lowering generates 2 instructions for what was previously 1. This * can trick the IR to believe we're doing partial writes, but the * register is actually fully written. Mark it as undef to help the IR diff --git a/src/intel/compiler/brw_lower_regioning.cpp b/src/intel/compiler/brw_lower_regioning.cpp index 229d57c9197..defe845bb68 100644 --- a/src/intel/compiler/brw_lower_regioning.cpp +++ b/src/intel/compiler/brw_lower_regioning.cpp @@ -478,7 +478,7 @@ namespace brw { MIN2(brw_type_size_bytes(inst->src[0].type), brw_type_size_bytes(inst->src[1].type)) >= 4 || brw_type_size_bytes(inst->src[i].type) == get_exec_type_size(inst)); - const fs_builder ibld(v, block, inst); + const brw_builder ibld(v, block, inst); const brw_reg tmp = ibld.vgrf(get_exec_type(inst)); lower_instruction(v, block, ibld.MOV(tmp, inst->src[i])); @@ -499,7 +499,7 @@ namespace { bool lower_dst_modifiers(fs_visitor *v, bblock_t *block, fs_inst *inst) { - const fs_builder ibld(v, block, inst); + const brw_builder ibld(v, block, inst); const brw_reg_type type = get_exec_type(inst); /* Not strictly necessary, but if possible use a temporary with the same * channel alignment as the current destination in order to avoid @@ -550,7 +550,7 @@ namespace { { assert(inst->components_read(i) == 1); const intel_device_info *devinfo = v->devinfo; - const fs_builder ibld(v, block, inst); + const brw_builder ibld(v, block, inst); const unsigned stride = required_src_byte_stride(devinfo, inst, i) / brw_type_size_bytes(inst->src[i].type); assert(stride > 0); @@ -618,7 +618,7 @@ namespace { assert(inst->opcode != BRW_OPCODE_MUL || !inst->dst.is_accumulator() || brw_type_is_float(inst->dst.type)); - const fs_builder ibld(v, block, inst); + const brw_builder ibld(v, block, inst); const unsigned stride = required_dst_byte_stride(inst) / brw_type_size_bytes(inst->dst.type); assert(stride > 0); @@ -689,7 +689,7 @@ namespace { const unsigned mask = has_invalid_exec_type(v->devinfo, inst); const brw_reg_type raw_type = required_exec_type(v->devinfo, inst); const unsigned n = get_exec_type_size(inst) / brw_type_size_bytes(raw_type); - const fs_builder ibld(v, block, inst); + const brw_builder ibld(v, block, inst); brw_reg tmp = ibld.vgrf(inst->dst.type, inst->dst.stride); ibld.UNDEF(tmp); @@ -736,7 +736,7 @@ namespace { lower_src_conversion(fs_visitor *v, bblock_t *block, fs_inst *inst) { const intel_device_info *devinfo = v->devinfo; - const fs_builder ibld = fs_builder(v, block, inst).scalar_group(); + const brw_builder ibld = brw_builder(v, block, inst).scalar_group(); /* We only handle scalar conversions from small types for now. */ assert(is_uniform(inst->src[0])); diff --git a/src/intel/compiler/brw_lower_scoreboard.cpp b/src/intel/compiler/brw_lower_scoreboard.cpp index 1a751fc9b1a..cccd217849f 100644 --- a/src/intel/compiler/brw_lower_scoreboard.cpp +++ b/src/intel/compiler/brw_lower_scoreboard.cpp @@ -1304,8 +1304,8 @@ namespace { /* Emit dependency into the SWSB of an extra SYNC * instruction. */ - const fs_builder ibld = fs_builder(shader, block, inst) - .exec_all().group(1, 0); + const brw_builder ibld = brw_builder(shader, block, inst) + .exec_all().group(1, 0); fs_inst *sync = ibld.SYNC(TGL_SYNC_NOP); sync->sched.sbid = dep.id; sync->sched.mode = dep.unordered; @@ -1327,8 +1327,8 @@ namespace { * scenario with unordered dependencies should have been * handled above. */ - const fs_builder ibld = fs_builder(shader, block, inst) - .exec_all().group(1, 0); + const brw_builder ibld = brw_builder(shader, block, inst) + .exec_all().group(1, 0); fs_inst *sync = ibld.SYNC(TGL_SYNC_NOP); sync->sched = ordered_dependency_swsb(deps[ip], jps[ip], true); break; diff --git a/src/intel/compiler/brw_lower_simd_width.cpp b/src/intel/compiler/brw_lower_simd_width.cpp index c97d1c77be6..b7fe4e01768 100644 --- a/src/intel/compiler/brw_lower_simd_width.cpp +++ b/src/intel/compiler/brw_lower_simd_width.cpp @@ -470,7 +470,7 @@ brw_get_lowered_simd_width(const fs_visitor *shader, const fs_inst *inst) * of the lowered instruction. */ static inline bool -needs_src_copy(const fs_builder &lbld, const fs_inst *inst, unsigned i) +needs_src_copy(const brw_builder &lbld, const fs_inst *inst, unsigned i) { /* The indirectly indexed register stays the same even if we split the * instruction. @@ -492,7 +492,7 @@ needs_src_copy(const fs_builder &lbld, const fs_inst *inst, unsigned i) * it as result in packed form. */ static brw_reg -emit_unzip(const fs_builder &lbld, fs_inst *inst, unsigned i) +emit_unzip(const brw_builder &lbld, fs_inst *inst, unsigned i) { assert(lbld.group() >= inst->group); @@ -537,7 +537,7 @@ emit_unzip(const fs_builder &lbld, fs_inst *inst, unsigned i) * destination region. */ static inline bool -needs_dst_copy(const fs_builder &lbld, const fs_inst *inst) +needs_dst_copy(const brw_builder &lbld, const fs_inst *inst) { if (inst->dst.is_null()) return false; @@ -580,7 +580,7 @@ needs_dst_copy(const fs_builder &lbld, const fs_inst *inst) * zipping up the destination of \p inst will be inserted using \p lbld_after. */ static brw_reg -emit_zip(const fs_builder &lbld_before, const fs_builder &lbld_after, +emit_zip(const brw_builder &lbld_before, const brw_builder &lbld_after, fs_inst *inst) { assert(lbld_before.dispatch_width() == lbld_after.dispatch_width()); @@ -632,7 +632,7 @@ emit_zip(const fs_builder &lbld_before, const fs_builder &lbld_after, * have to build a single 32bit value for the SIMD32 message out of 2 * SIMD16 16 bit values. */ - const fs_builder rbld = lbld_after.exec_all().group(1, 0); + const brw_builder rbld = lbld_after.exec_all().group(1, 0); brw_reg local_res_reg = component( retype(offset(tmp, lbld_before, dst_size), BRW_TYPE_UW), 0); brw_reg final_res_reg = @@ -660,8 +660,8 @@ brw_lower_simd_width(fs_visitor &s) assert(lower_width < inst->exec_size); /* Builder matching the original instruction. */ - const fs_builder bld = fs_builder(&s).at_end(); - const fs_builder ibld = + const brw_builder bld = brw_builder(&s).at_end(); + const brw_builder ibld = bld.at(block, inst).exec_all(inst->force_writemask_all) .group(inst->exec_size, inst->group / inst->exec_size); @@ -737,7 +737,7 @@ brw_lower_simd_width(fs_visitor &s) * transform the sources and destination and emit the lowered * instruction. */ - const fs_builder lbld = ibld.group(lower_width, i); + const brw_builder lbld = ibld.group(lower_width, i); for (unsigned j = 0; j < inst->sources; j++) split_inst.src[j] = emit_unzip(lbld.at(block, inst), inst, j); diff --git a/src/intel/compiler/brw_lower_subgroup_ops.cpp b/src/intel/compiler/brw_lower_subgroup_ops.cpp index 20bc3218c19..6ecf328b624 100644 --- a/src/intel/compiler/brw_lower_subgroup_ops.cpp +++ b/src/intel/compiler/brw_lower_subgroup_ops.cpp @@ -122,7 +122,7 @@ brw_get_reduction_info(brw_reduce_op red_op, brw_reg_type type) } static void -brw_emit_scan_step(const fs_builder &bld, enum opcode opcode, brw_conditional_mod mod, +brw_emit_scan_step(const brw_builder &bld, enum opcode opcode, brw_conditional_mod mod, const brw_reg &tmp, unsigned left_offset, unsigned left_stride, unsigned right_offset, unsigned right_stride) @@ -187,7 +187,7 @@ brw_emit_scan_step(const fs_builder &bld, enum opcode opcode, brw_conditional_mo } static void -brw_emit_scan(const fs_builder &bld, enum opcode opcode, const brw_reg &tmp, +brw_emit_scan(const brw_builder &bld, enum opcode opcode, const brw_reg &tmp, unsigned cluster_size, brw_conditional_mod mod) { unsigned dispatch_width = bld.dispatch_width(); @@ -198,7 +198,7 @@ brw_emit_scan(const fs_builder &bld, enum opcode opcode, const brw_reg &tmp, */ if (dispatch_width * brw_type_size_bytes(tmp.type) > 2 * REG_SIZE) { const unsigned half_width = dispatch_width / 2; - const fs_builder ubld = bld.exec_all().group(half_width, 0); + const brw_builder ubld = bld.exec_all().group(half_width, 0); brw_reg left = tmp; brw_reg right = horiz_offset(tmp, half_width); brw_emit_scan(ubld, opcode, left, cluster_size, mod); @@ -211,13 +211,13 @@ brw_emit_scan(const fs_builder &bld, enum opcode opcode, const brw_reg &tmp, } if (cluster_size > 1) { - const fs_builder ubld = bld.exec_all().group(dispatch_width / 2, 0); + const brw_builder ubld = bld.exec_all().group(dispatch_width / 2, 0); brw_emit_scan_step(ubld, opcode, mod, tmp, 0, 2, 1, 2); } if (cluster_size > 2) { if (brw_type_size_bytes(tmp.type) <= 4) { - const fs_builder ubld = + const brw_builder ubld = bld.exec_all().group(dispatch_width / 4, 0); brw_emit_scan_step(ubld, opcode, mod, tmp, 1, 4, 2, 4); brw_emit_scan_step(ubld, opcode, mod, tmp, 1, 4, 3, 4); @@ -228,7 +228,7 @@ brw_emit_scan(const fs_builder &bld, enum opcode opcode, const brw_reg &tmp, * 8-wide in that case and it's the same number of * instructions. */ - const fs_builder ubld = bld.exec_all().group(2, 0); + const brw_builder ubld = bld.exec_all().group(2, 0); for (unsigned i = 0; i < dispatch_width; i += 4) brw_emit_scan_step(ubld, opcode, mod, tmp, i + 1, 0, i + 2, 1); } @@ -237,7 +237,7 @@ brw_emit_scan(const fs_builder &bld, enum opcode opcode, const brw_reg &tmp, for (unsigned i = 4; i < MIN2(cluster_size, dispatch_width); i *= 2) { - const fs_builder ubld = bld.exec_all().group(i, 0); + const brw_builder ubld = bld.exec_all().group(i, 0); brw_emit_scan_step(ubld, opcode, mod, tmp, i - 1, 0, i, 1); if (dispatch_width > i * 2) @@ -253,7 +253,7 @@ brw_emit_scan(const fs_builder &bld, enum opcode opcode, const brw_reg &tmp, static bool brw_lower_reduce(fs_visitor &s, bblock_t *block, fs_inst *inst) { - const fs_builder bld(&s, block, inst); + const brw_builder bld(&s, block, inst); assert(inst->dst.type == inst->src[0].type); brw_reg dst = inst->dst; @@ -305,7 +305,7 @@ brw_lower_reduce(fs_visitor &s, bblock_t *block, fs_inst *inst) static bool brw_lower_scan(fs_visitor &s, bblock_t *block, fs_inst *inst) { - const fs_builder bld(&s, block, inst); + const brw_builder bld(&s, block, inst); assert(inst->dst.type == inst->src[0].type); brw_reg dst = inst->dst; @@ -320,7 +320,7 @@ brw_lower_scan(fs_visitor &s, bblock_t *block, fs_inst *inst) * to reduction operation's identity value. */ brw_reg scan = bld.vgrf(src.type); - const fs_builder ubld = bld.exec_all(); + const brw_builder ubld = bld.exec_all(); ubld.emit(SHADER_OPCODE_SEL_EXEC, scan, src, info.identity); if (inst->opcode == SHADER_OPCODE_EXCLUSIVE_SCAN) { @@ -346,9 +346,9 @@ brw_lower_scan(fs_visitor &s, bblock_t *block, fs_inst *inst) } static brw_reg -brw_fill_flag(const fs_builder &bld, unsigned v) +brw_fill_flag(const brw_builder &bld, unsigned v) { - const fs_builder ubld1 = bld.exec_all().group(1, 0); + const brw_builder ubld1 = bld.exec_all().group(1, 0); brw_reg flag = brw_flag_reg(0, 0); if (bld.shader->dispatch_width == 32) { @@ -363,7 +363,7 @@ brw_fill_flag(const fs_builder &bld, unsigned v) } static void -brw_lower_dispatch_width_vote(const fs_builder &bld, enum opcode opcode, brw_reg dst, brw_reg src) +brw_lower_dispatch_width_vote(const brw_builder &bld, enum opcode opcode, brw_reg dst, brw_reg src) { const intel_device_info *devinfo = bld.shader->devinfo; const unsigned dispatch_width = bld.shader->dispatch_width; @@ -393,8 +393,8 @@ brw_lower_dispatch_width_vote(const fs_builder &bld, enum opcode opcode, brw_reg * * TODO: Check if we still need this for newer platforms. */ - const fs_builder ubld = devinfo->ver >= 20 ? bld.exec_all() - : bld.exec_all().group(1, 0); + const brw_builder ubld = devinfo->ver >= 20 ? bld.exec_all() + : bld.exec_all().group(1, 0); brw_reg res1 = ubld.MOV(brw_imm_d(0)); enum brw_predicate pred; @@ -415,7 +415,7 @@ brw_lower_dispatch_width_vote(const fs_builder &bld, enum opcode opcode, brw_reg } static void -brw_lower_quad_vote_gfx9(const fs_builder &bld, enum opcode opcode, brw_reg dst, brw_reg src) +brw_lower_quad_vote_gfx9(const brw_builder &bld, enum opcode opcode, brw_reg dst, brw_reg src) { assert(opcode == SHADER_OPCODE_VOTE_ANY || opcode == SHADER_OPCODE_VOTE_ALL); const bool any = opcode == SHADER_OPCODE_VOTE_ANY; @@ -437,7 +437,7 @@ brw_lower_quad_vote_gfx9(const fs_builder &bld, enum opcode opcode, brw_reg dst, } static void -brw_lower_quad_vote_gfx20(const fs_builder &bld, enum opcode opcode, brw_reg dst, brw_reg src) +brw_lower_quad_vote_gfx20(const brw_builder &bld, enum opcode opcode, brw_reg dst, brw_reg src) { assert(opcode == SHADER_OPCODE_VOTE_ANY || opcode == SHADER_OPCODE_VOTE_ALL); const bool any = opcode == SHADER_OPCODE_VOTE_ANY; @@ -484,7 +484,7 @@ brw_lower_quad_vote_gfx20(const fs_builder &bld, enum opcode opcode, brw_reg dst static bool brw_lower_vote(fs_visitor &s, bblock_t *block, fs_inst *inst) { - const fs_builder bld(&s, block, inst); + const brw_builder bld(&s, block, inst); brw_reg dst = inst->dst; brw_reg src = inst->src[0]; @@ -514,12 +514,12 @@ brw_lower_vote(fs_visitor &s, bblock_t *block, fs_inst *inst) static bool brw_lower_ballot(fs_visitor &s, bblock_t *block, fs_inst *inst) { - const fs_builder bld(&s, block, inst); + const brw_builder bld(&s, block, inst); brw_reg value = retype(inst->src[0], BRW_TYPE_UD); brw_reg dst = inst->dst; - const fs_builder xbld = dst.is_scalar ? bld.scalar_group() : bld; + const brw_builder xbld = dst.is_scalar ? bld.scalar_group() : bld; if (value.file == IMM) { /* Implement a fast-path for ballot(true). */ @@ -544,7 +544,7 @@ brw_lower_ballot(fs_visitor &s, bblock_t *block, fs_inst *inst) static bool brw_lower_quad_swap(fs_visitor &s, bblock_t *block, fs_inst *inst) { - const fs_builder bld(&s, block, inst); + const brw_builder bld(&s, block, inst); assert(inst->dst.type == inst->src[0].type); brw_reg dst = inst->dst; @@ -557,7 +557,7 @@ brw_lower_quad_swap(fs_visitor &s, bblock_t *block, fs_inst *inst) case BRW_SWAP_HORIZONTAL: { const brw_reg tmp = bld.vgrf(value.type); - const fs_builder ubld = bld.exec_all().group(s.dispatch_width / 2, 0); + const brw_builder ubld = bld.exec_all().group(s.dispatch_width / 2, 0); const brw_reg src_left = horiz_stride(value, 2); const brw_reg src_right = horiz_stride(horiz_offset(value, 1), 2); @@ -577,7 +577,7 @@ brw_lower_quad_swap(fs_visitor &s, bblock_t *block, fs_inst *inst) const unsigned swizzle = dir == BRW_SWAP_VERTICAL ? BRW_SWIZZLE4(2,3,0,1) : BRW_SWIZZLE4(3,2,1,0); const brw_reg tmp = bld.vgrf(value.type); - const fs_builder ubld = bld.exec_all(); + const brw_builder ubld = bld.exec_all(); ubld.emit(SHADER_OPCODE_QUAD_SWIZZLE, tmp, value, brw_imm_ud(swizzle)); bld.MOV(dst, tmp); } else { @@ -600,7 +600,7 @@ brw_lower_quad_swap(fs_visitor &s, bblock_t *block, fs_inst *inst) static bool brw_lower_read_from_live_channel(fs_visitor &s, bblock_t *block, fs_inst *inst) { - const fs_builder bld(&s, block, inst); + const brw_builder bld(&s, block, inst); assert(inst->sources == 1); assert(inst->dst.type == inst->src[0].type); @@ -616,7 +616,7 @@ brw_lower_read_from_live_channel(fs_visitor &s, bblock_t *block, fs_inst *inst) static bool brw_lower_read_from_channel(fs_visitor &s, bblock_t *block, fs_inst *inst) { - const fs_builder bld(&s, block, inst); + const brw_builder bld(&s, block, inst); assert(inst->sources == 2); assert(inst->dst.type == inst->src[0].type); diff --git a/src/intel/compiler/brw_opt.cpp b/src/intel/compiler/brw_opt.cpp index 48b54d6e0d5..9027b458639 100644 --- a/src/intel/compiler/brw_opt.cpp +++ b/src/intel/compiler/brw_opt.cpp @@ -345,7 +345,7 @@ brw_opt_split_sends(fs_visitor &s) if (end <= mid) continue; - const fs_builder ibld(&s, block, lp); + const brw_builder ibld(&s, block, lp); fs_inst *lp1 = ibld.LOAD_PAYLOAD(lp->dst, &lp->src[0], mid, lp->header_size); fs_inst *lp2 = ibld.LOAD_PAYLOAD(lp->dst, &lp->src[mid], end - mid, 0); diff --git a/src/intel/compiler/brw_opt_address_reg_load.cpp b/src/intel/compiler/brw_opt_address_reg_load.cpp index 75465a02b90..4d2cc58cbd1 100644 --- a/src/intel/compiler/brw_opt_address_reg_load.cpp +++ b/src/intel/compiler/brw_opt_address_reg_load.cpp @@ -39,7 +39,7 @@ opt_address_reg_load_local(fs_visitor &s, bblock_t *block, const brw::def_analys src_inst->sources > 2) continue; - fs_builder ubld = fs_builder(&s).at(block, inst).exec_all().group(1, 0); + brw_builder ubld = brw_builder(&s).at(block, inst).exec_all().group(1, 0); brw_reg sources[3]; for (unsigned i = 0; i < src_inst->sources; i++) { sources[i] = inst->src[i].file == VGRF ? component(src_inst->src[i], 0) : src_inst->src[i]; diff --git a/src/intel/compiler/brw_opt_combine_constants.cpp b/src/intel/compiler/brw_opt_combine_constants.cpp index d082fa0c75a..33ab66e08b8 100644 --- a/src/intel/compiler/brw_opt_combine_constants.cpp +++ b/src/intel/compiler/brw_opt_combine_constants.cpp @@ -1606,7 +1606,7 @@ brw_opt_combine_constants(fs_visitor &s) * both HF slots within a DWord with the constant. */ const uint32_t width = 1; - const fs_builder ibld = fs_builder(&s, width).at(insert_block, n).exec_all(); + const brw_builder ibld = brw_builder(&s, width).at(insert_block, n).exec_all(); brw_reg reg = brw_vgrf(imm->nr, BRW_TYPE_F); reg.offset = imm->subreg_offset; diff --git a/src/intel/compiler/brw_opt_cse.cpp b/src/intel/compiler/brw_opt_cse.cpp index 6f6fb8a870a..078d0d642c5 100644 --- a/src/intel/compiler/brw_opt_cse.cpp +++ b/src/intel/compiler/brw_opt_cse.cpp @@ -379,8 +379,8 @@ remap_sources(fs_visitor &s, const brw::def_analysis &defs, */ fs_inst *def = defs.get(inst->src[i]); bblock_t *def_block = defs.get_block(inst->src[i]); - const fs_builder dbld = - fs_builder(&s, def_block, def).at(def_block, def->next); + const brw_builder dbld = + brw_builder(&s, def_block, def).at(def_block, def->next); /* Resolve any deferred block IP changes before inserting */ if (def_block->end_ip_delta) diff --git a/src/intel/compiler/brw_opt_txf_combiner.cpp b/src/intel/compiler/brw_opt_txf_combiner.cpp index 714020cbd08..da1a56146fd 100644 --- a/src/intel/compiler/brw_opt_txf_combiner.cpp +++ b/src/intel/compiler/brw_opt_txf_combiner.cpp @@ -152,9 +152,9 @@ brw_opt_combine_convergent_txf(fs_visitor &s) for (unsigned curr = 0; curr < count; curr += max_simd) { const unsigned lanes = CLAMP(count - curr, min_simd, max_simd); const unsigned width = util_next_power_of_two(lanes); - const fs_builder ubld = - fs_builder(&s).at(block, txfs[curr]).exec_all().group(width, 0); - const fs_builder ubld1 = ubld.group(1, 0); + const brw_builder ubld = + brw_builder(&s).at(block, txfs[curr]).exec_all().group(width, 0); + const brw_builder ubld1 = ubld.group(1, 0); enum brw_reg_type coord_type = txfs[curr]->src[TEX_LOGICAL_SRC_COORDINATE].type; @@ -211,7 +211,7 @@ brw_opt_combine_convergent_txf(fs_visitor &s) if (!txf) break; - const fs_builder ibld = fs_builder(&s, block, txf); + const brw_builder ibld = brw_builder(&s, block, txf); /* Replace each of the original TXFs with MOVs from our new one */ const unsigned dest_comps = dest_comps_for_txf(s, txf); diff --git a/src/intel/compiler/brw_opt_virtual_grfs.cpp b/src/intel/compiler/brw_opt_virtual_grfs.cpp index 6129a6916bc..6e203a01ac6 100644 --- a/src/intel/compiler/brw_opt_virtual_grfs.cpp +++ b/src/intel/compiler/brw_opt_virtual_grfs.cpp @@ -145,7 +145,7 @@ brw_opt_split_virtual_grfs(fs_visitor &s) if (inst->opcode == SHADER_OPCODE_UNDEF) { assert(inst->dst.file == VGRF); if (vgrf_has_split[inst->dst.nr]) { - const fs_builder ibld(&s, block, inst); + const brw_builder ibld(&s, block, inst); assert(inst->size_written % REG_SIZE == 0); unsigned reg_offset = inst->dst.offset / REG_SIZE; unsigned size_written = 0; diff --git a/src/intel/compiler/brw_workaround.cpp b/src/intel/compiler/brw_workaround.cpp index fdb004d0ce6..75bbf578459 100644 --- a/src/intel/compiler/brw_workaround.cpp +++ b/src/intel/compiler/brw_workaround.cpp @@ -30,8 +30,8 @@ brw_workaround_emit_dummy_mov_instruction(fs_visitor &s) return false; /* Insert dummy mov as first instruction. */ - const fs_builder ubld = - fs_builder(&s, s.cfg->first_block(), (fs_inst *)first_inst).exec_all().group(8, 0); + const brw_builder ubld = + brw_builder(&s, s.cfg->first_block(), (fs_inst *)first_inst).exec_all().group(8, 0); ubld.MOV(ubld.null_reg_ud(), brw_imm_ud(0u)); s.invalidate_analysis(DEPENDENCY_INSTRUCTIONS | DEPENDENCY_VARIABLES); @@ -100,8 +100,8 @@ brw_workaround_memory_fence_before_eot(fs_visitor &s) if (!has_ugm_write_or_atomic) break; - const fs_builder ibld(&s, block, inst); - const fs_builder ubld = ibld.exec_all().group(1, 0); + const brw_builder ibld(&s, block, inst); + const brw_builder ubld = ibld.exec_all().group(1, 0); brw_reg dst = ubld.vgrf(BRW_TYPE_UD); fs_inst *dummy_fence = ubld.emit(SHADER_OPCODE_MEMORY_FENCE, @@ -228,7 +228,7 @@ brw_workaround_nomask_control_flow(fs_visitor &s) * instruction), in order to avoid getting a right-shifted * value. */ - const fs_builder ubld = fs_builder(&s, block, inst) + const brw_builder ubld = brw_builder(&s, block, inst) .exec_all().group(s.dispatch_width, 0); const brw_reg flag = retype(brw_flag_reg(0, 0), BRW_TYPE_UD); @@ -343,8 +343,8 @@ brw_workaround_source_arf_before_eot(fs_visitor &s) */ assert(++eot_count == 1); - const fs_builder ibld(&s, block, inst); - const fs_builder ubld = ibld.exec_all().group(1, 0); + const brw_builder ibld(&s, block, inst); + const brw_builder ubld = ibld.exec_all().group(1, 0); if (flags_unread & 0x0f) ubld.MOV(ubld.null_reg_ud(), retype(brw_flag_reg(0, 0), BRW_TYPE_UD)); diff --git a/src/intel/compiler/test_lower_scoreboard.cpp b/src/intel/compiler/test_lower_scoreboard.cpp index f2b4944de69..ca18f0d91b6 100644 --- a/src/intel/compiler/test_lower_scoreboard.cpp +++ b/src/intel/compiler/test_lower_scoreboard.cpp @@ -40,7 +40,7 @@ protected: struct brw_wm_prog_data *prog_data; struct gl_shader_program *shader_prog; fs_visitor *v; - fs_builder bld; + brw_builder bld; }; scoreboard_test::scoreboard_test() @@ -65,7 +65,7 @@ scoreboard_test::scoreboard_test() v = new fs_visitor(compiler, ¶ms, NULL, &prog_data->base, shader, 8, false, false); - bld = fs_builder(v).at_end(); + bld = brw_builder(v).at_end(); } scoreboard_test::~scoreboard_test() @@ -106,7 +106,7 @@ lower_scoreboard(fs_visitor *v) } fs_inst * -emit_SEND(const fs_builder &bld, const brw_reg &dst, +emit_SEND(const brw_builder &bld, const brw_reg &dst, const brw_reg &desc, const brw_reg &payload) { fs_inst *inst = bld.emit(SHADER_OPCODE_SEND, dst, desc, desc, payload); diff --git a/src/intel/compiler/test_opt_cmod_propagation.cpp b/src/intel/compiler/test_opt_cmod_propagation.cpp index 2ecb7e484ba..0e796a3caa8 100644 --- a/src/intel/compiler/test_opt_cmod_propagation.cpp +++ b/src/intel/compiler/test_opt_cmod_propagation.cpp @@ -40,7 +40,7 @@ protected: struct brw_wm_prog_data *prog_data; struct gl_shader_program *shader_prog; fs_visitor *v; - fs_builder bld; + brw_builder bld; void test_mov_prop(enum brw_conditional_mod cmod, enum brw_reg_type add_type, @@ -72,7 +72,7 @@ cmod_propagation_test::cmod_propagation_test() v = new fs_visitor(compiler, ¶ms, NULL, &prog_data->base, shader, 8, false, false); - bld = fs_builder(v).at_end(); + bld = brw_builder(v).at_end(); devinfo->ver = 9; devinfo->verx10 = devinfo->ver * 10; diff --git a/src/intel/compiler/test_opt_combine_constants.cpp b/src/intel/compiler/test_opt_combine_constants.cpp index fa6947775a7..fc6b63b3009 100644 --- a/src/intel/compiler/test_opt_combine_constants.cpp +++ b/src/intel/compiler/test_opt_combine_constants.cpp @@ -67,15 +67,15 @@ struct FSCombineConstantsTest : public ::testing::Test { } }; -static fs_builder +static brw_builder make_builder(fs_visitor *s) { - return fs_builder(s, s->dispatch_width).at_end(); + return brw_builder(s, s->dispatch_width).at_end(); } TEST_F(FSCombineConstantsTest, Simple) { - fs_builder bld = make_builder(shader); + brw_builder bld = make_builder(shader); brw_reg r = brw_vec8_grf(1, 0); brw_reg imm_a = brw_imm_ud(1); @@ -100,7 +100,7 @@ TEST_F(FSCombineConstantsTest, Simple) TEST_F(FSCombineConstantsTest, DoContainingDo) { - fs_builder bld = make_builder(shader); + brw_builder bld = make_builder(shader); brw_reg r1 = brw_vec8_grf(1, 0); brw_reg r2 = brw_vec8_grf(2, 0); diff --git a/src/intel/compiler/test_opt_copy_propagation.cpp b/src/intel/compiler/test_opt_copy_propagation.cpp index efa2182f8c4..177e829b090 100644 --- a/src/intel/compiler/test_opt_copy_propagation.cpp +++ b/src/intel/compiler/test_opt_copy_propagation.cpp @@ -40,7 +40,7 @@ protected: struct brw_wm_prog_data *prog_data; struct gl_shader_program *shader_prog; fs_visitor *v; - fs_builder bld; + brw_builder bld; }; copy_propagation_test::copy_propagation_test() @@ -61,7 +61,7 @@ copy_propagation_test::copy_propagation_test() v = new fs_visitor(compiler, ¶ms, NULL, &prog_data->base, shader, 8, false, false); - bld = fs_builder(v).at_end(); + bld = brw_builder(v).at_end(); devinfo->ver = 9; devinfo->verx10 = devinfo->ver * 10; diff --git a/src/intel/compiler/test_opt_cse.cpp b/src/intel/compiler/test_opt_cse.cpp index 1cac79909ae..f163515c8b7 100644 --- a/src/intel/compiler/test_opt_cse.cpp +++ b/src/intel/compiler/test_opt_cse.cpp @@ -22,7 +22,7 @@ protected: struct brw_wm_prog_data *prog_data; struct gl_shader_program *shader_prog; fs_visitor *v; - fs_builder bld; + brw_builder bld; }; cse_test::cse_test() @@ -43,7 +43,7 @@ cse_test::cse_test() v = new fs_visitor(compiler, ¶ms, NULL, &prog_data->base, shader, 16, false, false); - bld = fs_builder(v).at_end(); + bld = brw_builder(v).at_end(); devinfo->verx10 = 125; devinfo->ver = devinfo->verx10 / 10; diff --git a/src/intel/compiler/test_opt_saturate_propagation.cpp b/src/intel/compiler/test_opt_saturate_propagation.cpp index 7031dd8e591..fc034e9a439 100644 --- a/src/intel/compiler/test_opt_saturate_propagation.cpp +++ b/src/intel/compiler/test_opt_saturate_propagation.cpp @@ -40,7 +40,7 @@ protected: struct brw_wm_prog_data *prog_data; struct gl_shader_program *shader_prog; fs_visitor *v; - fs_builder bld; + brw_builder bld; }; saturate_propagation_test::saturate_propagation_test() @@ -61,7 +61,7 @@ saturate_propagation_test::saturate_propagation_test() v = new fs_visitor(compiler, ¶ms, NULL, &prog_data->base, shader, 16, false, false); - bld = fs_builder(v).at_end(); + bld = brw_builder(v).at_end(); devinfo->ver = 9; devinfo->verx10 = devinfo->ver * 10;