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i965: Split register allocation out of the ever-growing brw_fs.cpp.
This commit is contained in:
Eric Anholt
parent
3f5fde5c45
commit
5ac6c4ecfe
3 changed files with 266 additions and 216 deletions
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@ -108,6 +108,7 @@ CXX_SOURCES = \
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brw_cubemap_normalize.cpp \
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brw_fs.cpp \
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brw_fs_channel_expressions.cpp \
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brw_fs_reg_allocate.cpp \
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brw_fs_vector_splitting.cpp
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ASM_SOURCES =
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@ -2311,222 +2311,6 @@ fs_visitor::assign_urb_setup()
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this->first_non_payload_grf = urb_start + c->prog_data.urb_read_length;
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}
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static void
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assign_reg(int *reg_hw_locations, fs_reg *reg)
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{
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if (reg->file == GRF && reg->reg != 0) {
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assert(reg->reg_offset >= 0);
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reg->hw_reg = reg_hw_locations[reg->reg] + reg->reg_offset;
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reg->reg = 0;
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}
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}
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void
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fs_visitor::assign_regs_trivial()
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{
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int last_grf = 0;
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int hw_reg_mapping[this->virtual_grf_next];
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int i;
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hw_reg_mapping[0] = 0;
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hw_reg_mapping[1] = this->first_non_payload_grf;
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for (i = 2; i < this->virtual_grf_next; i++) {
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hw_reg_mapping[i] = (hw_reg_mapping[i - 1] +
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this->virtual_grf_sizes[i - 1]);
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}
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last_grf = hw_reg_mapping[i - 1] + this->virtual_grf_sizes[i - 1];
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foreach_iter(exec_list_iterator, iter, this->instructions) {
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fs_inst *inst = (fs_inst *)iter.get();
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assign_reg(hw_reg_mapping, &inst->dst);
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assign_reg(hw_reg_mapping, &inst->src[0]);
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assign_reg(hw_reg_mapping, &inst->src[1]);
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}
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this->grf_used = last_grf + 1;
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}
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void
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fs_visitor::assign_regs()
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{
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int last_grf = 0;
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int hw_reg_mapping[this->virtual_grf_next + 1];
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int base_reg_count = BRW_MAX_GRF - this->first_non_payload_grf;
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int class_sizes[base_reg_count];
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int class_count = 0;
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int aligned_pair_class = -1;
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/* Set up the register classes.
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*
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* The base registers store a scalar value. For texture samples,
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* we get virtual GRFs composed of 4 contiguous hw register. For
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* structures and arrays, we store them as contiguous larger things
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* than that, though we should be able to do better most of the
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* time.
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*/
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class_sizes[class_count++] = 1;
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if (brw->has_pln && intel->gen < 6) {
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/* Always set up the (unaligned) pairs for gen5, so we can find
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* them for making the aligned pair class.
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*/
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class_sizes[class_count++] = 2;
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}
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for (int r = 1; r < this->virtual_grf_next; r++) {
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int i;
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for (i = 0; i < class_count; i++) {
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if (class_sizes[i] == this->virtual_grf_sizes[r])
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break;
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}
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if (i == class_count) {
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if (this->virtual_grf_sizes[r] >= base_reg_count) {
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fprintf(stderr, "Object too large to register allocate.\n");
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this->fail = true;
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}
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class_sizes[class_count++] = this->virtual_grf_sizes[r];
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}
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}
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int ra_reg_count = 0;
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int class_base_reg[class_count];
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int class_reg_count[class_count];
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int classes[class_count + 1];
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for (int i = 0; i < class_count; i++) {
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class_base_reg[i] = ra_reg_count;
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class_reg_count[i] = base_reg_count - (class_sizes[i] - 1);
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ra_reg_count += class_reg_count[i];
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}
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struct ra_regs *regs = ra_alloc_reg_set(ra_reg_count);
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for (int i = 0; i < class_count; i++) {
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classes[i] = ra_alloc_reg_class(regs);
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for (int i_r = 0; i_r < class_reg_count[i]; i_r++) {
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ra_class_add_reg(regs, classes[i], class_base_reg[i] + i_r);
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}
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/* Add conflicts between our contiguous registers aliasing
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* base regs and other register classes' contiguous registers
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* that alias base regs, or the base regs themselves for classes[0].
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*/
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for (int c = 0; c <= i; c++) {
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for (int i_r = 0; i_r < class_reg_count[i]; i_r++) {
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for (int c_r = MAX2(0, i_r - (class_sizes[c] - 1));
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c_r < MIN2(class_reg_count[c], i_r + class_sizes[i]);
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c_r++) {
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if (0) {
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printf("%d/%d conflicts %d/%d\n",
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class_sizes[i], this->first_non_payload_grf + i_r,
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class_sizes[c], this->first_non_payload_grf + c_r);
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}
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ra_add_reg_conflict(regs,
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class_base_reg[i] + i_r,
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class_base_reg[c] + c_r);
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}
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}
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}
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}
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/* Add a special class for aligned pairs, which we'll put delta_x/y
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* in on gen5 so that we can do PLN.
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*/
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if (brw->has_pln && intel->gen < 6) {
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int reg_count = (base_reg_count - 1) / 2;
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int unaligned_pair_class = 1;
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assert(class_sizes[unaligned_pair_class] == 2);
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aligned_pair_class = class_count;
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classes[aligned_pair_class] = ra_alloc_reg_class(regs);
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class_sizes[aligned_pair_class] = 2;
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class_base_reg[aligned_pair_class] = 0;
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class_reg_count[aligned_pair_class] = 0;
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int start = (this->first_non_payload_grf & 1) ? 1 : 0;
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for (int i = 0; i < reg_count; i++) {
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ra_class_add_reg(regs, classes[aligned_pair_class],
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class_base_reg[unaligned_pair_class] + i * 2 + start);
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}
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class_count++;
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}
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ra_set_finalize(regs);
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struct ra_graph *g = ra_alloc_interference_graph(regs,
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this->virtual_grf_next);
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/* Node 0 is just a placeholder to keep virtual_grf[] mapping 1:1
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* with nodes.
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*/
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ra_set_node_class(g, 0, classes[0]);
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for (int i = 1; i < this->virtual_grf_next; i++) {
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for (int c = 0; c < class_count; c++) {
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if (class_sizes[c] == this->virtual_grf_sizes[i]) {
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if (aligned_pair_class >= 0 &&
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this->delta_x.reg == i) {
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ra_set_node_class(g, i, classes[aligned_pair_class]);
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} else {
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ra_set_node_class(g, i, classes[c]);
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}
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break;
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}
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}
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for (int j = 1; j < i; j++) {
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if (virtual_grf_interferes(i, j)) {
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ra_add_node_interference(g, i, j);
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}
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}
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}
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/* FINISHME: Handle spilling */
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if (!ra_allocate_no_spills(g)) {
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fprintf(stderr, "Failed to allocate registers.\n");
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this->fail = true;
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return;
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}
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/* Get the chosen virtual registers for each node, and map virtual
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* regs in the register classes back down to real hardware reg
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* numbers.
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*/
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hw_reg_mapping[0] = 0; /* unused */
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for (int i = 1; i < this->virtual_grf_next; i++) {
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int reg = ra_get_node_reg(g, i);
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int hw_reg = -1;
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for (int c = 0; c < class_count; c++) {
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if (reg >= class_base_reg[c] &&
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reg < class_base_reg[c] + class_reg_count[c]) {
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hw_reg = reg - class_base_reg[c];
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break;
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}
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}
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assert(hw_reg >= 0);
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hw_reg_mapping[i] = this->first_non_payload_grf + hw_reg;
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last_grf = MAX2(last_grf,
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hw_reg_mapping[i] + this->virtual_grf_sizes[i] - 1);
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}
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foreach_iter(exec_list_iterator, iter, this->instructions) {
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fs_inst *inst = (fs_inst *)iter.get();
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assign_reg(hw_reg_mapping, &inst->dst);
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assign_reg(hw_reg_mapping, &inst->src[0]);
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assign_reg(hw_reg_mapping, &inst->src[1]);
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}
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this->grf_used = last_grf + 1;
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talloc_free(g);
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talloc_free(regs);
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}
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/**
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* Split large virtual GRFs into separate components if we can.
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*
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265
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
Normal file
265
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
Normal file
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@ -0,0 +1,265 @@
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/*
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* Copyright © 2010 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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*
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*/
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extern "C" {
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#include <sys/types.h>
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#include "main/macros.h"
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#include "main/shaderobj.h"
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#include "main/uniforms.h"
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#include "program/prog_parameter.h"
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#include "program/prog_print.h"
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#include "program/prog_optimize.h"
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#include "program/register_allocate.h"
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#include "program/sampler.h"
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#include "program/hash_table.h"
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#include "brw_context.h"
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#include "brw_eu.h"
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#include "brw_wm.h"
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#include "talloc.h"
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}
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#include "brw_fs.h"
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#include "../glsl/glsl_types.h"
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#include "../glsl/ir_optimization.h"
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#include "../glsl/ir_print_visitor.h"
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static void
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assign_reg(int *reg_hw_locations, fs_reg *reg)
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{
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if (reg->file == GRF && reg->reg != 0) {
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assert(reg->reg_offset >= 0);
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reg->hw_reg = reg_hw_locations[reg->reg] + reg->reg_offset;
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reg->reg = 0;
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}
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}
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void
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fs_visitor::assign_regs_trivial()
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{
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int last_grf = 0;
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int hw_reg_mapping[this->virtual_grf_next];
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int i;
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hw_reg_mapping[0] = 0;
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hw_reg_mapping[1] = this->first_non_payload_grf;
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for (i = 2; i < this->virtual_grf_next; i++) {
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hw_reg_mapping[i] = (hw_reg_mapping[i - 1] +
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this->virtual_grf_sizes[i - 1]);
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}
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last_grf = hw_reg_mapping[i - 1] + this->virtual_grf_sizes[i - 1];
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foreach_iter(exec_list_iterator, iter, this->instructions) {
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fs_inst *inst = (fs_inst *)iter.get();
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assign_reg(hw_reg_mapping, &inst->dst);
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assign_reg(hw_reg_mapping, &inst->src[0]);
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assign_reg(hw_reg_mapping, &inst->src[1]);
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}
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this->grf_used = last_grf + 1;
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}
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void
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fs_visitor::assign_regs()
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{
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int last_grf = 0;
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int hw_reg_mapping[this->virtual_grf_next + 1];
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int base_reg_count = BRW_MAX_GRF - this->first_non_payload_grf;
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int class_sizes[base_reg_count];
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int class_count = 0;
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int aligned_pair_class = -1;
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/* Set up the register classes.
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*
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* The base registers store a scalar value. For texture samples,
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* we get virtual GRFs composed of 4 contiguous hw register. For
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* structures and arrays, we store them as contiguous larger things
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* than that, though we should be able to do better most of the
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* time.
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*/
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class_sizes[class_count++] = 1;
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if (brw->has_pln && intel->gen < 6) {
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/* Always set up the (unaligned) pairs for gen5, so we can find
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* them for making the aligned pair class.
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*/
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class_sizes[class_count++] = 2;
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}
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for (int r = 1; r < this->virtual_grf_next; r++) {
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int i;
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for (i = 0; i < class_count; i++) {
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if (class_sizes[i] == this->virtual_grf_sizes[r])
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break;
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}
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if (i == class_count) {
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if (this->virtual_grf_sizes[r] >= base_reg_count) {
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fprintf(stderr, "Object too large to register allocate.\n");
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this->fail = true;
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}
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class_sizes[class_count++] = this->virtual_grf_sizes[r];
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}
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}
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int ra_reg_count = 0;
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int class_base_reg[class_count];
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int class_reg_count[class_count];
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int classes[class_count + 1];
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for (int i = 0; i < class_count; i++) {
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class_base_reg[i] = ra_reg_count;
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class_reg_count[i] = base_reg_count - (class_sizes[i] - 1);
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ra_reg_count += class_reg_count[i];
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}
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struct ra_regs *regs = ra_alloc_reg_set(ra_reg_count);
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for (int i = 0; i < class_count; i++) {
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classes[i] = ra_alloc_reg_class(regs);
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for (int i_r = 0; i_r < class_reg_count[i]; i_r++) {
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ra_class_add_reg(regs, classes[i], class_base_reg[i] + i_r);
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}
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/* Add conflicts between our contiguous registers aliasing
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* base regs and other register classes' contiguous registers
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* that alias base regs, or the base regs themselves for classes[0].
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*/
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for (int c = 0; c <= i; c++) {
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for (int i_r = 0; i_r < class_reg_count[i]; i_r++) {
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for (int c_r = MAX2(0, i_r - (class_sizes[c] - 1));
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c_r < MIN2(class_reg_count[c], i_r + class_sizes[i]);
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c_r++) {
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if (0) {
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printf("%d/%d conflicts %d/%d\n",
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class_sizes[i], this->first_non_payload_grf + i_r,
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class_sizes[c], this->first_non_payload_grf + c_r);
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}
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ra_add_reg_conflict(regs,
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class_base_reg[i] + i_r,
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class_base_reg[c] + c_r);
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}
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}
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}
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}
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/* Add a special class for aligned pairs, which we'll put delta_x/y
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* in on gen5 so that we can do PLN.
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*/
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if (brw->has_pln && intel->gen < 6) {
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int reg_count = (base_reg_count - 1) / 2;
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int unaligned_pair_class = 1;
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assert(class_sizes[unaligned_pair_class] == 2);
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aligned_pair_class = class_count;
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classes[aligned_pair_class] = ra_alloc_reg_class(regs);
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class_sizes[aligned_pair_class] = 2;
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class_base_reg[aligned_pair_class] = 0;
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class_reg_count[aligned_pair_class] = 0;
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int start = (this->first_non_payload_grf & 1) ? 1 : 0;
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for (int i = 0; i < reg_count; i++) {
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ra_class_add_reg(regs, classes[aligned_pair_class],
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class_base_reg[unaligned_pair_class] + i * 2 + start);
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}
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class_count++;
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}
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ra_set_finalize(regs);
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struct ra_graph *g = ra_alloc_interference_graph(regs,
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this->virtual_grf_next);
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/* Node 0 is just a placeholder to keep virtual_grf[] mapping 1:1
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* with nodes.
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*/
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ra_set_node_class(g, 0, classes[0]);
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for (int i = 1; i < this->virtual_grf_next; i++) {
|
||||
for (int c = 0; c < class_count; c++) {
|
||||
if (class_sizes[c] == this->virtual_grf_sizes[i]) {
|
||||
if (aligned_pair_class >= 0 &&
|
||||
this->delta_x.reg == i) {
|
||||
ra_set_node_class(g, i, classes[aligned_pair_class]);
|
||||
} else {
|
||||
ra_set_node_class(g, i, classes[c]);
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
for (int j = 1; j < i; j++) {
|
||||
if (virtual_grf_interferes(i, j)) {
|
||||
ra_add_node_interference(g, i, j);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* FINISHME: Handle spilling */
|
||||
if (!ra_allocate_no_spills(g)) {
|
||||
fprintf(stderr, "Failed to allocate registers.\n");
|
||||
this->fail = true;
|
||||
return;
|
||||
}
|
||||
|
||||
/* Get the chosen virtual registers for each node, and map virtual
|
||||
* regs in the register classes back down to real hardware reg
|
||||
* numbers.
|
||||
*/
|
||||
hw_reg_mapping[0] = 0; /* unused */
|
||||
for (int i = 1; i < this->virtual_grf_next; i++) {
|
||||
int reg = ra_get_node_reg(g, i);
|
||||
int hw_reg = -1;
|
||||
|
||||
for (int c = 0; c < class_count; c++) {
|
||||
if (reg >= class_base_reg[c] &&
|
||||
reg < class_base_reg[c] + class_reg_count[c]) {
|
||||
hw_reg = reg - class_base_reg[c];
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
assert(hw_reg >= 0);
|
||||
hw_reg_mapping[i] = this->first_non_payload_grf + hw_reg;
|
||||
last_grf = MAX2(last_grf,
|
||||
hw_reg_mapping[i] + this->virtual_grf_sizes[i] - 1);
|
||||
}
|
||||
|
||||
foreach_iter(exec_list_iterator, iter, this->instructions) {
|
||||
fs_inst *inst = (fs_inst *)iter.get();
|
||||
|
||||
assign_reg(hw_reg_mapping, &inst->dst);
|
||||
assign_reg(hw_reg_mapping, &inst->src[0]);
|
||||
assign_reg(hw_reg_mapping, &inst->src[1]);
|
||||
}
|
||||
|
||||
this->grf_used = last_grf + 1;
|
||||
|
||||
talloc_free(g);
|
||||
talloc_free(regs);
|
||||
}
|
||||
Loading…
Add table
Reference in a new issue