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i965: Do not generate D16 B5G6R5_UNORM configs on gen < 8

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We don't support MESA_FORMAT_Z_UNORM16 before Gen8, see
intel_screen_init_surface_formats.

As a consequence disables B5G6R5_UNORM configs with depth
on gen < 6.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2275
CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3206>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3206>
(cherry picked from commit 5bfd363be4)
This commit is contained in:
Danylo Piliaiev 2019-12-24 14:19:24 +02:00 • committed by Dylan Baker
parent 5adcb0a62a
commit 5a7ae6be76
2 changed files with 24 additions and 12 deletions
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2
.pick_status.json
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@ -40,7 +40,7 @@
"description": "i965: Do not generate D16 B5G6R5_UNORM configs on gen < 8",
"nominated": true,
"nomination_type": 0,
"resolution": 0,
"resolution": 1,
"master_sha": null,
"because_sha": null
},

34
src/mesa/drivers/dri/i965/intel_screen.c
View file

@ -2281,7 +2281,7 @@ intel_screen_make_configs(__DRIscreen *dri_screen)
*/
for (unsigned i = 0; i < num_formats; i++) {
__DRIconfig **new_configs;
int num_depth_stencil_bits = 2;
int num_depth_stencil_bits = 1;
if (!intel_allowed_format(dri_screen, formats[i]))
continue;
@ -2294,16 +2294,20 @@ intel_screen_make_configs(__DRIscreen *dri_screen)
stencil_bits[0] = 0;
if (formats[i] == MESA_FORMAT_B5G6R5_UNORM) {
depth_bits[1] = 16;
stencil_bits[1] = 0;
if (devinfo->gen >= 8) {
depth_bits[num_depth_stencil_bits] = 16;
stencil_bits[num_depth_stencil_bits] = 0;
num_depth_stencil_bits++;
}
if (devinfo->gen >= 6) {
depth_bits[2] = 24;
stencil_bits[2] = 8;
num_depth_stencil_bits = 3;
depth_bits[num_depth_stencil_bits] = 24;
stencil_bits[num_depth_stencil_bits] = 8;
num_depth_stencil_bits++;
}
} else {
depth_bits[1] = 24;
stencil_bits[1] = 8;
depth_bits[num_depth_stencil_bits] = 24;
stencil_bits[num_depth_stencil_bits] = 8;
num_depth_stencil_bits++;
}
new_configs = driCreateConfigs(formats[i],
@ -2327,8 +2331,16 @@ intel_screen_make_configs(__DRIscreen *dri_screen)
continue;
if (formats[i] == MESA_FORMAT_B5G6R5_UNORM) {
depth_bits[0] = 16;
stencil_bits[0] = 0;
if (devinfo->gen >= 8) {
depth_bits[0] = 16;
stencil_bits[0] = 0;
} else if (devinfo->gen >= 6) {
depth_bits[0] = 24;
stencil_bits[0] = 8;
} else {
depth_bits[0] = 0;
stencil_bits[0] = 0;
}
} else {
depth_bits[0] = 24;
stencil_bits[0] = 8;
@ -2370,7 +2382,7 @@ intel_screen_make_configs(__DRIscreen *dri_screen)
depth_bits[0] = 0;
stencil_bits[0] = 0;
if (formats[i] == MESA_FORMAT_B5G6R5_UNORM) {
if (formats[i] == MESA_FORMAT_B5G6R5_UNORM && devinfo->gen >= 8) {
depth_bits[1] = 16;
stencil_bits[1] = 0;
} else {