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Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestline

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This commit is contained in:
Nian Wu 2007-03-12 09:03:27 +08:00
commit 5a5b55943d
33 changed files with 979 additions and 425 deletions
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3
src/mesa/drivers/dri/i915tex/Makefile
View file

@ -60,7 +60,8 @@ C_SOURCES = \
ASM_SOURCES =
DRIVER_DEFINES = -I../intel
DRIVER_DEFINES = -I../intel $(shell pkg-config libdrm --atleast-version=2.3.1 \
&& echo "-DDRM_VBLANK_FLIP=DRM_VBLANK_FLIP")
include ../Makefile.template

11
src/mesa/drivers/dri/i915tex/i915_tex_layout.c
View file

@ -190,6 +190,9 @@ i945_miptree_layout(struct intel_mipmap_tree * mt)
case GL_TEXTURE_CUBE_MAP:{
const GLuint dim = mt->width0;
GLuint face;
GLuint lvlWidth = mt->width0, lvlHeight = mt->height0;
assert(lvlWidth == lvlHeight); /* cubemap images are square */
/* Depending on the size of the largest images, pitch can be
* determined either by the old-style packing of cubemap faces,
@ -204,11 +207,13 @@ i945_miptree_layout(struct intel_mipmap_tree * mt)
/* Set all the levels to effectively occupy the whole rectangular region.
*/
for (level = mt->first_level; level <= mt->last_level; level++)
for (level = mt->first_level; level <= mt->last_level; level++) {
intel_miptree_set_level_info(mt, level, 6,
0, 0,
mt->pitch, mt->total_height, 1);
lvlWidth, lvlHeight, 1);
lvlWidth /= 2;
lvlHeight /= 2;
}
for (face = 0; face < 6; face++) {

257
src/mesa/drivers/dri/i915tex/intel_blit.c
View file

@ -55,8 +55,6 @@ intelCopyBuffer(const __DRIdrawablePrivate * dPriv,
struct intel_context *intel;
const intelScreenPrivate *intelScreen;
GLboolean missed_target;
int64_t ust;
DBG("%s\n", __FUNCTION__);
@ -68,41 +66,6 @@ intelCopyBuffer(const __DRIdrawablePrivate * dPriv,
intelScreen = intel->intelScreen;
if (!rect && !intel->swap_scheduled && intelScreen->drmMinor >= 6 &&
!(intel->vblank_flags & VBLANK_FLAG_NO_IRQ) &&
intelScreen->current_rotation == 0) {
unsigned int interval = driGetVBlankInterval(dPriv, intel->vblank_flags);
unsigned int target;
drm_i915_vblank_swap_t swap;
swap.drawable = dPriv->hHWDrawable;
swap.seqtype = DRM_VBLANK_ABSOLUTE;
target = swap.sequence = intel->vbl_seq + interval;
if (intel->vblank_flags & VBLANK_FLAG_SYNC) {
swap.seqtype |= DRM_VBLANK_NEXTONMISS;
} else if (interval == 0) {
goto noschedule;
}
if ( intel->vblank_flags & VBLANK_FLAG_SECONDARY ) {
swap.seqtype |= DRM_VBLANK_SECONDARY;
}
intel_batchbuffer_flush(intel->batch);
if (!drmCommandWriteRead(intel->driFd, DRM_I915_VBLANK_SWAP, &swap,
sizeof(swap))) {
intel->swap_scheduled = 1;
intel->vbl_seq = swap.sequence;
swap.sequence -= target;
missed_target = swap.sequence > 0 && swap.sequence <= (1 << 23);
}
} else {
intel->swap_scheduled = 0;
}
noschedule:
if (intel->last_swap_fence) {
driFenceFinish(intel->last_swap_fence, DRM_FENCE_TYPE_EXE, GL_TRUE);
driFenceUnReference(intel->last_swap_fence);
@ -111,122 +74,88 @@ noschedule:
intel->last_swap_fence = intel->first_swap_fence;
intel->first_swap_fence = NULL;
if (!intel->swap_scheduled) {
if (!rect) {
driWaitForVBlank(dPriv, &intel->vbl_seq, intel->vblank_flags,
&missed_target);
/* The LOCK_HARDWARE is required for the cliprects. Buffer offsets
* should work regardless.
*/
LOCK_HARDWARE(intel);
if (dPriv && dPriv->numClipRects) {
struct intel_framebuffer *intel_fb = dPriv->driverPrivate;
const struct intel_region *frontRegion
= intel_get_rb_region(&intel_fb->Base, BUFFER_FRONT_LEFT);
const struct intel_region *backRegion
= intel_get_rb_region(&intel_fb->Base, BUFFER_BACK_LEFT);
const int nbox = dPriv->numClipRects;
const drm_clip_rect_t *pbox = dPriv->pClipRects;
const int pitch = frontRegion->pitch;
const int cpp = frontRegion->cpp;
int BR13, CMD;
int i;
ASSERT(intel_fb);
ASSERT(intel_fb->Base.Name == 0); /* Not a user-created FBO */
ASSERT(frontRegion);
ASSERT(backRegion);
ASSERT(frontRegion->pitch == backRegion->pitch);
ASSERT(frontRegion->cpp == backRegion->cpp);
if (cpp == 2) {
BR13 = (pitch * cpp) | (0xCC << 16) | (1 << 24);
CMD = XY_SRC_COPY_BLT_CMD;
}
else {
BR13 = (pitch * cpp) | (0xCC << 16) | (1 << 24) | (1 << 25);
CMD = (XY_SRC_COPY_BLT_CMD | XY_SRC_COPY_BLT_WRITE_ALPHA |
XY_SRC_COPY_BLT_WRITE_RGB);
}
for (i = 0; i < nbox; i++, pbox++) {
drm_clip_rect_t box;
/* The LOCK_HARDWARE is required for the cliprects. Buffer offsets
* should work regardless.
*/
LOCK_HARDWARE(intel);
if (pbox->x1 > pbox->x2 ||
pbox->y1 > pbox->y2 ||
pbox->x2 > intelScreen->width || pbox->y2 > intelScreen->height)
continue;
if (intel->driDrawable && intel->driDrawable->numClipRects) {
const intelScreenPrivate *intelScreen = intel->intelScreen;
struct gl_framebuffer *fb
= (struct gl_framebuffer *) dPriv->driverPrivate;
const struct intel_region *frontRegion
= intel_get_rb_region(fb, BUFFER_FRONT_LEFT);
const struct intel_region *backRegion
= intel_get_rb_region(fb, BUFFER_BACK_LEFT);
const int nbox = dPriv->numClipRects;
const drm_clip_rect_t *pbox = dPriv->pClipRects;
const int pitch = frontRegion->pitch;
const int cpp = frontRegion->cpp;
int BR13, CMD;
int i;
box = *pbox;
ASSERT(fb);
ASSERT(fb->Name == 0); /* Not a user-created FBO */
ASSERT(frontRegion);
ASSERT(backRegion);
ASSERT(frontRegion->pitch == backRegion->pitch);
ASSERT(frontRegion->cpp == backRegion->cpp);
if (rect) {
if (rect->x1 > box.x1)
box.x1 = rect->x1;
if (rect->y1 > box.y1)
box.y1 = rect->y1;
if (rect->x2 < box.x2)
box.x2 = rect->x2;
if (rect->y2 < box.y2)
box.y2 = rect->y2;
if (cpp == 2) {
BR13 = (pitch * cpp) | (0xCC << 16) | (1 << 24);
CMD = XY_SRC_COPY_BLT_CMD;
}
else {
BR13 = (pitch * cpp) | (0xCC << 16) | (1 << 24) | (1 << 25);
CMD = (XY_SRC_COPY_BLT_CMD | XY_SRC_COPY_BLT_WRITE_ALPHA |
XY_SRC_COPY_BLT_WRITE_RGB);
}
for (i = 0; i < nbox; i++, pbox++) {
drm_clip_rect_t box;
if (pbox->x1 > pbox->x2 ||
pbox->y1 > pbox->y2 ||
pbox->x2 > intelScreen->width || pbox->y2 > intelScreen->height)
if (box.x1 > box.x2 || box.y1 > box.y2)
continue;
box = *pbox;
if (rect) {
if (rect->x1 > box.x1)
box.x1 = rect->x1;
if (rect->y1 > box.y1)
box.y1 = rect->y1;
if (rect->x2 < box.x2)
box.x2 = rect->x2;
if (rect->y2 < box.y2)
box.y2 = rect->y2;
if (box.x1 > box.x2 || box.y1 > box.y2)
continue;
}
BEGIN_BATCH(8, INTEL_BATCH_NO_CLIPRECTS);
OUT_BATCH(CMD);
OUT_BATCH(BR13);
OUT_BATCH((pbox->y1 << 16) | pbox->x1);
OUT_BATCH((pbox->y2 << 16) | pbox->x2);
if (intel->sarea->pf_current_page == 0)
OUT_RELOC(frontRegion->buffer,
DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
DRM_BO_MASK_MEM | DRM_BO_FLAG_WRITE, 0);
else
OUT_RELOC(backRegion->buffer,
DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
DRM_BO_MASK_MEM | DRM_BO_FLAG_WRITE, 0);
OUT_BATCH((pbox->y1 << 16) | pbox->x1);
OUT_BATCH(BR13 & 0xffff);
if (intel->sarea->pf_current_page == 0)
OUT_RELOC(backRegion->buffer,
DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
DRM_BO_MASK_MEM | DRM_BO_FLAG_READ, 0);
else
OUT_RELOC(frontRegion->buffer,
DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
DRM_BO_MASK_MEM | DRM_BO_FLAG_READ, 0);
ADVANCE_BATCH();
}
if (intel->first_swap_fence)
driFenceUnReference(intel->first_swap_fence);
intel->first_swap_fence = intel_batchbuffer_flush(intel->batch);
driFenceReference(intel->first_swap_fence);
BEGIN_BATCH(8, INTEL_BATCH_NO_CLIPRECTS);
OUT_BATCH(CMD);
OUT_BATCH(BR13);
OUT_BATCH((pbox->y1 << 16) | pbox->x1);
OUT_BATCH((pbox->y2 << 16) | pbox->x2);
OUT_RELOC(frontRegion->buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
DRM_BO_MASK_MEM | DRM_BO_FLAG_WRITE, 0);
OUT_BATCH((pbox->y1 << 16) | pbox->x1);
OUT_BATCH(BR13 & 0xffff);
OUT_RELOC(backRegion->buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
DRM_BO_MASK_MEM | DRM_BO_FLAG_READ, 0);
ADVANCE_BATCH();
}
UNLOCK_HARDWARE(intel);
if (intel->first_swap_fence)
driFenceUnReference(intel->first_swap_fence);
intel->first_swap_fence = intel_batchbuffer_flush(intel->batch);
driFenceReference(intel->first_swap_fence);
}
if (!rect) {
intel->swap_count++;
(*dri_interface->getUST) (&ust);
if (missed_target) {
intel->swap_missed_count++;
intel->swap_missed_ust = ust - intel->swap_ust;
}
intel->swap_ust = ust;
}
UNLOCK_HARDWARE(intel);
}
@ -406,6 +335,7 @@ void
intelClearWithBlit(GLcontext * ctx, GLbitfield mask)
{
struct intel_context *intel = intel_context(ctx);
struct gl_framebuffer *fb = ctx->DrawBuffer;
GLuint clear_depth;
GLbitfield skipBuffers = 0;
BATCH_LOCALS;
@ -417,7 +347,7 @@ intelClearWithBlit(GLcontext * ctx, GLbitfield mask)
*/
clear_depth = 0;
if (mask & BUFFER_BIT_DEPTH) {
clear_depth = (GLuint) (ctx->DrawBuffer->_DepthMax * ctx->Depth.Clear);
clear_depth = (GLuint) (fb->_DepthMax * ctx->Depth.Clear);
}
if (mask & BUFFER_BIT_STENCIL) {
clear_depth |= (ctx->Stencil.Clear & 0xff) << 24;
@ -440,12 +370,12 @@ intelClearWithBlit(GLcontext * ctx, GLbitfield mask)
int i;
/* Get clear bounds after locking */
cx = ctx->DrawBuffer->_Xmin;
cy = ctx->DrawBuffer->_Ymin;
cw = ctx->DrawBuffer->_Xmax - ctx->DrawBuffer->_Xmin;
ch = ctx->DrawBuffer->_Ymax - ctx->DrawBuffer->_Ymin;
cx = fb->_Xmin;
cy = fb->_Ymin;
cw = fb->_Xmax - cx;
ch = fb->_Ymax - cy;
if (intel->ctx.DrawBuffer->Name == 0) {
if (fb->Name == 0) {
/* clearing a window */
/* flip top to bottom */
@ -453,16 +383,6 @@ intelClearWithBlit(GLcontext * ctx, GLbitfield mask)
clear.y1 = intel->driDrawable->y + intel->driDrawable->h - cy - ch;
clear.x2 = clear.x1 + cw;
clear.y2 = clear.y1 + ch;
/* adjust for page flipping */
if (intel->sarea->pf_current_page == 1) {
const GLuint tmp = mask;
mask &= ~(BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_BACK_LEFT);
if (tmp & BUFFER_BIT_FRONT_LEFT)
mask |= BUFFER_BIT_BACK_LEFT;
if (tmp & BUFFER_BIT_BACK_LEFT)
mask |= BUFFER_BIT_FRONT_LEFT;
}
}
else {
/* clearing FBO */
@ -480,8 +400,7 @@ intelClearWithBlit(GLcontext * ctx, GLbitfield mask)
drm_clip_rect_t b;
GLuint buf;
GLuint clearMask = mask; /* use copy, since we modify it below */
GLboolean all = (cw == ctx->DrawBuffer->Width &&
ch == ctx->DrawBuffer->Height);
GLboolean all = (cw == fb->Width && ch == fb->Height);
if (!all) {
intel_intersect_cliprects(&b, &clear, box);
@ -499,11 +418,10 @@ intelClearWithBlit(GLcontext * ctx, GLbitfield mask)
const GLbitfield bufBit = 1 << buf;
if ((clearMask & bufBit) && !(bufBit & skipBuffers)) {
/* OK, clear this renderbuffer */
const struct intel_renderbuffer *irb
= intel_renderbuffer(ctx->DrawBuffer->
Attachment[buf].Renderbuffer);
struct intel_region *irb_region =
intel_get_rb_region(fb, buf);
struct _DriBufferObject *write_buffer =
intel_region_buffer(intel->intelScreen, irb->region,
intel_region_buffer(intel->intelScreen, irb_region,
all ? INTEL_WRITE_FULL :
INTEL_WRITE_PART);
@ -511,16 +429,15 @@ intelClearWithBlit(GLcontext * ctx, GLbitfield mask)
GLint pitch, cpp;
GLuint BR13, CMD;
ASSERT(irb);
ASSERT(irb->region);
ASSERT(irb_region);
pitch = irb->region->pitch;
cpp = irb->region->cpp;
pitch = irb_region->pitch;
cpp = irb_region->cpp;
DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
__FUNCTION__,
irb->region->buffer, (pitch * cpp),
irb->region->draw_offset,
irb_region->buffer, (pitch * cpp),
irb_region->draw_offset,
b.x1, b.y1, b.x2 - b.x1, b.y2 - b.y1);
@ -558,6 +475,8 @@ intelClearWithBlit(GLcontext * ctx, GLbitfield mask)
_mesa_debug(ctx, "hardware blit clear buf %d rb id %d\n",
buf, irb->Base.Name);
*/
intel_wait_flips(intel, INTEL_BATCH_NO_CLIPRECTS);
BEGIN_BATCH(6, INTEL_BATCH_NO_CLIPRECTS);
OUT_BATCH(CMD);
OUT_BATCH(BR13);
@ -565,7 +484,7 @@ intelClearWithBlit(GLcontext * ctx, GLbitfield mask)
OUT_BATCH((b.y2 << 16) | b.x2);
OUT_RELOC(write_buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
DRM_BO_MASK_MEM | DRM_BO_FLAG_WRITE,
irb->region->draw_offset);
irb_region->draw_offset);
OUT_BATCH(clearVal);
ADVANCE_BATCH();
clearMask &= ~bufBit; /* turn off bit, for faster loop exit */

375
src/mesa/drivers/dri/i915tex/intel_buffers.c
View file

@ -34,6 +34,7 @@
#include "intel_tris.h"
#include "intel_regions.h"
#include "intel_batchbuffer.h"
#include "intel_reg.h"
#include "context.h"
#include "utils.h"
#include "drirenderbuffer.h"
@ -42,6 +43,23 @@
#include "vblank.h"
/* This block can be removed when libdrm >= 2.3.1 is required */
#ifndef DRM_VBLANK_FLIP
#define DRM_VBLANK_FLIP 0x8000000
typedef struct drm_i915_flip {
int pipes;
} drm_i915_flip_t;
#undef DRM_IOCTL_I915_FLIP
#define DRM_IOCTL_I915_FLIP DRM_IOW(DRM_COMMAND_BASE + DRM_I915_FLIP, \
drm_i915_flip_t)
#endif
/**
* XXX move this into a new dri/common/cliprects.c file.
*/
@ -155,11 +173,14 @@ static void
intelSetBackClipRects(struct intel_context *intel)
{
__DRIdrawablePrivate *dPriv = intel->driDrawable;
struct intel_framebuffer *intel_fb;
if (!dPriv)
return;
if (intel->sarea->pf_enabled == 0 && dPriv->numBackClipRects == 0) {
intel_fb = dPriv->driverPrivate;
if (intel_fb->pf_active || dPriv->numBackClipRects == 0) {
/* use the front clip rects */
intel->numClipRects = dPriv->numClipRects;
intel->pClipRects = dPriv->pClipRects;
@ -185,7 +206,7 @@ intelWindowMoved(struct intel_context *intel)
{
GLcontext *ctx = &intel->ctx;
__DRIdrawablePrivate *dPriv = intel->driDrawable;
GLframebuffer *drawFb = (GLframebuffer *) dPriv->driverPrivate;
struct intel_framebuffer *intel_fb = dPriv->driverPrivate;
if (!intel->ctx.DrawBuffer) {
/* when would this happen? -BP */
@ -197,7 +218,7 @@ intelWindowMoved(struct intel_context *intel)
}
else {
/* drawing to a window */
switch (drawFb->_ColorDrawBufferMask[0]) {
switch (intel_fb->Base._ColorDrawBufferMask[0]) {
case BUFFER_BIT_FRONT_LEFT:
intelSetFrontClipRects(intel);
break;
@ -210,10 +231,6 @@ intelWindowMoved(struct intel_context *intel)
}
}
/* Update Mesa's notion of window size */
driUpdateFramebufferSize(ctx, dPriv);
drawFb->Initialized = GL_TRUE; /* XXX remove someday */
if (intel->intelScreen->driScrnPriv->ddxMinor >= 7) {
drmI830Sarea *sarea = intel->sarea;
drm_clip_rect_t drw_rect = { .x1 = dPriv->x, .x2 = dPriv->x + dPriv->w,
@ -226,22 +243,110 @@ intelWindowMoved(struct intel_context *intel)
.y2 = sarea->pipeB_y + sarea->pipeB_h };
GLint areaA = driIntersectArea( drw_rect, pipeA_rect );
GLint areaB = driIntersectArea( drw_rect, pipeB_rect );
GLuint flags = intel->vblank_flags;
GLuint flags = intel_fb->vblank_flags;
GLboolean pf_active;
GLint pf_pipes;
if (areaB > areaA || (areaA == areaB && areaB > 0)) {
flags = intel->vblank_flags | VBLANK_FLAG_SECONDARY;
} else {
flags = intel->vblank_flags & ~VBLANK_FLAG_SECONDARY;
/* Update page flipping info
*/
pf_pipes = 0;
if (areaA > 0)
pf_pipes |= 1;
if (areaB > 0)
pf_pipes |= 2;
intel_fb->pf_current_page = (intel->sarea->pf_current_page >>
(intel_fb->pf_pipes & 0x2)) & 0x3;
intel_fb->pf_num_pages = intel->intelScreen->third.handle ? 3 : 2;
pf_active = pf_pipes && (pf_pipes & intel->sarea->pf_active) == pf_pipes;
if (INTEL_DEBUG & DEBUG_LOCK)
if (pf_active != intel_fb->pf_active)
_mesa_printf("%s - Page flipping %sactive\n", __progname,
pf_active ? "" : "in");
if (pf_active) {
/* Sync pages between pipes if we're flipping on both at the same time */
if (pf_pipes == 0x3 && pf_pipes != intel_fb->pf_pipes &&
(intel->sarea->pf_current_page & 0x3) !=
(((intel->sarea->pf_current_page) >> 2) & 0x3)) {
drm_i915_flip_t flip;
if (intel_fb->pf_current_page ==
(intel->sarea->pf_current_page & 0x3)) {
/* XXX: This is ugly, but emitting two flips 'in a row' can cause
* lockups for unknown reasons.
*/
intel->sarea->pf_current_page =
intel->sarea->pf_current_page & 0x3;
intel->sarea->pf_current_page |=
((intel_fb->pf_current_page + intel_fb->pf_num_pages - 1) %
intel_fb->pf_num_pages) << 2;
flip.pipes = 0x2;
} else {
intel->sarea->pf_current_page =
intel->sarea->pf_current_page & (0x3 << 2);
intel->sarea->pf_current_page |=
(intel_fb->pf_current_page + intel_fb->pf_num_pages - 1) %
intel_fb->pf_num_pages;
flip.pipes = 0x1;
}
drmCommandWrite(intel->driFd, DRM_I915_FLIP, &flip, sizeof(flip));
}
intel_fb->pf_pipes = pf_pipes;
}
if (flags != intel->vblank_flags) {
intel->vblank_flags = flags;
driGetCurrentVBlank(dPriv, intel->vblank_flags, &intel->vbl_seq);
intel_fb->pf_active = pf_active;
intel_flip_renderbuffers(intel_fb);
intel_draw_buffer(&intel->ctx, intel->ctx.DrawBuffer);
/* Update vblank info
*/
if (areaB > areaA || (areaA == areaB && areaB > 0)) {
flags = intel_fb->vblank_flags | VBLANK_FLAG_SECONDARY;
} else {
flags = intel_fb->vblank_flags & ~VBLANK_FLAG_SECONDARY;
}
if (flags != intel_fb->vblank_flags) {
drmVBlank vbl;
int i;
vbl.request.type = DRM_VBLANK_ABSOLUTE;
if ( intel_fb->vblank_flags & VBLANK_FLAG_SECONDARY ) {
vbl.request.type |= DRM_VBLANK_SECONDARY;
}
for (i = 0; i < intel_fb->pf_num_pages; i++) {
vbl.request.sequence = intel_fb->color_rb[i]->vbl_pending;
drmWaitVBlank(intel->driFd, &vbl);
}
intel_fb->vblank_flags = flags;
driGetCurrentVBlank(dPriv, intel_fb->vblank_flags, &intel_fb->vbl_seq);
intel_fb->vbl_waited = intel_fb->vbl_seq;
for (i = 0; i < intel_fb->pf_num_pages; i++) {
intel_fb->color_rb[i]->vbl_pending = intel_fb->vbl_waited;
}
}
} else {
intel->vblank_flags &= ~VBLANK_FLAG_SECONDARY;
intel_fb->vblank_flags &= ~VBLANK_FLAG_SECONDARY;
}
/* Update Mesa's notion of window size */
driUpdateFramebufferSize(ctx, dPriv);
intel_fb->Base.Initialized = GL_TRUE; /* XXX remove someday */
/* Update hardware scissor */
ctx->Driver.Scissor(ctx, ctx->Scissor.X, ctx->Scissor.Y,
ctx->Scissor.Width, ctx->Scissor.Height);
@ -259,6 +364,7 @@ static void
intelClearWithTris(struct intel_context *intel, GLbitfield mask)
{
GLcontext *ctx = &intel->ctx;
struct gl_framebuffer *fb = ctx->DrawBuffer;
drm_clip_rect_t clear;
if (INTEL_DEBUG & DEBUG_BLIT)
@ -274,10 +380,10 @@ intelClearWithTris(struct intel_context *intel, GLbitfield mask)
intel->vtbl.install_meta_state(intel);
/* Get clear bounds after locking */
cx = ctx->DrawBuffer->_Xmin;
cy = ctx->DrawBuffer->_Ymin;
ch = ctx->DrawBuffer->_Ymax - ctx->DrawBuffer->_Ymin;
cw = ctx->DrawBuffer->_Xmax - ctx->DrawBuffer->_Xmin;
cx = fb->_Xmin;
cy = fb->_Ymin;
ch = fb->_Ymax - cx;
cw = fb->_Xmax - cy;
/* note: regardless of 'all', cx, cy, cw, ch are now correct */
clear.x1 = cx;
@ -291,9 +397,9 @@ intelClearWithTris(struct intel_context *intel, GLbitfield mask)
if (mask &
(BUFFER_BIT_BACK_LEFT | BUFFER_BIT_STENCIL | BUFFER_BIT_DEPTH)) {
struct intel_region *backRegion =
intel_get_rb_region(ctx->DrawBuffer, BUFFER_BACK_LEFT);
intel_get_rb_region(fb, BUFFER_BACK_LEFT);
struct intel_region *depthRegion =
intel_get_rb_region(ctx->DrawBuffer, BUFFER_DEPTH);
intel_get_rb_region(fb, BUFFER_DEPTH);
const GLuint clearColor = (backRegion && backRegion->cpp == 4)
? intel->ClearColor8888 : intel->ClearColor565;
@ -330,8 +436,7 @@ intelClearWithTris(struct intel_context *intel, GLbitfield mask)
const GLuint bufBit = 1 << buf;
if (mask & bufBit) {
struct intel_renderbuffer *irbColor =
intel_renderbuffer(ctx->DrawBuffer->
Attachment[buf].Renderbuffer);
intel_renderbuffer(fb->Attachment[buf].Renderbuffer);
GLuint color = (irbColor->region->cpp == 4)
? intel->ClearColor8888 : intel->ClearColor565;
@ -372,6 +477,7 @@ intelRotateWindow(struct intel_context *intel,
{
intelScreenPrivate *screen = intel->intelScreen;
drm_clip_rect_t fullRect;
struct intel_framebuffer *intel_fb;
struct intel_region *src;
const drm_clip_rect_t *clipRects;
int numClipRects;
@ -421,16 +527,18 @@ intelRotateWindow(struct intel_context *intel,
intel->vtbl.meta_draw_region(intel, screen->rotated_region, NULL); /* ? */
if (srcBuf == BUFFER_BIT_FRONT_LEFT) {
src = intel->intelScreen->front_region;
clipRects = dPriv->pClipRects;
numClipRects = dPriv->numClipRects;
}
else {
src = intel->intelScreen->back_region;
intel_fb = dPriv->driverPrivate;
if ((srcBuf == BUFFER_BIT_BACK_LEFT && !intel_fb->pf_active)) {
src = intel_get_rb_region(&intel_fb->Base, BUFFER_BACK_LEFT);
clipRects = dPriv->pBackClipRects;
numClipRects = dPriv->numBackClipRects;
}
else {
src = intel_get_rb_region(&intel_fb->Base, BUFFER_FRONT_LEFT);
clipRects = dPriv->pClipRects;
numClipRects = dPriv->numClipRects;
}
if (src->cpp == 4) {
format = GL_BGRA;
@ -516,6 +624,7 @@ intelClear(GLcontext *ctx, GLbitfield mask)
GLbitfield tri_mask = 0;
GLbitfield blit_mask = 0;
GLbitfield swrast_mask = 0;
struct gl_framebuffer *fb = ctx->DrawBuffer;
GLuint i;
if (0)
@ -535,7 +644,7 @@ intelClear(GLcontext *ctx, GLbitfield mask)
/* HW stencil */
if (mask & BUFFER_BIT_STENCIL) {
const struct intel_region *stencilRegion
= intel_get_rb_region(ctx->DrawBuffer, BUFFER_STENCIL);
= intel_get_rb_region(fb, BUFFER_STENCIL);
if (stencilRegion) {
/* have hw stencil */
if ((ctx->Stencil.WriteMask[0] & 0xff) != 0xff) {
@ -564,7 +673,7 @@ intelClear(GLcontext *ctx, GLbitfield mask)
for (i = 0; i < BUFFER_COUNT; i++) {
GLuint bufBit = 1 << i;
if ((blit_mask | tri_mask) & bufBit) {
if (!ctx->DrawBuffer->Attachment[i].Renderbuffer->ClassID) {
if (!fb->Attachment[i].Renderbuffer->ClassID) {
blit_mask &= ~bufBit;
tri_mask &= ~bufBit;
swrast_mask |= bufBit;
@ -586,15 +695,43 @@ intelClear(GLcontext *ctx, GLbitfield mask)
}
/* Emit wait for pending flips */
void
intel_wait_flips(struct intel_context *intel, GLuint batch_flags)
{
struct intel_framebuffer *intel_fb =
(struct intel_framebuffer *) intel->ctx.DrawBuffer;
struct intel_renderbuffer *intel_rb =
intel_get_renderbuffer(&intel_fb->Base,
intel_fb->Base._ColorDrawBufferMask[0] ==
BUFFER_BIT_FRONT_LEFT ? BUFFER_FRONT_LEFT :
BUFFER_BACK_LEFT);
if (intel_fb->Base.Name == 0 && intel_rb->pf_pending == intel_fb->pf_seq) {
GLint pf_pipes = intel_fb->pf_pipes;
BATCH_LOCALS;
/* Wait for pending flips to take effect */
BEGIN_BATCH(2, batch_flags);
OUT_BATCH(pf_pipes & 0x1 ? (MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP)
: 0);
OUT_BATCH(pf_pipes & 0x2 ? (MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_B_FLIP)
: 0);
ADVANCE_BATCH();
intel_rb->pf_pending--;
}
}
/* Flip the front & back buffers
*/
static void
static GLboolean
intelPageFlip(const __DRIdrawablePrivate * dPriv)
{
#if 0
struct intel_context *intel;
int tmp, ret;
int ret;
struct intel_framebuffer *intel_fb = dPriv->driverPrivate;
if (INTEL_DEBUG & DEBUG_IOCTL)
fprintf(stderr, "%s\n", __FUNCTION__);
@ -605,28 +742,45 @@ intelPageFlip(const __DRIdrawablePrivate * dPriv)
intel = (struct intel_context *) dPriv->driContextPriv->driverPrivate;
if (intel->intelScreen->drmMinor < 9)
return GL_FALSE;
intelFlush(&intel->ctx);
ret = 0;
LOCK_HARDWARE(intel);
if (dPriv->pClipRects) {
*(drm_clip_rect_t *) intel->sarea->boxes = dPriv->pClipRects[0];
intel->sarea->nbox = 1;
if (dPriv->numClipRects && intel_fb->pf_active) {
drm_i915_flip_t flip;
flip.pipes = intel_fb->pf_pipes;
ret = drmCommandWrite(intel->driFd, DRM_I915_FLIP, &flip, sizeof(flip));
}
ret = drmCommandNone(intel->driFd, DRM_I830_FLIP);
if (ret) {
fprintf(stderr, "%s: %d\n", __FUNCTION__, ret);
UNLOCK_HARDWARE(intel);
exit(1);
}
tmp = intel->sarea->last_enqueue;
intelRefillBatchLocked(intel);
UNLOCK_HARDWARE(intel);
if (ret || !intel_fb->pf_active)
return GL_FALSE;
intelSetDrawBuffer(&intel->ctx, intel->ctx.Color.DriverDrawBuffer);
#endif
if (!dPriv->numClipRects) {
usleep(10000); /* throttle invisible client 10ms */
}
intel_fb->pf_current_page = (intel->sarea->pf_current_page >>
(intel_fb->pf_pipes & 0x2)) & 0x3;
if (dPriv->numClipRects != 0) {
intel_get_renderbuffer(&intel_fb->Base, BUFFER_FRONT_LEFT)->pf_pending =
intel_get_renderbuffer(&intel_fb->Base, BUFFER_BACK_LEFT)->pf_pending =
++intel_fb->pf_seq;
}
intel_flip_renderbuffers(intel_fb);
intel_draw_buffer(&intel->ctx, &intel_fb->Base);
return GL_TRUE;
}
#if 0
@ -641,7 +795,7 @@ intelSwapBuffers(__DRIdrawablePrivate * dPriv)
if (ctx && ctx->DrawBuffer == fb) {
_mesa_notifySwapBuffers(ctx); /* flush pending rendering */
}
if (0 /*intel->doPageFlip */ ) { /* doPageFlip is never set !!! */
if (intel->doPageFlip) {
intelPageFlip(dPriv);
}
else {
@ -657,6 +811,83 @@ intelSwapBuffers(__DRIdrawablePrivate * dPriv)
#else
/* Trunk version:
*/
static GLboolean
intelScheduleSwap(const __DRIdrawablePrivate * dPriv, GLboolean *missed_target)
{
struct intel_framebuffer *intel_fb = dPriv->driverPrivate;
unsigned int interval = driGetVBlankInterval(dPriv, intel_fb->vblank_flags);
struct intel_context *intel =
intelScreenContext(dPriv->driScreenPriv->private);
const intelScreenPrivate *intelScreen = intel->intelScreen;
unsigned int target;
drm_i915_vblank_swap_t swap;
GLboolean ret;
if ((intel_fb->vblank_flags & VBLANK_FLAG_NO_IRQ) ||
intelScreen->current_rotation != 0 ||
intelScreen->drmMinor < (intel_fb->pf_active ? 9 : 6))
return GL_FALSE;
swap.seqtype = DRM_VBLANK_ABSOLUTE;
if (intel_fb->vblank_flags & VBLANK_FLAG_SYNC) {
swap.seqtype |= DRM_VBLANK_NEXTONMISS;
} else if (interval == 0) {
return GL_FALSE;
}
swap.drawable = dPriv->hHWDrawable;
target = swap.sequence = intel_fb->vbl_seq + interval;
if ( intel_fb->vblank_flags & VBLANK_FLAG_SECONDARY ) {
swap.seqtype |= DRM_VBLANK_SECONDARY;
}
LOCK_HARDWARE(intel);
intel_batchbuffer_flush(intel->batch);
if ( intel_fb->pf_active ) {
swap.seqtype |= DRM_VBLANK_FLIP;
intel_fb->pf_current_page = (((intel->sarea->pf_current_page >>
(intel_fb->pf_pipes & 0x2)) & 0x3) + 1) %
intel_fb->pf_num_pages;
}
if (!drmCommandWriteRead(intel->driFd, DRM_I915_VBLANK_SWAP, &swap,
sizeof(swap))) {
intel_fb->vbl_seq = swap.sequence;
swap.sequence -= target;
*missed_target = swap.sequence > 0 && swap.sequence <= (1 << 23);
intel_get_renderbuffer(&intel_fb->Base, BUFFER_BACK_LEFT)->vbl_pending =
intel_get_renderbuffer(&intel_fb->Base,
BUFFER_FRONT_LEFT)->vbl_pending =
intel_fb->vbl_seq;
if (swap.seqtype & DRM_VBLANK_FLIP) {
intel_flip_renderbuffers(intel_fb);
intel_draw_buffer(&intel->ctx, intel->ctx.DrawBuffer);
}
ret = GL_TRUE;
} else {
if (swap.seqtype & DRM_VBLANK_FLIP) {
intel_fb->pf_current_page = ((intel->sarea->pf_current_page >>
(intel_fb->pf_pipes & 0x2)) & 0x3) %
intel_fb->pf_num_pages;
}
ret = GL_FALSE;
}
UNLOCK_HARDWARE(intel);
return ret;
}
void
intelSwapBuffers(__DRIdrawablePrivate * dPriv)
{
@ -671,16 +902,34 @@ intelSwapBuffers(__DRIdrawablePrivate * dPriv)
if (ctx->Visual.doubleBufferMode) {
intelScreenPrivate *screen = intel->intelScreen;
_mesa_notifySwapBuffers(ctx); /* flush pending rendering comands */
if (0 /*intel->doPageFlip */ ) { /* doPageFlip is never set !!! */
intelPageFlip(dPriv);
}
else {
intelCopyBuffer(dPriv, NULL);
}
if (screen->current_rotation != 0) {
intelRotateWindow(intel, dPriv, BUFFER_BIT_FRONT_LEFT);
}
GLboolean missed_target;
struct intel_framebuffer *intel_fb = dPriv->driverPrivate;
int64_t ust;
_mesa_notifySwapBuffers(ctx); /* flush pending rendering comands */
if (screen->current_rotation != 0 ||
!intelScheduleSwap(dPriv, &missed_target)) {
driWaitForVBlank(dPriv, &intel_fb->vbl_seq, intel_fb->vblank_flags,
&missed_target);
if (screen->current_rotation != 0 || !intelPageFlip(dPriv)) {
intelCopyBuffer(dPriv, NULL);
}
if (screen->current_rotation != 0) {
intelRotateWindow(intel, dPriv, BUFFER_BIT_FRONT_LEFT);
}
}
intel_fb->swap_count++;
(*dri_interface->getUST) (&ust);
if (missed_target) {
intel_fb->swap_missed_count++;
intel_fb->swap_missed_ust = ust - intel_fb->swap_ust;
}
intel_fb->swap_ust = ust;
}
}
else {
@ -788,10 +1037,6 @@ intel_draw_buffer(GLcontext * ctx, struct gl_framebuffer *fb)
*/
if (fb->Name == 0) {
/* drawing to window system buffer */
if (intel->sarea->pf_current_page == 1) {
/* page flipped back/front */
front ^= 1;
}
if (front) {
intelSetFrontClipRects(intel);
colorRegion = intel_get_rb_region(fb, BUFFER_FRONT_LEFT);

3
src/mesa/drivers/dri/i915tex/intel_buffers.h
View file

@ -30,6 +30,7 @@
struct intel_context;
struct intel_framebuffer;
extern GLboolean
@ -41,6 +42,8 @@ extern struct intel_region *intel_readbuf_region(struct intel_context *intel);
extern struct intel_region *intel_drawbuf_region(struct intel_context *intel);
extern void intel_wait_flips(struct intel_context *intel, GLuint batch_flags);
extern void intelSwapBuffers(__DRIdrawablePrivate * dPriv);
extern void intelWindowMoved(struct intel_context *intel);

78
src/mesa/drivers/dri/i915tex/intel_context.c
View file

@ -59,6 +59,7 @@
#include "intel_buffer_objects.h"
#include "intel_fbo.h"
#include "drirenderbuffer.h"
#include "vblank.h"
#include "utils.h"
#include "xmlpool.h" /* for symbolic values of enum-type options */
@ -442,10 +443,6 @@ intelInitContext(struct intel_context *intel,
intel->do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
intel->vblank_flags = (intel->intelScreen->irq_active != 0)
? driGetDefaultVBlankFlags(&intel->optionCache) : VBLANK_FLAG_NO_IRQ;
(*dri_interface->getUST) (&intel->swap_ust);
_math_matrix_ctr(&intel->ViewportMatrix);
/* Disable imaging extension until convolution is working in
@ -550,27 +547,30 @@ intelMakeCurrent(__DRIcontextPrivate * driContextPriv,
if (driContextPriv) {
struct intel_context *intel =
(struct intel_context *) driContextPriv->driverPrivate;
GLframebuffer *drawFb = (GLframebuffer *) driDrawPriv->driverPrivate;
struct intel_framebuffer *intel_fb =
(struct intel_framebuffer *) driDrawPriv->driverPrivate;
GLframebuffer *readFb = (GLframebuffer *) driReadPriv->driverPrivate;
/* XXX FBO temporary fix-ups! */
/* if the renderbuffers don't have regions, init them from the context */
{
struct intel_renderbuffer *irbFront
= intel_get_renderbuffer(drawFb, BUFFER_FRONT_LEFT);
struct intel_renderbuffer *irbBack
= intel_get_renderbuffer(drawFb, BUFFER_BACK_LEFT);
struct intel_renderbuffer *irbDepth
= intel_get_renderbuffer(drawFb, BUFFER_DEPTH);
= intel_get_renderbuffer(&intel_fb->Base, BUFFER_DEPTH);
struct intel_renderbuffer *irbStencil
= intel_get_renderbuffer(drawFb, BUFFER_STENCIL);
= intel_get_renderbuffer(&intel_fb->Base, BUFFER_STENCIL);
if (irbFront && !irbFront->region) {
intel_region_reference(&irbFront->region, intel->intelScreen->front_region);
if (intel_fb->color_rb[0] && !intel_fb->color_rb[0]->region) {
intel_region_reference(&intel_fb->color_rb[0]->region,
intel->intelScreen->front_region);
}
if (irbBack && !irbBack->region) {
intel_region_reference(&irbBack->region, intel->intelScreen->back_region);
if (intel_fb->color_rb[1] && !intel_fb->color_rb[1]->region) {
intel_region_reference(&intel_fb->color_rb[1]->region,
intel->intelScreen->back_region);
}
if (intel_fb->color_rb[2] && !intel_fb->color_rb[2]->region) {
intel_region_reference(&intel_fb->color_rb[2]->region,
intel->intelScreen->third_region);
}
if (irbDepth && !irbDepth->region) {
intel_region_reference(&irbDepth->region, intel->intelScreen->depth_region);
@ -580,29 +580,34 @@ intelMakeCurrent(__DRIcontextPrivate * driContextPriv,
}
}
/* set initial GLframebuffer size to match window, if needed */
if (drawFb->Width == 0 && driDrawPriv->w) {
_mesa_resize_framebuffer(&intel->ctx, drawFb,
/* set GLframebuffer size to match window, if needed */
if (intel_fb->Base.Width != driDrawPriv->w) {
_mesa_resize_framebuffer(&intel->ctx, &intel_fb->Base,
driDrawPriv->w, driDrawPriv->h);
}
if (readFb->Width == 0 && driReadPriv->w) {
if (readFb->Width != driReadPriv->w) {
_mesa_resize_framebuffer(&intel->ctx, readFb,
driReadPriv->w, driReadPriv->h);
}
_mesa_make_current(&intel->ctx, drawFb, readFb);
_mesa_make_current(&intel->ctx, &intel_fb->Base, readFb);
/* The drawbuffer won't always be updated by _mesa_make_current:
*/
if (intel->ctx.DrawBuffer == drawFb) {
if (intel->ctx.DrawBuffer == &intel_fb->Base) {
if (intel->driDrawable != driDrawPriv) {
driDrawableInitVBlank(driDrawPriv, intel->vblank_flags, &intel->vbl_seq);
intel_fb->vblank_flags = (intel->intelScreen->irq_active != 0)
? driGetDefaultVBlankFlags(&intel->optionCache)
: VBLANK_FLAG_NO_IRQ;
(*dri_interface->getUST) (&intel_fb->swap_ust);
driDrawableInitVBlank(driDrawPriv, intel_fb->vblank_flags,
&intel_fb->vbl_seq);
intel->driDrawable = driDrawPriv;
intelWindowMoved(intel);
}
intel_draw_buffer(&intel->ctx, drawFb);
intel_draw_buffer(&intel->ctx, &intel_fb->Base);
}
}
else {
@ -683,7 +688,6 @@ intelContendedLock(struct intel_context *intel, GLuint flags)
intel->current_rotation = sarea->rotation;
}
/* Drawable changed?
*/
if (dPriv && intel->lastStamp != dPriv->lastStamp) {
@ -693,24 +697,40 @@ intelContendedLock(struct intel_context *intel, GLuint flags)
}
/* Lock the hardware and validate our state.
*/
void LOCK_HARDWARE( struct intel_context *intel )
{
char __ret=0;
struct intel_framebuffer *intel_fb = NULL;
struct intel_renderbuffer *intel_rb = NULL;
_glthread_LOCK_MUTEX(lockMutex);
assert(!intel->locked);
if (intel->swap_scheduled) {
if (intel->driDrawable) {
intel_fb = intel->driDrawable->driverPrivate;
if (intel_fb)
intel_rb =
intel_get_renderbuffer(&intel_fb->Base,
intel_fb->Base._ColorDrawBufferMask[0] ==
BUFFER_BIT_FRONT_LEFT ? BUFFER_FRONT_LEFT :
BUFFER_BACK_LEFT);
}
if (intel_rb && (intel_fb->vbl_waited - intel_rb->vbl_pending) > (1<<23)) {
drmVBlank vbl;
vbl.request.type = DRM_VBLANK_ABSOLUTE;
if ( intel->vblank_flags & VBLANK_FLAG_SECONDARY ) {
if ( intel_fb->vblank_flags & VBLANK_FLAG_SECONDARY ) {
vbl.request.type |= DRM_VBLANK_SECONDARY;
}
vbl.request.sequence = intel->vbl_seq;
vbl.request.sequence = intel_rb->vbl_pending;
drmWaitVBlank(intel->driFd, &vbl);
intel->swap_scheduled = 0;
intel_fb->vbl_waited = vbl.reply.sequence;
}
DRM_CAS(intel->driHwLock, intel->hHWContext,

14
src/mesa/drivers/dri/i915tex/intel_context.h
View file

@ -274,19 +274,6 @@ struct intel_context
*/
driOptionCache optionCache;
/* VBI
*/
GLuint vbl_seq;
GLuint vblank_flags;
int64_t swap_ust;
int64_t swap_missed_ust;
GLuint swap_count;
GLuint swap_missed_count;
GLuint swap_scheduled;
/* Rotation. Need to match that of the
* current screen.
*/
@ -294,7 +281,6 @@ struct intel_context
int width;
int height;
int current_rotation;
};
/* These are functions now:

46
src/mesa/drivers/dri/i915tex/intel_fbo.c
View file

@ -75,11 +75,35 @@ intel_get_renderbuffer(struct gl_framebuffer *fb, GLuint attIndex)
}
void
intel_flip_renderbuffers(struct intel_framebuffer *intel_fb)
{
int current_page = intel_fb->pf_current_page;
int next_page = (current_page + 1) % intel_fb->pf_num_pages;
if (intel_fb->color_rb[current_page] &&
intel_fb->Base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer !=
&intel_fb->color_rb[current_page]->Base) {
_mesa_remove_renderbuffer(&intel_fb->Base, BUFFER_FRONT_LEFT);
_mesa_add_renderbuffer(&intel_fb->Base, BUFFER_FRONT_LEFT,
&intel_fb->color_rb[current_page]->Base);
}
if (intel_fb->color_rb[next_page] &&
intel_fb->Base.Attachment[BUFFER_BACK_LEFT].Renderbuffer !=
&intel_fb->color_rb[next_page]->Base) {
_mesa_remove_renderbuffer(&intel_fb->Base, BUFFER_BACK_LEFT);
_mesa_add_renderbuffer(&intel_fb->Base, BUFFER_BACK_LEFT,
&intel_fb->color_rb[next_page]->Base);
}
}
struct intel_region *
intel_get_rb_region(struct gl_framebuffer *fb, GLuint attIndex)
{
struct intel_renderbuffer *irb
= intel_renderbuffer(fb->Attachment[attIndex].Renderbuffer);
struct intel_renderbuffer *irb = intel_get_renderbuffer(fb, attIndex);
if (irb)
return irb->region;
else
@ -94,7 +118,9 @@ intel_get_rb_region(struct gl_framebuffer *fb, GLuint attIndex)
static struct gl_framebuffer *
intel_new_framebuffer(GLcontext * ctx, GLuint name)
{
/* there's no intel_framebuffer at this time, just use Mesa's class */
/* Only drawable state in intel_framebuffer at this time, just use Mesa's
* class
*/
return _mesa_new_framebuffer(ctx, name);
}
@ -271,10 +297,24 @@ static GLboolean
intel_alloc_window_storage(GLcontext * ctx, struct gl_renderbuffer *rb,
GLenum internalFormat, GLuint width, GLuint height)
{
struct intel_context *intel = intel_context(ctx);
struct intel_framebuffer *intel_fb;
ASSERT(rb->Name == 0);
rb->Width = width;
rb->Height = height;
rb->_ActualFormat = internalFormat;
if (intel && intel->driDrawable &&
(intel_fb = intel->driDrawable->driverPrivate) &&
intel_fb->pf_num_pages == 3 &&
rb == &intel_fb->color_rb[intel_fb->pf_current_page]->Base &&
(rb = &intel_fb->color_rb[(intel_fb->pf_current_page + 2) % 3]->Base)) {
rb->Width = width;
rb->Height = height;
rb->_ActualFormat = internalFormat;
}
return GL_TRUE;
}

35
src/mesa/drivers/dri/i915tex/intel_fbo.h
View file

@ -32,6 +32,35 @@
struct intel_context;
struct intel_region;
/**
* Intel framebuffer, derived from gl_framebuffer.
*/
struct intel_framebuffer
{
struct gl_framebuffer Base;
struct intel_renderbuffer *color_rb[3];
/* Drawable page flipping state */
GLboolean pf_active;
GLuint pf_seq;
GLint pf_pipes;
GLint pf_current_page;
GLint pf_num_pages;
/* VBI
*/
GLuint vbl_seq;
GLuint vblank_flags;
GLuint vbl_waited;
int64_t swap_ust;
int64_t swap_missed_ust;
GLuint swap_count;
GLuint swap_missed_count;
};
/**
* Intel renderbuffer, derived from gl_renderbuffer.
@ -49,6 +78,10 @@ struct intel_renderbuffer
GLuint PairedDepth; /**< only used if this is a depth renderbuffer */
GLuint PairedStencil; /**< only used if this is a stencil renderbuffer */
GLuint pf_pending; /**< sequence number of pending flip */
GLuint vbl_pending; /**< vblank sequence number of pending flip */
};
@ -69,6 +102,8 @@ extern struct intel_renderbuffer *intel_get_renderbuffer(struct gl_framebuffer
*fb,
GLuint attIndex);
extern void intel_flip_renderbuffers(struct intel_framebuffer *intel_fb);
/* XXX make inline or macro */
extern struct intel_region *intel_get_rb_region(struct gl_framebuffer *fb,

4
src/mesa/drivers/dri/i915tex/intel_reg.h
View file

@ -81,4 +81,8 @@
#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
#define MI_WAIT_FOR_EVENT ((0x3<<23))
#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
#endif

111
src/mesa/drivers/dri/i915tex/intel_screen.c
View file

@ -98,6 +98,18 @@ intelMapScreenRegions(__DRIscreenPrivate * sPriv)
return GL_FALSE;
}
if (intelScreen->third.handle) {
if (0)
_mesa_printf("Third 0x%08x ", intelScreen->third.handle);
if (drmMap(sPriv->fd,
intelScreen->third.handle,
intelScreen->third.size,
(drmAddress *) & intelScreen->third.map) != 0) {
intelUnmapScreenRegions(intelScreen);
return GL_FALSE;
}
}
if (0)
_mesa_printf("Depth 0x%08x ", intelScreen->depth.handle);
if (drmMap(sPriv->fd,
@ -119,9 +131,9 @@ intelMapScreenRegions(__DRIscreenPrivate * sPriv)
}
#endif
if (0)
printf("Mappings: front: %p back: %p depth: %p tex: %p\n",
printf("Mappings: front: %p back: %p third: %p depth: %p tex: %p\n",
intelScreen->front.map,
intelScreen->back.map,
intelScreen->back.map, intelScreen->third.map,
intelScreen->depth.map, intelScreen->tex.map);
return GL_TRUE;
}
@ -191,6 +203,18 @@ intel_recreate_static_regions(intelScreenPrivate *intelScreen)
intelScreen->back.pitch / intelScreen->cpp,
intelScreen->height);
if (intelScreen->third.handle) {
intelScreen->third_region =
intel_recreate_static(intelScreen,
intelScreen->third_region,
DRM_BO_FLAG_MEM_TT,
intelScreen->third.offset,
intelScreen->third.map,
intelScreen->cpp,
intelScreen->third.pitch / intelScreen->cpp,
intelScreen->height);
}
/* Still assuming front.cpp == depth.cpp
*/
intelScreen->depth_region =
@ -240,6 +264,13 @@ intelUnmapScreenRegions(intelScreenPrivate * intelScreen)
#endif
intelScreen->back.map = NULL;
}
if (intelScreen->third.map) {
#if REALLY_UNMAP
if (drmUnmap(intelScreen->third.map, intelScreen->third.size) != 0)
printf("drmUnmap third failed!\n");
#endif
intelScreen->third.map = NULL;
}
if (intelScreen->depth.map) {
#if REALLY_UNMAP
drmUnmap(intelScreen->depth.map, intelScreen->depth.size);
@ -325,6 +356,13 @@ intelUpdateScreenFromSAREA(intelScreenPrivate * intelScreen,
intelScreen->back.handle = sarea->back_handle;
intelScreen->back.size = sarea->back_size;
if (intelScreen->driScrnPriv->ddxMinor >= 8) {
intelScreen->third.offset = sarea->third_offset;
intelScreen->third.pitch = sarea->pitch * intelScreen->cpp;
intelScreen->third.handle = sarea->third_handle;
intelScreen->third.size = sarea->third_size;
}
intelScreen->depth.offset = sarea->depth_offset;
intelScreen->depth.pitch = sarea->pitch * intelScreen->cpp;
intelScreen->depth.handle = sarea->depth_handle;
@ -541,31 +579,49 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv,
mesaVis->depthBits != 24);
GLenum rgbFormat = (mesaVis->redBits == 5 ? GL_RGB5 : GL_RGBA8);
struct gl_framebuffer *fb = _mesa_create_framebuffer(mesaVis);
struct intel_framebuffer *intel_fb = CALLOC_STRUCT(intel_framebuffer);
if (!intel_fb)
return GL_FALSE;
_mesa_initialize_framebuffer(&intel_fb->Base, mesaVis);
/* setup the hardware-based renderbuffers */
{
struct intel_renderbuffer *frontRb
intel_fb->color_rb[0]
= intel_create_renderbuffer(rgbFormat,
screen->width, screen->height,
screen->front.offset,
screen->front.pitch,
screen->cpp,
screen->front.map);
intel_set_span_functions(&frontRb->Base);
_mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &frontRb->Base);
intel_set_span_functions(&intel_fb->color_rb[0]->Base);
_mesa_add_renderbuffer(&intel_fb->Base, BUFFER_FRONT_LEFT,
&intel_fb->color_rb[0]->Base);
}
if (mesaVis->doubleBufferMode) {
struct intel_renderbuffer *backRb
intel_fb->color_rb[1]
= intel_create_renderbuffer(rgbFormat,
screen->width, screen->height,
screen->back.offset,
screen->back.pitch,
screen->cpp,
screen->back.map);
intel_set_span_functions(&backRb->Base);
_mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &backRb->Base);
intel_set_span_functions(&intel_fb->color_rb[1]->Base);
_mesa_add_renderbuffer(&intel_fb->Base, BUFFER_BACK_LEFT,
&intel_fb->color_rb[1]->Base);
if (screen->third.handle) {
intel_fb->color_rb[2]
= intel_create_renderbuffer(rgbFormat,
screen->width, screen->height,
screen->third.offset,
screen->third.pitch,
screen->cpp,
screen->third.map);
intel_set_span_functions(&intel_fb->color_rb[2]->Base);
}
}
if (mesaVis->depthBits == 24 && mesaVis->stencilBits == 8) {
@ -579,8 +635,10 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv,
screen->depth.map);
intel_set_span_functions(&depthStencilRb->Base);
/* note: bind RB to two attachment points */
_mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthStencilRb->Base);
_mesa_add_renderbuffer(fb, BUFFER_STENCIL, &depthStencilRb->Base);
_mesa_add_renderbuffer(&intel_fb->Base, BUFFER_DEPTH,
&depthStencilRb->Base);
_mesa_add_renderbuffer(&intel_fb->Base, BUFFER_STENCIL,
&depthStencilRb->Base);
}
else if (mesaVis->depthBits == 16) {
/* just 16-bit depth buffer, no hw stencil */
@ -592,17 +650,19 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv,
screen->cpp, /* 2! */
screen->depth.map);
intel_set_span_functions(&depthRb->Base);
_mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base);
_mesa_add_renderbuffer(&intel_fb->Base, BUFFER_DEPTH, &depthRb->Base);
}
/* now add any/all software-based renderbuffers we may need */
_mesa_add_soft_renderbuffers(fb, GL_FALSE, /* never sw color */
GL_FALSE, /* never sw depth */
swStencil, mesaVis->accumRedBits > 0, GL_FALSE, /* never sw alpha */
GL_FALSE /* never sw aux */ );
driDrawPriv->driverPrivate = (void *) fb;
_mesa_add_soft_renderbuffers(&intel_fb->Base,
GL_FALSE, /* never sw color */
GL_FALSE, /* never sw depth */
swStencil, mesaVis->accumRedBits > 0,
GL_FALSE, /* never sw alpha */
GL_FALSE /* never sw aux */ );
driDrawPriv->driverPrivate = (void *) intel_fb;
return (driDrawPriv->driverPrivate != NULL);
return GL_TRUE;
}
}
@ -619,21 +679,20 @@ intelDestroyBuffer(__DRIdrawablePrivate * driDrawPriv)
static int
intelGetSwapInfo(__DRIdrawablePrivate * dPriv, __DRIswapInfo * sInfo)
{
struct intel_context *intel;
struct intel_framebuffer *intel_fb;
if ((dPriv == NULL) || (dPriv->driContextPriv == NULL)
|| (dPriv->driContextPriv->driverPrivate == NULL)
if ((dPriv == NULL) || (dPriv->driverPrivate == NULL)
|| (sInfo == NULL)) {
return -1;
}
intel = dPriv->driContextPriv->driverPrivate;
sInfo->swap_count = intel->swap_count;
sInfo->swap_ust = intel->swap_ust;
sInfo->swap_missed_count = intel->swap_missed_count;
intel_fb = dPriv->driverPrivate;
sInfo->swap_count = intel_fb->swap_count;
sInfo->swap_ust = intel_fb->swap_ust;
sInfo->swap_missed_count = intel_fb->swap_missed_count;
sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0)
? driCalculateSwapUsage(dPriv, 0, intel->swap_missed_ust)
? driCalculateSwapUsage(dPriv, 0, intel_fb->swap_missed_ust)
: 0.0;
return 0;

2
src/mesa/drivers/dri/i915tex/intel_screen.h
View file

@ -51,12 +51,14 @@ typedef struct
{
intelRegion front;
intelRegion back;
intelRegion third;
intelRegion rotated;
intelRegion depth;
intelRegion tex;
struct intel_region *front_region;
struct intel_region *back_region;
struct intel_region *third_region;
struct intel_region *depth_region;
struct intel_region *rotated_region;

3
src/mesa/drivers/dri/i915tex/intel_tris.c
View file

@ -43,6 +43,7 @@
#include "intel_context.h"
#include "intel_tris.h"
#include "intel_batchbuffer.h"
#include "intel_buffers.h"
#include "intel_reg.h"
#include "intel_span.h"
#include "intel_tex.h"
@ -102,6 +103,8 @@ intelStartInlinePrimitive(struct intel_context *intel,
/* _mesa_printf("%s *", __progname); */
intel_wait_flips(intel, batch_flags);
/* Emit a slot which will be filled with the inline primitive
* command later.
*/

6
src/mesa/drivers/dri/i915tex/server/i830_common.h
View file

@ -129,6 +129,12 @@ typedef struct {
int pipeB_y;
int pipeB_w;
int pipeB_h;
/* Triple buffering */
drm_handle_t third_handle;
int third_offset;
int third_size;
unsigned int third_tiled;
} drmI830Sarea;
/* Flags for perf_boxes

9
src/mesa/drivers/dri/i965/brw_vs_tnl.c
View file

@ -988,7 +988,14 @@ static void build_lighting( struct tnl_program *p )
*/
VPpli = register_param3(p, STATE_LIGHT, i,
STATE_POSITION_NORMALIZED);
half = register_param3(p, STATE_LIGHT, i, STATE_HALF);
if (p->state->light_local_viewer) {
struct ureg eye_hat = get_eye_position_normalized(p);
half = get_temp(p);
emit_op2(p, OPCODE_SUB, half, 0, VPpli, eye_hat);
emit_normalize_vec3(p, half, half);
} else {
half = register_param3(p, STATE_LIGHT, i, STATE_HALF);
}
}
else {
struct ureg Ppli = register_param3(p, STATE_LIGHT, i,

4
src/mesa/drivers/dri/nouveau/nouveau_fifo.c
View file

@ -38,6 +38,10 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "nouveau_object.h"
#include "nouveau_sync.h"
#ifdef NOUVEAU_RING_DEBUG
int nouveau_fifo_remaining=0;
#endif
#define RING_SKIPS 8

20
src/mesa/drivers/dri/nouveau/nouveau_fifo.h
View file

@ -74,17 +74,33 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifdef NOUVEAU_RING_DEBUG
extern int nouveau_fifo_remaining;
#define OUT_RINGp(ptr,sz) do { \
uint32_t* p=(uint32_t*)(ptr); \
int i; printf("OUT_RINGp: (size 0x%x dwords)\n",sz); for(i=0;i<sz;i++) printf(" 0x%08x %f\n", *(p+i), *((float*)(p+i))); \
nouveau_fifo_remaining-=sz; \
}while(0)
#define OUT_RING(n) do { \
printf("OUT_RINGn: 0x%08x (%s)\n", n, __func__); \
nouveau_fifo_remaining--; \
}while(0)
#define OUT_RINGf(n) do { \
printf("OUT_RINGf: %.04f (%s)\n", n, __func__); \
nouveau_fifo_remaining--; \
}while(0)
#define BEGIN_RING_SIZE(subchannel,tag,size) do { \
if (nouveau_fifo_remaining!=0) \
printf("RING ERROR : remaining %d\n",nouveau_fifo_remaining); \
nouveau_state_cache_flush(nmesa); \
if (nmesa->fifo.free <= (size)) \
WAIT_RING(nmesa,(size)); \
OUT_RING( ((size)<<18) | ((subchannel) << 13) | (tag)); \
nmesa->fifo.free -= ((size) + 1); \
nouveau_fifo_remaining=size; \
}while(0)
#else
@ -110,8 +126,6 @@ if (NOUVEAU_RING_TRACE) \
*((float*)(nmesa->fifo.buffer+nmesa->fifo.current++))=(n); \
}while(0)
#endif
#define BEGIN_RING_SIZE(subchannel,tag,size) do { \
nouveau_state_cache_flush(nmesa); \
if (nmesa->fifo.free <= (size)) \
@ -120,6 +134,8 @@ if (NOUVEAU_RING_TRACE) \
nmesa->fifo.free -= ((size) + 1); \
}while(0)
#endif
extern void WAIT_RING(nouveauContextPtr nmesa,u_int32_t size);
extern void nouveau_state_cache_flush(nouveauContextPtr nmesa);
extern void nouveau_state_cache_init(nouveauContextPtr nmesa);

28
src/mesa/drivers/dri/nouveau/nv04_state.c
View file

@ -455,35 +455,37 @@ static GLboolean nv04BindBuffers(nouveauContextPtr nmesa, int num_color,
nouveau_renderbuffer *depth)
{
GLuint x, y, w, h;
uint32_t depth_pitch=(depth?depth->pitch:0+15)&~15+16;
if (depth_pitch<256) depth_pitch=256;
w = color[0]->mesa.Width;
h = color[0]->mesa.Height;
x = nmesa->drawX;
y = nmesa->drawY;
BEGIN_RING_SIZE(NvSubCtxSurf3D, NV04_CONTEXT_SURFACES_3D_FORMAT, 1);
if (color[0]->mesa._ActualFormat == GL_RGBA8)
OUT_RING(0x108/*A8R8G8B8*/);
else
OUT_RING(0x103/*R5G6B5*/);
/* FIXME pitches have to be aligned ! */
BEGIN_RING_SIZE(NvSubCtxSurf3D, NV04_CONTEXT_SURFACES_3D_PITCH, 2);
OUT_RING(color[0]->pitch|(depth?(depth->pitch<<16):0));
OUT_RING(color[0]->pitch|(depth_pitch<<16));
OUT_RING(color[0]->offset);
if (depth) {
BEGIN_RING_SIZE(NvSubCtxSurf3D, NV04_CONTEXT_SURFACES_3D_OFFSET_ZETA, 1);
OUT_RING(depth->offset);
}
BEGIN_RING_SIZE(NvSubCtxSurf3D, NV04_CONTEXT_SURFACES_3D_CLIP_HORIZONTAL, 2);
OUT_RING((w<<16)|x);
OUT_RING((h<<16)|y);
// BEGIN_RING_SIZE(NvSubCtxSurf3D, NV04_CONTEXT_SURFACES_3D_CLIP_HORIZONTAL, 2);
// OUT_RING((w<<16)|x);
// OUT_RING((h<<16)|y);
/* FIXME not sure... */
BEGIN_RING_SIZE(NvSubCtxSurf3D, NV04_CONTEXT_SURFACES_3D_CLIP_SIZE, 1);
OUT_RING((h<<16)|w);
BEGIN_RING_SIZE(NvSubCtxSurf3D, NV04_CONTEXT_SURFACES_3D_FORMAT, 1);
if (color[0]->mesa._ActualFormat == GL_RGBA8)
OUT_RING(108/*A8R8G8B8*/);
else
OUT_RING(103/*R5G6B5*/);
/* BEGIN_RING_SIZE(NvSubCtxSurf3D, NV04_CONTEXT_SURFACES_3D_CLIP_SIZE, 1);
OUT_RING((h<<16)|w);*/
return GL_TRUE;
}

3
src/mesa/drivers/dri/nouveau/nv04_swtcl.c
View file

@ -473,6 +473,7 @@ static inline void nv04OutputVertexFormat(struct nouveau_context* nmesa)
/*
* Tell t_vertex about the vertex format
*/
nmesa->vertex_attr_count = 0;
RENDERINPUTS_COPY(index, nmesa->render_inputs_bitset);
// SX SY SZ INVW
@ -503,7 +504,7 @@ static inline void nv04OutputVertexFormat(struct nouveau_context* nmesa)
nmesa->vertex_size=_tnl_install_attrs( ctx,
nmesa->vertex_attrs,
nmesa->vertex_attr_count,
ctx->Viewport._WindowMap.m, 0 );
nmesa->viewport.m, 0 );
}

60
src/mesa/drivers/dri/r300/r300_cmdbuf.c
View file

@ -291,14 +291,14 @@ void r300InitCmdBuf(r300ContextPtr r300)
/* Initialize state atoms */
ALLOC_STATE( vpt, always, R300_VPT_CMDSIZE, "vpt", 0 );
r300->hw.vpt.cmd[R300_VPT_CMD_0] = cmdpacket0(R300_SE_VPORT_XSCALE, 6);
ALLOC_STATE( unk2080, always, 2, "unk2080", 0 );
r300->hw.unk2080.cmd[0] = cmdpacket0(R300_VAP_CNTL, 1);
ALLOC_STATE( vap_cntl, always, 2, "vap_cntl", 0 );
r300->hw.vap_cntl.cmd[0] = cmdpacket0(R300_VAP_CNTL, 1);
ALLOC_STATE( vte, always, 3, "vte", 0 );
r300->hw.vte.cmd[0] = cmdpacket0(R300_SE_VTE_CNTL, 2);
ALLOC_STATE( unk2134, always, 3, "unk2134", 0 );
r300->hw.unk2134.cmd[0] = cmdpacket0(0x2134, 2);
ALLOC_STATE( unk2140, always, 2, "unk2140", 0 );
r300->hw.unk2140.cmd[0] = cmdpacket0(R300_VAP_CNTL_STATUS, 1);
ALLOC_STATE( vap_cntl_status, always, 2, "vap_cntl_status", 0 );
r300->hw.vap_cntl_status.cmd[0] = cmdpacket0(R300_VAP_CNTL_STATUS, 1);
ALLOC_STATE( vir[0], variable, R300_VIR_CMDSIZE, "vir/0", 0 );
r300->hw.vir[0].cmd[R300_VIR_CMD_0] = cmdpacket0(R300_VAP_INPUT_ROUTE_0_0, 1);
ALLOC_STATE( vir[1], variable, R300_VIR_CMDSIZE, "vir/1", 1 );
@ -335,18 +335,18 @@ void r300InitCmdBuf(r300ContextPtr r300)
r300->hw.lcntl.cmd[0] = cmdpacket0(R300_RE_LINE_CNT, 1);
ALLOC_STATE( unk4260, always, 4, "unk4260", 0 );
r300->hw.unk4260.cmd[0] = cmdpacket0(0x4260, 3);
ALLOC_STATE( unk4274, always, 5, "unk4274", 0 );
r300->hw.unk4274.cmd[0] = cmdpacket0(R300_RE_SHADE, 4);
ALLOC_STATE( unk4288, always, 4, "unk4288", 0 );
r300->hw.unk4288.cmd[0] = cmdpacket0(R300_RE_POLYGON_MODE, 3);
ALLOC_STATE( shade, always, 5, "shade", 0 );
r300->hw.shade.cmd[0] = cmdpacket0(R300_RE_SHADE, 4);
ALLOC_STATE( polygon_mode, always, 4, "unk4288", 0 );
r300->hw.polygon_mode.cmd[0] = cmdpacket0(R300_RE_POLYGON_MODE, 3);
ALLOC_STATE( fogp, always, 3, "fogp", 0 );
r300->hw.fogp.cmd[0] = cmdpacket0(R300_RE_FOG_SCALE, 2);
ALLOC_STATE( unk42A0, always, 2, "unk42A0", 0 );
r300->hw.unk42A0.cmd[0] = cmdpacket0(0x42A0, 1);
ALLOC_STATE( zbias_cntl, always, 2, "zbias_cntl", 0 );
r300->hw.zbias_cntl.cmd[0] = cmdpacket0(R300_RE_ZBIAS_CNTL, 1);
ALLOC_STATE( zbs, always, R300_ZBS_CMDSIZE, "zbs", 0 );
r300->hw.zbs.cmd[R300_ZBS_CMD_0] = cmdpacket0(R300_RE_ZBIAS_T_FACTOR, 4);
ALLOC_STATE( unk42B4, always, 2, "unk42B4", 0 );
r300->hw.unk42B4.cmd[0] = cmdpacket0(R300_RE_OCCLUSION_CNTL, 1);
ALLOC_STATE( occlusion_cntl, always, 2, "occlusion_cntl", 0 );
r300->hw.occlusion_cntl.cmd[0] = cmdpacket0(R300_RE_OCCLUSION_CNTL, 1);
ALLOC_STATE( cul, always, R300_CUL_CMDSIZE, "cul", 0 );
r300->hw.cul.cmd[R300_CUL_CMD_0] = cmdpacket0(R300_RE_CULL_CNTL, 1);
ALLOC_STATE( unk42C0, always, 3, "unk42C0", 0 );
@ -392,8 +392,8 @@ void r300InitCmdBuf(r300ContextPtr r300)
r300->hw.bld.cmd[R300_BLD_CMD_0] = cmdpacket0(R300_RB3D_CBLEND, 2);
ALLOC_STATE( cmk, always, R300_CMK_CMDSIZE, "cmk", 0 );
r300->hw.cmk.cmd[R300_CMK_CMD_0] = cmdpacket0(R300_RB3D_COLORMASK, 1);
ALLOC_STATE( unk4E10, always, 4, "unk4E10", 0 );
r300->hw.unk4E10.cmd[0] = cmdpacket0(R300_RB3D_BLEND_COLOR, 3);
ALLOC_STATE( blend_color, always, 4, "blend_color", 0 );
r300->hw.blend_color.cmd[0] = cmdpacket0(R300_RB3D_BLEND_COLOR, 3);
ALLOC_STATE( cb, always, R300_CB_CMDSIZE, "cb", 0 );
r300->hw.cb.cmd[R300_CB_CMD_0] = cmdpacket0(R300_RB3D_COLOROFFSET0, 1);
r300->hw.cb.cmd[R300_CB_CMD_1] = cmdpacket0(R300_RB3D_COLORPITCH0, 1);
@ -405,8 +405,8 @@ void r300InitCmdBuf(r300ContextPtr r300)
r300->hw.unk4EA0.cmd[0] = cmdpacket0(0x4EA0, 2);
ALLOC_STATE( zs, always, R300_ZS_CMDSIZE, "zstencil", 0 );
r300->hw.zs.cmd[R300_ZS_CMD_0] = cmdpacket0(R300_RB3D_ZSTENCIL_CNTL_0, 3);
ALLOC_STATE( unk4F10, always, 5, "unk4F10", 0 );
r300->hw.unk4F10.cmd[0] = cmdpacket0(R300_RB3D_ZSTENCIL_FORMAT, 4);
ALLOC_STATE( zstencil_format, always, 5, "zstencil_format", 0 );
r300->hw.zstencil_format.cmd[0] = cmdpacket0(R300_RB3D_ZSTENCIL_FORMAT, 4);
ALLOC_STATE( zb, always, R300_ZB_CMDSIZE, "zb", 0 );
r300->hw.zb.cmd[R300_ZB_CMD_0] = cmdpacket0(R300_RB3D_DEPTHOFFSET, 2);
ALLOC_STATE( unk4F28, always, 2, "unk4F28", 0 );
@ -429,8 +429,8 @@ void r300InitCmdBuf(r300ContextPtr r300)
ALLOC_STATE( tex.filter, variable, mtu+1, "tex_filter", 0 );
r300->hw.tex.filter.cmd[R300_TEX_CMD_0] = cmdpacket0(R300_TX_FILTER_0, 0);
ALLOC_STATE( tex.unknown1, variable, mtu+1, "tex_unknown1", 0 );
r300->hw.tex.unknown1.cmd[R300_TEX_CMD_0] = cmdpacket0(R300_TX_FILTER1_0, 0);
ALLOC_STATE( tex.filter_1, variable, mtu+1, "tex_filter_1", 0 );
r300->hw.tex.filter_1.cmd[R300_TEX_CMD_0] = cmdpacket0(R300_TX_FILTER1_0, 0);
ALLOC_STATE( tex.size, variable, mtu+1, "tex_size", 0 );
r300->hw.tex.size.cmd[R300_TEX_CMD_0] = cmdpacket0(R300_TX_SIZE_0, 0);
@ -444,8 +444,8 @@ void r300InitCmdBuf(r300ContextPtr r300)
ALLOC_STATE( tex.offset, variable, mtu+1, "tex_offset", 0 );
r300->hw.tex.offset.cmd[R300_TEX_CMD_0] = cmdpacket0(R300_TX_OFFSET_0, 0);
ALLOC_STATE( tex.unknown4, variable, mtu+1, "tex_unknown4", 0 );
r300->hw.tex.unknown4.cmd[R300_TEX_CMD_0] = cmdpacket0(R300_TX_CHROMA_KEY_0, 0);
ALLOC_STATE( tex.chroma_key, variable, mtu+1, "tex_chroma_key", 0 );
r300->hw.tex.chroma_key.cmd[R300_TEX_CMD_0] = cmdpacket0(R300_TX_CHROMA_KEY_0, 0);
ALLOC_STATE( tex.border_color, variable, mtu+1, "tex_border_color", 0 );
r300->hw.tex.border_color.cmd[R300_TEX_CMD_0] = cmdpacket0(R300_TX_BORDER_COLOR_0, 0);
@ -456,10 +456,10 @@ void r300InitCmdBuf(r300ContextPtr r300)
r300->hw.atomlist.name = "atom-list";
insert_at_tail(&r300->hw.atomlist, &r300->hw.vpt);
insert_at_tail(&r300->hw.atomlist, &r300->hw.unk2080);
insert_at_tail(&r300->hw.atomlist, &r300->hw.vap_cntl);
insert_at_tail(&r300->hw.atomlist, &r300->hw.vte);
insert_at_tail(&r300->hw.atomlist, &r300->hw.unk2134);
insert_at_tail(&r300->hw.atomlist, &r300->hw.unk2140);
insert_at_tail(&r300->hw.atomlist, &r300->hw.vap_cntl_status);
insert_at_tail(&r300->hw.atomlist, &r300->hw.vir[0]);
insert_at_tail(&r300->hw.atomlist, &r300->hw.vir[1]);
insert_at_tail(&r300->hw.atomlist, &r300->hw.vic);
@ -478,12 +478,12 @@ void r300InitCmdBuf(r300ContextPtr r300)
insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4230);
insert_at_tail(&r300->hw.atomlist, &r300->hw.lcntl);
insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4260);
insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4274);
insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4288);
insert_at_tail(&r300->hw.atomlist, &r300->hw.shade);
insert_at_tail(&r300->hw.atomlist, &r300->hw.polygon_mode);
insert_at_tail(&r300->hw.atomlist, &r300->hw.fogp);
insert_at_tail(&r300->hw.atomlist, &r300->hw.unk42A0);
insert_at_tail(&r300->hw.atomlist, &r300->hw.zbias_cntl);
insert_at_tail(&r300->hw.atomlist, &r300->hw.zbs);
insert_at_tail(&r300->hw.atomlist, &r300->hw.unk42B4);
insert_at_tail(&r300->hw.atomlist, &r300->hw.occlusion_cntl);
insert_at_tail(&r300->hw.atomlist, &r300->hw.cul);
insert_at_tail(&r300->hw.atomlist, &r300->hw.unk42C0);
insert_at_tail(&r300->hw.atomlist, &r300->hw.rc);
@ -506,13 +506,13 @@ void r300InitCmdBuf(r300ContextPtr r300)
insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4E00);
insert_at_tail(&r300->hw.atomlist, &r300->hw.bld);
insert_at_tail(&r300->hw.atomlist, &r300->hw.cmk);
insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4E10);
insert_at_tail(&r300->hw.atomlist, &r300->hw.blend_color);
insert_at_tail(&r300->hw.atomlist, &r300->hw.cb);
insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4E50);
insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4E88);
insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4EA0);
insert_at_tail(&r300->hw.atomlist, &r300->hw.zs);
insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4F10);
insert_at_tail(&r300->hw.atomlist, &r300->hw.zstencil_format);
insert_at_tail(&r300->hw.atomlist, &r300->hw.zb);
insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4F28);
insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4F30);
@ -524,12 +524,12 @@ void r300InitCmdBuf(r300ContextPtr r300)
insert_at_tail(&r300->hw.atomlist, &r300->hw.vps);
insert_at_tail(&r300->hw.atomlist, &r300->hw.tex.filter);
insert_at_tail(&r300->hw.atomlist, &r300->hw.tex.unknown1);
insert_at_tail(&r300->hw.atomlist, &r300->hw.tex.filter_1);
insert_at_tail(&r300->hw.atomlist, &r300->hw.tex.size);
insert_at_tail(&r300->hw.atomlist, &r300->hw.tex.format);
insert_at_tail(&r300->hw.atomlist, &r300->hw.tex.pitch);
insert_at_tail(&r300->hw.atomlist, &r300->hw.tex.offset);
insert_at_tail(&r300->hw.atomlist, &r300->hw.tex.unknown4);
insert_at_tail(&r300->hw.atomlist, &r300->hw.tex.chroma_key);
insert_at_tail(&r300->hw.atomlist, &r300->hw.tex.border_color);
r300->hw.is_dirty = GL_TRUE;

21
src/mesa/drivers/dri/r300/r300_context.h
View file

@ -180,6 +180,7 @@ struct r300_tex_obj {
/* hardware register values */
/* Note that R200 has 8 registers per texture and R300 only 7 */
GLuint filter;
GLuint filter_1;
GLuint pitch_reg;
GLuint size; /* npot only */
GLuint format;
@ -432,11 +433,11 @@ struct r300_hw_state {
int max_state_size; /* in dwords */
struct r300_state_atom vpt; /* viewport (1D98) */
struct r300_state_atom unk2080; /* (2080) */
struct r300_state_atom vap_cntl;
struct r300_state_atom vof; /* VAP output format register 0x2090 */
struct r300_state_atom vte; /* (20B0) */
struct r300_state_atom unk2134; /* (2134) */
struct r300_state_atom unk2140; /* (2140) */
struct r300_state_atom vap_cntl_status;
struct r300_state_atom vir[2]; /* vap input route (2150/21E0) */
struct r300_state_atom vic; /* vap input control (2180) */
struct r300_state_atom unk21DC; /* (21DC) */
@ -452,13 +453,13 @@ struct r300_hw_state {
struct r300_state_atom unk4230; /* (4230) */
struct r300_state_atom lcntl; /* line control */
struct r300_state_atom unk4260; /* (4260) */
struct r300_state_atom unk4274; /* (4274) */
struct r300_state_atom unk4288; /* (4288) */
struct r300_state_atom shade;
struct r300_state_atom polygon_mode;
struct r300_state_atom fogp; /* fog parameters (4294) */
struct r300_state_atom unk429C; /* (429C) */
struct r300_state_atom unk42A0; /* (42A0) */
struct r300_state_atom zbias_cntl;
struct r300_state_atom zbs; /* zbias (42A4) */
struct r300_state_atom unk42B4; /* (42B4) */
struct r300_state_atom occlusion_cntl;
struct r300_state_atom cul; /* cull cntl (42B8) */
struct r300_state_atom unk42C0; /* (42C0) */
struct r300_state_atom rc; /* rs control (4300) */
@ -478,13 +479,13 @@ struct r300_hw_state {
struct r300_state_atom unk4E00; /* (4E00) */
struct r300_state_atom bld; /* blending (4E04) */
struct r300_state_atom cmk; /* colormask (4E0C) */
struct r300_state_atom unk4E10; /* constant blend color + ??? (4E10) */
struct r300_state_atom blend_color; /* constant blend color */
struct r300_state_atom cb; /* colorbuffer (4E28) */
struct r300_state_atom unk4E50; /* (4E50) */
struct r300_state_atom unk4E88; /* (4E88) */
struct r300_state_atom unk4EA0; /* (4E88) I saw it only written on RV350 hardware.. */
struct r300_state_atom zs; /* zstencil control (4F00) */
struct r300_state_atom unk4F10; /* (4F10) */
struct r300_state_atom zstencil_format;
struct r300_state_atom zb; /* z buffer (4F20) */
struct r300_state_atom unk4F28; /* (4F28) */
struct r300_state_atom unk4F30; /* (4F30) */
@ -501,12 +502,12 @@ struct r300_hw_state {
updating the whole thing at once */
struct {
struct r300_state_atom filter;
struct r300_state_atom unknown1;
struct r300_state_atom filter_1;
struct r300_state_atom size;
struct r300_state_atom format;
struct r300_state_atom pitch;
struct r300_state_atom offset;
struct r300_state_atom unknown4;
struct r300_state_atom chroma_key;
struct r300_state_atom border_color;
} tex;
struct r300_state_atom txe; /* tex enable (4104) */

1
src/mesa/drivers/dri/r300/r300_reg.h
View file

@ -571,6 +571,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
* Some of the tests indicate that fgl has a fallback implementation of zbias
* via pixel shaders.
*/
#define R300_RE_ZBIAS_CNTL 0x42A0 /* GUESS */
#define R300_RE_ZBIAS_T_FACTOR 0x42A4
#define R300_RE_ZBIAS_T_CONSTANT 0x42A8
#define R300_RE_ZBIAS_W_FACTOR 0x42AC

74
src/mesa/drivers/dri/r300/r300_state.c
View file

@ -69,14 +69,14 @@ static void r300BlendColor(GLcontext * ctx, const GLfloat cf[4])
GLubyte color[4];
r300ContextPtr rmesa = R300_CONTEXT(ctx);
R300_STATECHANGE(rmesa, unk4E10);
R300_STATECHANGE(rmesa, blend_color);
CLAMPED_FLOAT_TO_UBYTE(color[0], cf[0]);
CLAMPED_FLOAT_TO_UBYTE(color[1], cf[1]);
CLAMPED_FLOAT_TO_UBYTE(color[2], cf[2]);
CLAMPED_FLOAT_TO_UBYTE(color[3], cf[3]);
rmesa->hw.unk4E10.cmd[1] = r300PackColor(4, color[3], color[0],
rmesa->hw.blend_color.cmd[1] = r300PackColor(4, color[3], color[0],
color[1], color[2]);
}
@ -335,17 +335,17 @@ static void update_early_z(GLcontext *ctx)
*/
r300ContextPtr r300 = R300_CONTEXT(ctx);
R300_STATECHANGE(r300, unk4F10);
R300_STATECHANGE(r300, zstencil_format);
if (ctx->Color.AlphaEnabled && ctx->Color.AlphaFunc != GL_ALWAYS)
/* disable early Z */
r300->hw.unk4F10.cmd[2] = R300_EARLY_Z_DISABLE;
r300->hw.zstencil_format.cmd[2] = R300_EARLY_Z_DISABLE;
else {
if (ctx->Depth.Test && ctx->Depth.Func != GL_NEVER)
/* enable early Z */
r300->hw.unk4F10.cmd[2] = R300_EARLY_Z_ENABLE;
r300->hw.zstencil_format.cmd[2] = R300_EARLY_Z_ENABLE;
else
/* disable early Z */
r300->hw.unk4F10.cmd[2] = R300_EARLY_Z_DISABLE;
r300->hw.zstencil_format.cmd[2] = R300_EARLY_Z_DISABLE;
}
}
@ -531,11 +531,11 @@ static void r300Enable(GLcontext* ctx, GLenum cap, GLboolean state)
break;
case GL_POLYGON_OFFSET_FILL:
R300_STATECHANGE(r300, unk42B4);
R300_STATECHANGE(r300, occlusion_cntl);
if(state){
r300->hw.unk42B4.cmd[1] |= (3<<0);
r300->hw.occlusion_cntl.cmd[1] |= (3<<0);
} else {
r300->hw.unk42B4.cmd[1] &= ~(3<<0);
r300->hw.occlusion_cntl.cmd[1] &= ~(3<<0);
}
break;
default:
@ -589,9 +589,9 @@ static void r300UpdatePolygonMode(GLcontext *ctx)
}
}
if (r300->hw.unk4288.cmd[1] != hw_mode) {
R300_STATECHANGE(r300, unk4288);
r300->hw.unk4288.cmd[1] = hw_mode;
if (r300->hw.polygon_mode.cmd[1] != hw_mode) {
R300_STATECHANGE(r300, polygon_mode);
r300->hw.polygon_mode.cmd[1] = hw_mode;
}
}
@ -830,13 +830,13 @@ static void r300ShadeModel(GLcontext * ctx, GLenum mode)
{
r300ContextPtr rmesa = R300_CONTEXT(ctx);
R300_STATECHANGE(rmesa, unk4274);
R300_STATECHANGE(rmesa, shade);
switch (mode) {
case GL_FLAT:
rmesa->hw.unk4274.cmd[2] = R300_RE_SHADE_MODEL_FLAT;
rmesa->hw.shade.cmd[2] = R300_RE_SHADE_MODEL_FLAT;
break;
case GL_SMOOTH:
rmesa->hw.unk4274.cmd[2] = R300_RE_SHADE_MODEL_SMOOTH;
rmesa->hw.shade.cmd[2] = R300_RE_SHADE_MODEL_SMOOTH;
break;
default:
return;
@ -1217,12 +1217,12 @@ void r300_setup_textures(GLcontext *ctx)
R300_STATECHANGE(r300, txe);
R300_STATECHANGE(r300, tex.filter);
R300_STATECHANGE(r300, tex.unknown1);
R300_STATECHANGE(r300, tex.filter_1);
R300_STATECHANGE(r300, tex.size);
R300_STATECHANGE(r300, tex.format);
R300_STATECHANGE(r300, tex.pitch);
R300_STATECHANGE(r300, tex.offset);
R300_STATECHANGE(r300, tex.unknown4);
R300_STATECHANGE(r300, tex.chroma_key);
R300_STATECHANGE(r300, tex.border_color);
r300->hw.txe.cmd[R300_TXE_ENABLE]=0x0;
@ -1259,7 +1259,7 @@ void r300_setup_textures(GLcontext *ctx)
r300->hw.tex.filter.cmd[R300_TEX_VALUE_0 + hw_tmu] = gen_fixed_filter(t->filter) | (hw_tmu << 28);
/* Currently disabled! */
r300->hw.tex.unknown1.cmd[R300_TEX_VALUE_0 + hw_tmu] = 0x0; //0x20501f80;
r300->hw.tex.filter_1.cmd[R300_TEX_VALUE_0 + hw_tmu] = 0x0; //0x20501f80;
r300->hw.tex.size.cmd[R300_TEX_VALUE_0 + hw_tmu] = t->size;
r300->hw.tex.format.cmd[R300_TEX_VALUE_0 + hw_tmu] = t->format;
r300->hw.tex.pitch.cmd[R300_TEX_VALUE_0 + hw_tmu] = t->pitch_reg;
@ -1273,7 +1273,7 @@ void r300_setup_textures(GLcontext *ctx)
WARN_ONCE("micro tiling enabled!\n");
}
r300->hw.tex.unknown4.cmd[R300_TEX_VALUE_0 + hw_tmu] = 0x0;
r300->hw.tex.chroma_key.cmd[R300_TEX_VALUE_0 + hw_tmu] = 0x0;
r300->hw.tex.border_color.cmd[R300_TEX_VALUE_0 + hw_tmu] = t->pp_border_color;
last_hw_tmu = hw_tmu;
@ -1283,12 +1283,12 @@ void r300_setup_textures(GLcontext *ctx)
}
r300->hw.tex.filter.cmd[R300_TEX_CMD_0] = cmdpacket0(R300_TX_FILTER_0, last_hw_tmu + 1);
r300->hw.tex.unknown1.cmd[R300_TEX_CMD_0] = cmdpacket0(R300_TX_FILTER1_0, last_hw_tmu + 1);
r300->hw.tex.filter_1.cmd[R300_TEX_CMD_0] = cmdpacket0(R300_TX_FILTER1_0, last_hw_tmu + 1);
r300->hw.tex.size.cmd[R300_TEX_CMD_0] = cmdpacket0(R300_TX_SIZE_0, last_hw_tmu + 1);
r300->hw.tex.format.cmd[R300_TEX_CMD_0] = cmdpacket0(R300_TX_FORMAT_0, last_hw_tmu + 1);
r300->hw.tex.pitch.cmd[R300_TEX_CMD_0] = cmdpacket0(R300_TX_PITCH_0, last_hw_tmu + 1);
r300->hw.tex.offset.cmd[R300_TEX_CMD_0] = cmdpacket0(R300_TX_OFFSET_0, last_hw_tmu + 1);
r300->hw.tex.unknown4.cmd[R300_TEX_CMD_0] = cmdpacket0(R300_TX_CHROMA_KEY_0, last_hw_tmu + 1);
r300->hw.tex.chroma_key.cmd[R300_TEX_CMD_0] = cmdpacket0(R300_TX_CHROMA_KEY_0, last_hw_tmu + 1);
r300->hw.tex.border_color.cmd[R300_TEX_CMD_0] = cmdpacket0(R300_TX_BORDER_COLOR_0, last_hw_tmu + 1);
@ -1973,7 +1973,7 @@ void r300ResetHwState(r300ContextPtr r300)
/* Initialize magic registers
TODO : learn what they really do, or get rid of
those we don't have to touch */
r300->hw.unk2080.cmd[1] = 0x0030045A; //0x0030065a /* Dangerous */
r300->hw.vap_cntl.cmd[1] = 0x0030045A; //0x0030065a /* Dangerous */
r300->hw.vte.cmd[1] = R300_VPORT_X_SCALE_ENA
| R300_VPORT_X_OFFSET_ENA
@ -1987,9 +1987,9 @@ void r300ResetHwState(r300ContextPtr r300)
r300->hw.unk2134.cmd[1] = 0x00FFFFFF;
r300->hw.unk2134.cmd[2] = 0x00000000;
if (_mesa_little_endian())
r300->hw.unk2140.cmd[1] = 0x00000000;
r300->hw.vap_cntl_status.cmd[1] = 0x00000000;
else
r300->hw.unk2140.cmd[1] = 0x00000002;
r300->hw.vap_cntl_status.cmd[1] = 0x00000002;
#if 0 /* Done in setup routing */
((drm_r300_cmd_header_t*)r300->hw.vir[0].cmd)->packet0.count = 1;
@ -2080,16 +2080,16 @@ void r300ResetHwState(r300ContextPtr r300)
r300->hw.unk4260.cmd[2] = r300PackFloat32(0.0);
r300->hw.unk4260.cmd[3] = r300PackFloat32(1.0);
r300->hw.unk4274.cmd[1] = 0x00000002;
r300->hw.shade.cmd[1] = 0x00000002;
r300ShadeModel(ctx, ctx->Light.ShadeModel);
r300->hw.unk4274.cmd[3] = 0x00000000;
r300->hw.unk4274.cmd[4] = 0x00000000;
r300->hw.shade.cmd[3] = 0x00000000;
r300->hw.shade.cmd[4] = 0x00000000;
r300PolygonMode(ctx, GL_FRONT, ctx->Polygon.FrontMode);
r300PolygonMode(ctx, GL_BACK, ctx->Polygon.BackMode);
r300->hw.unk4288.cmd[2] = 0x00000001;
r300->hw.unk4288.cmd[3] = 0x00000000;
r300->hw.unk42A0.cmd[1] = 0x00000000;
r300->hw.polygon_mode.cmd[2] = 0x00000001;
r300->hw.polygon_mode.cmd[3] = 0x00000000;
r300->hw.zbias_cntl.cmd[1] = 0x00000000;
r300PolygonOffset(ctx, ctx->Polygon.OffsetFactor, ctx->Polygon.OffsetUnits);
r300Enable(ctx, GL_POLYGON_OFFSET_FILL, ctx->Polygon.OffsetFill);
@ -2147,8 +2147,8 @@ void r300ResetHwState(r300ContextPtr r300)
#endif
r300BlendColor(ctx, ctx->Color.BlendColor);
r300->hw.unk4E10.cmd[2] = 0;
r300->hw.unk4E10.cmd[3] = 0;
r300->hw.blend_color.cmd[2] = 0;
r300->hw.blend_color.cmd[3] = 0;
/* Again, r300ClearBuffer uses this */
r300->hw.cb.cmd[R300_CB_OFFSET] = r300->radeon.state.color.drawOffset +
@ -2180,10 +2180,10 @@ void r300ResetHwState(r300ContextPtr r300)
switch (ctx->Visual.depthBits) {
case 16:
r300->hw.unk4F10.cmd[1] = R300_DEPTH_FORMAT_16BIT_INT_Z;
r300->hw.zstencil_format.cmd[1] = R300_DEPTH_FORMAT_16BIT_INT_Z;
break;
case 24:
r300->hw.unk4F10.cmd[1] = R300_DEPTH_FORMAT_24BIT_INT_Z;
r300->hw.zstencil_format.cmd[1] = R300_DEPTH_FORMAT_24BIT_INT_Z;
break;
default:
fprintf(stderr, "Error: Unsupported depth %d... exiting\n",
@ -2192,10 +2192,10 @@ void r300ResetHwState(r300ContextPtr r300)
}
/* z compress? */
//r300->hw.unk4F10.cmd[1] |= R300_DEPTH_FORMAT_UNK32;
//r300->hw.zstencil_format.cmd[1] |= R300_DEPTH_FORMAT_UNK32;
r300->hw.unk4F10.cmd[3] = 0x00000003;
r300->hw.unk4F10.cmd[4] = 0x00000000;
r300->hw.zstencil_format.cmd[3] = 0x00000003;
r300->hw.zstencil_format.cmd[4] = 0x00000000;
r300->hw.zb.cmd[R300_ZB_OFFSET] =
r300->radeon.radeonScreen->depthOffset +

12
src/mesa/drivers/dri/r300/radeon_context.c
View file

@ -273,15 +273,15 @@ GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv,
&radeon->vbl_seq);
}
if (radeon->dri.drawable != driDrawPriv ||
radeon->dri.readable != driReadPriv) {
radeon->dri.drawable = driDrawPriv;
radeon->dri.readable = driReadPriv;
radeon->dri.readable = driReadPriv;
r300UpdateWindow(radeon->glCtx);
r300UpdateViewportOffset(radeon->glCtx);
if (radeon->dri.drawable != driDrawPriv ||
radeon->lastStamp != driDrawPriv->lastStamp) {
radeon->dri.drawable = driDrawPriv;
radeonSetCliprects(radeon);
r300UpdateWindow(radeon->glCtx);
r300UpdateViewportOffset(radeon->glCtx);
}
_mesa_make_current(radeon->glCtx,

3
src/mesa/main/getstring.c
View file

@ -114,7 +114,8 @@ _mesa_GetString( GLenum name )
ctx->Extensions.ARB_shader_objects &&
ctx->Extensions.ARB_vertex_shader &&
ctx->Extensions.ARB_fragment_shader &&
ctx->Extensions.ARB_texture_non_power_of_two) {
ctx->Extensions.ARB_texture_non_power_of_two &&
ctx->Extensions.EXT_blend_equation_separate) {
if (ctx->Extensions.ARB_shading_language_120 &&
ctx->Extensions.EXT_pixel_buffer_object &&
ctx->Extensions.EXT_texture_sRGB) {

19
src/mesa/main/image.c
View file

@ -1182,15 +1182,24 @@ _mesa_pack_rgba_span_float(GLcontext *ctx, GLuint n, GLfloat rgba[][4],
if (dstFormat == GL_LUMINANCE || dstFormat == GL_LUMINANCE_ALPHA) {
/* compute luminance values */
if (dstType != GL_FLOAT || ctx->Color.ClampReadColor == GL_TRUE) {
if (transferOps & IMAGE_RED_TO_LUMINANCE) {
/* Luminance = Red (glGetTexImage) */
for (i = 0; i < n; i++) {
GLfloat sum = rgba[i][RCOMP] + rgba[i][GCOMP] + rgba[i][BCOMP];
luminance[i] = CLAMP(sum, 0.0F, 1.0F);
luminance[i] = rgba[i][RCOMP];
}
}
else {
for (i = 0; i < n; i++) {
luminance[i] = rgba[i][RCOMP] + rgba[i][GCOMP] + rgba[i][BCOMP];
/* Luminance = Red + Green + Blue (glReadPixels) */
if (dstType != GL_FLOAT || ctx->Color.ClampReadColor == GL_TRUE) {
for (i = 0; i < n; i++) {
GLfloat sum = rgba[i][RCOMP] + rgba[i][GCOMP] + rgba[i][BCOMP];
luminance[i] = CLAMP(sum, 0.0F, 1.0F);
}
}
else {
for (i = 0; i < n; i++) {
luminance[i] = rgba[i][RCOMP] + rgba[i][GCOMP] + rgba[i][BCOMP];
}
}
}
}

1
src/mesa/main/mtypes.h
View file

@ -2540,6 +2540,7 @@ struct matrix_stack
#define IMAGE_HISTOGRAM_BIT 0x200
#define IMAGE_MIN_MAX_BIT 0x400
#define IMAGE_CLAMP_BIT 0x800 /* extra */
#define IMAGE_RED_TO_LUMINANCE 0x1000
/** Pixel Transfer ops up to convolution */

3
src/mesa/main/rastpos.c
View file

@ -133,8 +133,7 @@ shade_rastpos(GLcontext *ctx,
GLfloat diffuseColor[4], specularColor[4]; /* for RGB mode only */
GLfloat diffuseCI = 0.0, specularCI = 0.0; /* for CI mode only */
if (!ctx->_ShineTable[0] || !ctx->_ShineTable[1])
_mesa_validate_all_lighting_tables( ctx );
_mesa_validate_all_lighting_tables( ctx );
COPY_3V(diffuseColor, base[0]);
diffuseColor[3] = CLAMP(

2
src/mesa/main/texstore.c
View file

@ -3611,7 +3611,7 @@ _mesa_get_teximage(GLcontext *ctx, GLenum target, GLint level,
}
_mesa_pack_rgba_span_float(ctx, width, (GLfloat (*)[4]) rgba,
format, type, dest,
&ctx->Pack, 0x0 /*image xfer ops*/);
&ctx->Pack, IMAGE_RED_TO_LUMINANCE);
} /* format */
} /* row */
} /* img */

9
src/mesa/tnl/t_vp_build.c
View file

@ -939,7 +939,14 @@ static void build_lighting( struct tnl_program *p )
*/
VPpli = register_param3(p, STATE_LIGHT, i,
STATE_POSITION_NORMALIZED);
half = register_param3(p, STATE_LIGHT, i, STATE_HALF);
if (p->state->light_local_viewer) {
struct ureg eye_hat = get_eye_position_normalized(p);
half = get_temp(p);
emit_op2(p, OPCODE_SUB, half, 0, VPpli, eye_hat);
emit_normalize_vec3(p, half, half);
} else {
half = register_param3(p, STATE_LIGHT, i, STATE_HALF);
}
}
else {
struct ureg Ppli = register_param3(p, STATE_LIGHT, i,

60
src/mesa/vbo/descrip.mms Normal file
View file

@ -0,0 +1,60 @@
# Makefile for core library for VMS
# contributed by Jouk Jansen joukj@hrem.nano.tudelft.nl
# Last revision : 7 March 2007
.first
define gl [---.include.gl]
define math [-.math]
define vbo [-.vbo]
define tnl [-.tnl]
define shader [-.shader]
define swrast [-.swrast]
define swrast_setup [-.swrast_setup]
.include [---]mms-config.
##### MACROS #####
VPATH = RCS
INCDIR = [---.include],[-.main],[-.glapi],[-.shader],[-.shader.slang]
LIBDIR = [---.lib]
CFLAGS = /include=($(INCDIR),[])/define=(PTHREADS=1)/name=(as_is,short)/float=ieee/ieee=denorm
SOURCES =vbo_context.c,vbo_exec.c,vbo_exec_api.c,vbo_exec_array.c,\
vbo_exec_draw.c,vbo_exec_eval.c,vbo_rebase.c,vbo_save.c,\
vbo_save_api.c,vbo_save_draw.c,vbo_save_loopback.c,\
vbo_split.c,vbo_split_copy.c,vbo_split_inplace.c
OBJECTS =vbo_context.obj,vbo_exec.obj,vbo_exec_api.obj,vbo_exec_array.obj,\
vbo_exec_draw.obj,vbo_exec_eval.obj,vbo_rebase.obj,vbo_save.obj,\
vbo_save_api.obj,vbo_save_draw.obj,vbo_save_loopback.obj,\
vbo_split.obj,vbo_split_copy.obj,vbo_split_inplace.obj
##### RULES #####
VERSION=Mesa V3.4
##### TARGETS #####
# Make the library
$(LIBDIR)$(GL_LIB) : $(OBJECTS)
@ library $(LIBDIR)$(GL_LIB) $(OBJECTS)
clean :
purge
delete *.obj;*
vbo_context.obj : vbo_context.c
vbo_exec.obj : vbo_exec.c
vbo_exec_api.obj : vbo_exec_api.c
vbo_exec_array.obj : vbo_exec_array.c
vbo_exec_draw.obj : vbo_exec_draw.c
vbo_exec_eval.obj : vbo_exec_eval.c
vbo_rebase.obj : vbo_rebase.c
vbo_save.obj : vbo_save.c
vbo_save_api.obj : vbo_save_api.c
vbo_save_draw.obj : vbo_save_draw.c
vbo_save_loopback.obj : vbo_save_loopback.c
vbo_split.obj : vbo_split.c
vbo_split_copy.obj : vbo_split_copy.c
vbo_split_inplace.obj : vbo_split_inplace.c

41
src/mesa/x86/mmx_blend.S
View file

@ -1,4 +1,4 @@
;
/*
* Written by José Fonseca <j_r_fonseca@yahoo.co.uk>
*/
@ -240,7 +240,9 @@ TWO(PUNPCKHDQ ( MA2, MA2 )) /* pa2 | pa2 | pa
ONE(MOVD ( MSS, REGIND(rgba) )) /* | | | | sa1 | sb1 | sg1 | sr1 */ ;\
TWO(MOVQ ( MSS, REGIND(rgba) )) /* sa2 | sb2 | sg2 | sr2 | sa1 | sb1 | sg1 | sr1 */
/* Kevin F. Quinn <kevquinn@gentoo.org> 2 July 2006
* Replace data segment constants with text-segment
* constants (via pushl/movq)
SEG_DATA
ALIGNDATA8
@ -249,6 +251,11 @@ const_0080:
const_80:
D_LONG 0x80808080, 0x80808080
*/
#define const_0080_l 0x00800080
#define const_0080_h 0x00800080
#define const_80_l 0x80808080
#define const_80_h 0x80808080
SEG_TEXT
@ -302,8 +309,16 @@ TWO(MOVQ ( MM1, REGIND(rgba) ))
#define TAG(x) CONCAT(x,_min)
#define LLTAG(x) LLBL2(x,_min)
/* Kevin F. Quinn 2nd July 2006
* Replace data segment constants with text-segment instructions
#define INIT \
MOVQ ( CONTENT(const_80), MM7 ) /* 0x80| 0x80| 0x80| 0x80| 0x80| 0x80| 0x80| 0x80*/
MOVQ ( CONTENT(const_80), MM7 )
*/
#define INIT \
PUSH_L ( CONST(const_80_h) ) /* 0x80| 0x80| 0x80| 0x80| 0x80| 0x80| 0x80| 0x80*/ ;\
PUSH_L ( CONST(const_80_l) ) ;\
MOVQ ( REGIND(ESP), MM7 ) ;\
ADD_L ( CONST(8), ESP)
#define MAIN( rgba, dest ) \
GMB_LOAD( rgba, dest, MM1, MM2 ) ;\
@ -326,8 +341,16 @@ TWO(MOVQ ( MM1, REGIND(rgba) ))
#define TAG(x) CONCAT(x,_max)
#define LLTAG(x) LLBL2(x,_max)
/* Kevin F. Quinn 2nd July 2006
* Replace data segment constants with text-segment instructions
#define INIT \
MOVQ ( CONTENT(const_80), MM7 ) /* 0x80| 0x80| 0x80| 0x80| 0x80| 0x80| 0x80| 0x80*/
MOVQ ( CONTENT(const_80), MM7 )
*/
#define INIT \
PUSH_L ( CONST(const_80_l) ) /* 0x80| 0x80| 0x80| 0x80| 0x80| 0x80| 0x80| 0x80*/ ;\
PUSH_L ( CONST(const_80_h) ) ;\
MOVQ ( REGIND(ESP), MM7 ) ;\
ADD_L ( CONST(8), ESP)
#define MAIN( rgba, dest ) \
GMB_LOAD( rgba, dest, MM1, MM2 ) ;\
@ -350,9 +373,17 @@ TWO(MOVQ ( MM1, REGIND(rgba) ))
#define TAG(x) CONCAT(x,_modulate)
#define LLTAG(x) LLBL2(x,_modulate)
/* Kevin F. Quinn 2nd July 2006
* Replace data segment constants with text-segment instructions
#define INIT \
MOVQ ( CONTENT(const_0080), MM7 )
*/
#define INIT \
PXOR ( MM0, MM0 ) /* 0x0000 | 0x0000 | 0x0000 | 0x0000 */ ;\
MOVQ ( CONTENT(const_0080), MM7 ) /* 0x0080 | 0x0080 | 0x0080 | 0x0080 */
PUSH_L ( CONST(const_0080_l) ) /* 0x0080 | 0x0080 | 0x0080 | 0x0080 */ ;\
PUSH_L ( CONST(const_0080_h) ) ;\
MOVQ ( REGIND(ESP), MM7 ) ;\
ADD_L ( CONST(8), ESP)
#define MAIN( rgba, dest ) \
GMB_LOAD( rgba, dest, MM1, MM2 ) ;\

86
src/mesa/x86/read_rgba_span_x86.S
View file

@ -32,6 +32,8 @@
.file "read_rgba_span_x86.S"
#if !defined(__DJGPP__) && !defined(__MINGW32__) /* this one cries for assyntax.h */
/* Kevin F. Quinn 2nd July 2006
* Replace data segment constants with text-segment instructions
.section .rodata
.align 16
.type mask, @object
@ -45,6 +47,19 @@ mask:
.long 0x00ff0000
.long 0x00ff0000
.long 0x00ff0000
*/
#define LOAD_MASK(mvins,m1,m2) \
pushl $0xff00ff00 ;\
pushl $0xff00ff00 ;\
pushl $0xff00ff00 ;\
pushl $0xff00ff00 ;\
mvins (%esp), m1 ;\
pushl $0x00ff0000 ;\
pushl $0x00ff0000 ;\
pushl $0x00ff0000 ;\
pushl $0x00ff0000 ;\
mvins (%esp), m2 ;\
addl $32, %esp
/* I implemented these as macros because the appear in quite a few places,
@ -84,8 +99,12 @@ _generic_read_RGBA_span_BGRA8888_REV_MMX:
#ifdef USE_INNER_EMMS
emms
#endif
/* Kevin F. Quinn 2nd July 2006
* Replace data segment constants with text-segment instructions
movq mask, %mm1
movq mask+16, %mm2
*/
LOAD_MASK(movq,%mm1,%mm2)
movl 8(%esp), %ebx /* source pointer */
movl 16(%esp), %edx /* number of pixels to copy */
@ -182,8 +201,12 @@ _generic_read_RGBA_span_BGRA8888_REV_SSE:
#ifdef USE_INNER_EMMS
emms
#endif
/* Kevin F. Quinn 2nd July 2006
* Replace data segment constants with text-segment instructions
movq mask, %mm1
movq mask+16, %mm2
*/
LOAD_MASK(movq,%mm1,%mm2)
movl 16(%esp), %ebx /* source pointer */
movl 24(%esp), %edx /* number of pixels to copy */
@ -341,8 +364,12 @@ _generic_read_RGBA_span_BGRA8888_REV_SSE2:
pushl %esi
pushl %ebx
/* Kevin F. Quinn 2nd July 2006
* Replace data segment constants with text-segment instructions
movdqa mask, %xmm1
movdqa mask+16, %xmm2
*/
LOAD_MASK(movdqa,%xmm1,%xmm2)
movl 12(%esp), %ebx /* source pointer */
movl 20(%esp), %edx /* number of pixels to copy */
@ -464,6 +491,10 @@ _generic_read_RGBA_span_BGRA8888_REV_SSE2:
/* Kevin F. Quinn 2nd July 2006
* Replace data segment constants with text-segment instructions
*/
#if 0
.section .rodata
.align 16
@ -510,6 +541,26 @@ scale:
alpha: .long 0x00000000
.long 0x00ff0000
#endif
#define MASK_565_L 0x07e0f800
#define MASK_565_H 0x0000001f
#define SCALE_ADJUST 5
#if SCALE_ADJUST == 5
#define PRESCALE_L 0x00100001
#define PRESCALE_H 0x00000200
#define SCALE_L 0x40C620E8
#define SCALE_H 0x0000839d
#elif SCALE_ADJUST == 0
#define PRESCALE_L 0x00200001
#define PRESCALE_H 0x00000800
#define SCALE_L 0x01040108
#define SCALE_H 0x00000108
#else
#error SCALE_ADJUST must either be 5 or 0.
#endif
#define ALPHA_L 0x00000000
#define ALPHA_H 0x00ff0000
/**
* MMX optimized version of the RGB565 to RGBA copy routine.
@ -530,9 +581,25 @@ _generic_read_RGBA_span_RGB565_MMX:
movl 8(%esp), %edx /* destination pointer */
movl 12(%esp), %ecx /* number of pixels to copy */
/* Kevin F. Quinn 2nd July 2006
* Replace data segment constants with text-segment instructions
movq mask_565, %mm5
movq prescale, %mm6
movq scale, %mm7
*/
pushl MASK_565_H
pushl MASK_565_L
movq (%esp), %mm5
pushl PRESCALE_H
pushl PRESCALE_L
movq (%esp), %mm6
pushl SCALE_H
pushl SCALE_L
movq (%esp), %mm7
pushl ALPHA_H
pushl ALPHA_L
movq (%esp), %mm3
addl $32,%esp
sarl $2, %ecx
jle .L01 /* Bail early if the count is negative. */
@ -581,8 +648,13 @@ _generic_read_RGBA_span_RGB565_MMX:
/* Always set the alpha value to 0xff.
*/
/* Kevin F. Quinn 2nd July 2006
* Replace data segment constants with text-segment instructions
por alpha, %mm0
por alpha, %mm2
*/
por %mm3, %mm0
por %mm3, %mm2
/* Pack the 16-bit values to 8-bit values and store the converted
@ -609,8 +681,13 @@ _generic_read_RGBA_span_RGB565_MMX:
pmulhuw %mm7, %mm0
pmulhuw %mm7, %mm2
/* Kevin F. Quinn 2nd July 2006
* Replace data segment constants with text-segment instructions
por alpha, %mm0
por alpha, %mm2
*/
por %mm3, %mm0
por %mm3, %mm2
packuswb %mm2, %mm0
@ -647,8 +724,13 @@ _generic_read_RGBA_span_RGB565_MMX:
pmulhuw %mm7, %mm0
pmulhuw %mm7, %mm2
/* Kevin F. Quinn 2nd July 2006
* Replace data segment constants with text-segment instructions
por alpha, %mm0
por alpha, %mm2
*/
por %mm3, %mm0
por %mm3, %mm2
packuswb %mm2, %mm0
@ -675,7 +757,11 @@ _generic_read_RGBA_span_RGB565_MMX:
#endif
pmulhuw %mm7, %mm0
/* Kevin F. Quinn 2nd July 2006
* Replace data segment constants with text-segment instructions
por alpha, %mm0
*/
por %mm3, %mm0
packuswb %mm0, %mm0