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nak/sm20: Add more memory ops
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34616>
This commit is contained in:
Faith Ekstrand
Marge Bot
parent
84f18f31ad
commit
5a140e7c3e
1 changed files with 179 additions and 0 deletions
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@ -1862,6 +1862,119 @@ impl SM20Op for OpSt {
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}
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}
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fn atom_src_as_ssa(
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b: &mut LegalizeBuilder,
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src: Src,
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atom_type: AtomType,
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) -> SSARef {
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if let Some(ssa) = src.as_ssa() {
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return *ssa;
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}
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let tmp;
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if atom_type.bits() == 32 {
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tmp = b.alloc_ssa(RegFile::GPR, 1);
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b.copy_to(tmp.into(), 0.into());
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} else {
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debug_assert!(atom_type.bits() == 64);
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tmp = b.alloc_ssa(RegFile::GPR, 2);
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b.copy_to(tmp[0].into(), 0.into());
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b.copy_to(tmp[1].into(), 0.into());
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}
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tmp
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}
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impl SM20Op for OpAtom {
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fn legalize(&mut self, b: &mut LegalizeBuilder) {
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if self.atom_op == AtomOp::CmpExch(AtomCmpSrc::Separate) {
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let cmpr = atom_src_as_ssa(b, self.cmpr, self.atom_type);
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let data = atom_src_as_ssa(b, self.data, self.atom_type);
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let mut cmpr_data = Vec::new();
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cmpr_data.extend_from_slice(&cmpr);
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cmpr_data.extend_from_slice(&data);
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let cmpr_data = SSARef::try_from(cmpr_data).unwrap();
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self.cmpr = 0.into();
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self.data = cmpr_data.into();
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self.atom_op = AtomOp::CmpExch(AtomCmpSrc::Packed);
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}
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legalize_ext_instr(self, b);
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}
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fn encode(&self, e: &mut SM20Encoder<'_>) {
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let MemSpace::Global(addr_type) = self.mem_space else {
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panic!("SM20 only supports global atomics");
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};
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assert!(addr_type == MemAddrType::A64);
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if self.dst.is_none() {
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e.set_opcode(SM20Unit::Mem, 0x1);
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} else {
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e.set_opcode(SM20Unit::Mem, 0x11);
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}
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let op = match self.atom_op {
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AtomOp::Add => 0_u8,
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AtomOp::Min => 1_u8,
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AtomOp::Max => 2_u8,
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AtomOp::Inc => 3_u8,
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AtomOp::Dec => 4_u8,
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AtomOp::And => 5_u8,
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AtomOp::Or => 6_u8,
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AtomOp::Xor => 7_u8,
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AtomOp::Exch => 8_u8,
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AtomOp::CmpExch(_) => 9_u8,
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};
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e.set_field(5..9, op);
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let typ = match self.atom_type {
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AtomType::F16x2 => panic!("Unsupported atomic type"),
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// AtomType::U8 => 0x0_u8,
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// AtomType::I8 => 0x1_u8,
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// AtomType::U16 => 0x2_u8,
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// AtomType::I16 => 0x3_u8,
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AtomType::U32 => 0x4_u8,
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AtomType::U64 => 0x5_u8,
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//AtomType::U128 => 0x6_u8,
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AtomType::I32 => 0x7_u8,
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AtomType::I64 => 0x8_u8,
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//AtomType::I128 => 0x9_u8,
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//AtomType::F16 => 0xa_u8,
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AtomType::F64 => 0xc_u8,
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AtomType::F32 => 0xd_u8,
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};
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e.set_field(9..10, typ & 0x1);
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e.set_field(59..62, typ >> 1);
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e.set_reg_src(20..26, self.addr);
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e.set_reg_src(14..20, self.data);
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if self.dst.is_none() {
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e.set_field(26..58, self.addr_offset);
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} else {
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e.set_dst(43..49, self.dst);
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e.set_field(26..43, self.addr_offset & 0x1ffff);
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e.set_field(55..58, self.addr_offset >> 17);
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}
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if let AtomOp::CmpExch(cmp_src) = self.atom_op {
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// The hardware expects the first source to be packed and then the
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// second source to be the top half of the first.
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assert!(cmp_src == AtomCmpSrc::Packed);
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let cmpr_data = self.data.src_ref.as_reg().unwrap();
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assert!(cmpr_data.comps() % 2 == 0);
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let data_comps = cmpr_data.comps() / 2;
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let data_idx = cmpr_data.base_idx() + u32::from(data_comps);
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let data = RegRef::new(cmpr_data.file(), data_idx, data_comps);
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e.set_reg_src(49..55, data.into());
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} else if !self.dst.is_none() {
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e.set_reg_src(49..55, 0.into());
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}
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}
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}
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impl SM20Op for OpALd {
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fn legalize(&mut self, b: &mut LegalizeBuilder) {
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legalize_ext_instr(self, b);
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@ -1940,6 +2053,69 @@ impl SM20Op for OpIpa {
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}
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}
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impl SM20Op for OpCCtl {
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fn legalize(&mut self, b: &mut LegalizeBuilder) {
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legalize_ext_instr(self, b);
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}
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fn encode(&self, e: &mut SM20Encoder<'_>) {
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let op = match self.mem_space {
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MemSpace::Global(MemAddrType::A32) => 0x26,
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MemSpace::Global(MemAddrType::A64) => 0x27,
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MemSpace::Local => panic!("cctl does not support local"),
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MemSpace::Shared => 0x34,
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};
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e.set_opcode(SM20Unit::Mem, op);
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e.set_field(
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5..10,
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match self.op {
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CCtlOp::Qry1 => 0_u8,
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CCtlOp::PF1 => 1_u8,
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CCtlOp::PF1_5 => 2_u8,
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CCtlOp::PF2 => 3_u8,
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CCtlOp::WB => 4_u8,
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CCtlOp::IV => 5_u8,
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CCtlOp::IVAll => 6_u8,
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CCtlOp::RS => 7_u8,
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CCtlOp::WBAll => 8_u8,
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CCtlOp::RSLB => 9_u8,
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CCtlOp::IVAllP | CCtlOp::WBAllP => {
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panic!("cctl{} is not supported on SM20", self.op);
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}
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},
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);
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e.set_dst(14..20, Dst::None);
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e.set_reg_src(20..26, self.addr);
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e.set_field(26..28, 0); // 1: .u, 2: .c: 3: .i
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assert!(self.addr_offset % 4 == 0);
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if matches!(self.mem_space, MemSpace::Global(_)) {
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e.set_field(28..58, self.addr_offset / 4);
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} else {
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e.set_field(28..50, self.addr_offset / 4);
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}
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}
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}
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impl SM20Op for OpMemBar {
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fn legalize(&mut self, _b: &mut LegalizeBuilder) {
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// Nothing to do
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}
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fn encode(&self, e: &mut SM20Encoder<'_>) {
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e.set_opcode(SM20Unit::Mem, 0x38);
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e.set_field(
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5..7,
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match self.scope {
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MemScope::CTA => 0_u8,
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MemScope::GPU => 1_u8,
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MemScope::System => 2_u8,
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},
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);
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}
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}
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impl SM20Encoder<'_> {
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fn set_rel_offset(&mut self, range: Range<usize>, label: &Label) {
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let ip = u32::try_from(self.ip).unwrap();
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@ -2199,9 +2375,12 @@ macro_rules! as_sm20_op_match {
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Op::Ld(op) => op,
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Op::Ldc(op) => op,
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Op::St(op) => op,
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Op::Atom(op) => op,
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Op::ALd(op) => op,
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Op::ASt(op) => op,
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Op::Ipa(op) => op,
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Op::CCtl(op) => op,
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Op::MemBar(op) => op,
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Op::Bra(op) => op,
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Op::SSy(op) => op,
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Op::Sync(op) => op,
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