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i965: Set MOCS for push constant buffers on Haswell and Gfx9+

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We set MOCS on Ivybridge/Baytrail, but not Haswell, and not Skylake
and later.  We shoud set it everywhere.  While we're at it, we also
set it for null constant buffers, so that we aren't programming a 0
MOCS, to allow us to add some safeguards against that.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
This commit is contained in:
Kenneth Graunke 2021-10-19 15:18:09 -07:00 • committed by Marge Bot
parent d0e356b333
commit 59f53b07c4
1 changed files with 7 additions and 2 deletions
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9
src/mesa/drivers/dri/i965/genX_state_upload.c
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@ -3097,6 +3097,12 @@ genX(upload_push_constant_packets)(struct brw_context *brw)
brw_batch_emit(brw, GENX(3DSTATE_CONSTANT_VS), pkt) {
pkt._3DCommandSubOpcode = push_constant_opcodes[stage];
#if GFX_VER >= 9
pkt.MOCS = mocs;
#elif GFX_VER < 8
/* MOCS is MBZ on Gfx8 so we skip it there */
pkt.ConstantBody.MOCS = mocs;
#endif
if (stage_state->prog_data) {
#if GFX_VERx10 >= 75
/* The Skylake PRM contains the following restriction:
@ -3157,8 +3163,7 @@ genX(upload_push_constant_packets)(struct brw_context *brw)
}
#else
pkt.ConstantBody.ReadLength[0] = stage_state->push_const_size;
pkt.ConstantBody.Buffer[0].offset =
stage_state->push_const_offset | mocs;
pkt.ConstantBody.Buffer[0].offset = stage_state->push_const_offset;
#endif
}
}