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r300: add FP suffix to the current class list
We will add a new one for vp in a next commit Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com> Reviewed-by: Filip Gawin <filip@gawin.net> Tested-by: Filip Gawin <filip@gawin.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19618>
This commit is contained in:
Pavel Ondračka
Marge Bot
parent
024a8d8bda
commit
59e22d9d35
2 changed files with 58 additions and 58 deletions
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@ -33,134 +33,134 @@
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#define DBG(...) do { if (VERBOSE) fprintf(stderr, __VA_ARGS__); } while(0)
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const struct rc_class rc_class_list [] = {
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{RC_REG_CLASS_SINGLE, 3,
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const struct rc_class rc_class_list_fp [] = {
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{RC_REG_CLASS_FP_SINGLE, 3,
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{RC_MASK_X,
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RC_MASK_Y,
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RC_MASK_Z,
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RC_MASK_NONE,
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RC_MASK_NONE,
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RC_MASK_NONE}},
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{RC_REG_CLASS_DOUBLE, 3,
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{RC_REG_CLASS_FP_DOUBLE, 3,
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{RC_MASK_X | RC_MASK_Y,
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RC_MASK_X | RC_MASK_Z,
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RC_MASK_Y | RC_MASK_Z,
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RC_MASK_NONE,
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RC_MASK_NONE,
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RC_MASK_NONE}},
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{RC_REG_CLASS_TRIPLE, 1,
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{RC_REG_CLASS_FP_TRIPLE, 1,
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{RC_MASK_X | RC_MASK_Y | RC_MASK_Z,
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RC_MASK_NONE,
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RC_MASK_NONE,
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RC_MASK_NONE,
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RC_MASK_NONE,
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RC_MASK_NONE}},
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{RC_REG_CLASS_ALPHA, 1,
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{RC_REG_CLASS_FP_ALPHA, 1,
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{RC_MASK_W,
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RC_MASK_NONE,
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RC_MASK_NONE,
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RC_MASK_NONE,
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RC_MASK_NONE,
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RC_MASK_NONE}},
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{RC_REG_CLASS_SINGLE_PLUS_ALPHA, 3,
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{RC_REG_CLASS_FP_SINGLE_PLUS_ALPHA, 3,
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{RC_MASK_X | RC_MASK_W,
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RC_MASK_Y | RC_MASK_W,
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RC_MASK_Z | RC_MASK_W,
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RC_MASK_NONE,
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RC_MASK_NONE,
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RC_MASK_NONE}},
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{RC_REG_CLASS_DOUBLE_PLUS_ALPHA, 3,
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{RC_REG_CLASS_FP_DOUBLE_PLUS_ALPHA, 3,
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{RC_MASK_X | RC_MASK_Y | RC_MASK_W,
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RC_MASK_X | RC_MASK_Z | RC_MASK_W,
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RC_MASK_Y | RC_MASK_Z | RC_MASK_W,
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RC_MASK_NONE,
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RC_MASK_NONE,
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RC_MASK_NONE}},
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{RC_REG_CLASS_TRIPLE_PLUS_ALPHA, 1,
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{RC_REG_CLASS_FP_TRIPLE_PLUS_ALPHA, 1,
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{RC_MASK_X | RC_MASK_Y | RC_MASK_Z | RC_MASK_W,
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RC_MASK_NONE,
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RC_MASK_NONE,
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RC_MASK_NONE,
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RC_MASK_NONE,
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RC_MASK_NONE}},
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{RC_REG_CLASS_X, 1,
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{RC_REG_CLASS_FP_X, 1,
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{RC_MASK_X,
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RC_MASK_NONE,
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RC_MASK_NONE,
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RC_MASK_NONE,
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RC_MASK_NONE,
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RC_MASK_NONE}},
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{RC_REG_CLASS_Y, 1,
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{RC_REG_CLASS_FP_Y, 1,
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{RC_MASK_Y,
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RC_MASK_NONE,
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RC_MASK_NONE,
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RC_MASK_NONE,
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RC_MASK_NONE,
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RC_MASK_NONE}},
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{RC_REG_CLASS_Z, 1,
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{RC_REG_CLASS_FP_Z, 1,
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{RC_MASK_Z,
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RC_MASK_NONE,
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RC_MASK_NONE,
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RC_MASK_NONE,
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RC_MASK_NONE,
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RC_MASK_NONE}},
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{RC_REG_CLASS_XY, 1,
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{RC_REG_CLASS_FP_XY, 1,
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{RC_MASK_X | RC_MASK_Y,
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RC_MASK_NONE,
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RC_MASK_NONE,
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RC_MASK_NONE,
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RC_MASK_NONE,
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RC_MASK_NONE}},
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{RC_REG_CLASS_YZ, 1,
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{RC_REG_CLASS_FP_YZ, 1,
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{RC_MASK_Y | RC_MASK_Z,
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RC_MASK_NONE,
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RC_MASK_NONE,
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RC_MASK_NONE,
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RC_MASK_NONE,
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RC_MASK_NONE}},
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{RC_REG_CLASS_XZ, 1,
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{RC_REG_CLASS_FP_XZ, 1,
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{RC_MASK_X | RC_MASK_Z,
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RC_MASK_NONE,
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RC_MASK_NONE,
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RC_MASK_NONE,
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RC_MASK_NONE,
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RC_MASK_NONE}},
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{RC_REG_CLASS_XW, 1,
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{RC_REG_CLASS_FP_XW, 1,
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{RC_MASK_X | RC_MASK_W,
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RC_MASK_NONE,
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RC_MASK_NONE,
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RC_MASK_NONE,
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RC_MASK_NONE,
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RC_MASK_NONE}},
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{RC_REG_CLASS_YW, 1,
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{RC_REG_CLASS_FP_YW, 1,
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{RC_MASK_Y | RC_MASK_W,
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RC_MASK_NONE,
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RC_MASK_NONE,
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RC_MASK_NONE,
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RC_MASK_NONE,
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RC_MASK_NONE}},
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{RC_REG_CLASS_ZW, 1,
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{RC_REG_CLASS_FP_ZW, 1,
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{RC_MASK_Z | RC_MASK_W,
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RC_MASK_NONE,
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RC_MASK_NONE,
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RC_MASK_NONE,
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RC_MASK_NONE,
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RC_MASK_NONE}},
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{RC_REG_CLASS_XYW, 1,
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{RC_REG_CLASS_FP_XYW, 1,
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{RC_MASK_X | RC_MASK_Y | RC_MASK_W,
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RC_MASK_NONE,
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RC_MASK_NONE,
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RC_MASK_NONE,
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RC_MASK_NONE,
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RC_MASK_NONE}},
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{RC_REG_CLASS_YZW, 1,
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{RC_REG_CLASS_FP_YZW, 1,
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{RC_MASK_Y | RC_MASK_Z | RC_MASK_W,
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RC_MASK_NONE,
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RC_MASK_NONE,
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RC_MASK_NONE,
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RC_MASK_NONE,
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RC_MASK_NONE}},
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{RC_REG_CLASS_XZW, 1,
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{RC_REG_CLASS_FP_XZW, 1,
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{RC_MASK_X | RC_MASK_Z | RC_MASK_W,
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RC_MASK_NONE,
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RC_MASK_NONE,
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@ -222,7 +222,7 @@ int rc_find_class(
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unsigned int max_writemask_count)
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{
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unsigned int i;
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for (i = 0; i < RC_REG_CLASS_COUNT; i++) {
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for (i = 0; i < RC_REG_CLASS_FP_COUNT; i++) {
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unsigned int j;
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if (classes[i].WritemaskCount > max_writemask_count) {
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continue;
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@ -325,24 +325,24 @@ void rc_init_regalloc_state(struct rc_regalloc_state *s)
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*
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* For example:
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* q_values[0][2] is 3, because a register from class 2
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* (RC_REG_CLASS_TRIPLE) may conflict with at most 3 registers from
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* class 0 (RC_REG_CLASS_SINGLE) e.g. T0.xyz conflicts with T0.x, T0.y,
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* (RC_REG_CLASS_FP_TRIPLE) may conflict with at most 3 registers from
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* class 0 (RC_REG_CLASS_FP_SINGLE) e.g. T0.xyz conflicts with T0.x, T0.y,
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* and T0.z.
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*
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* q_values[2][0] is 1, because a register from class 0
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* (RC_REG_CLASS_SINGLE) may conflict with at most 1 register from
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* class 2 (RC_REG_CLASS_TRIPLE) e.g. T0.x conflicts with T0.xyz
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* (RC_REG_CLASS_FP_SINGLE) may conflict with at most 1 register from
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* class 2 (RC_REG_CLASS_FP_TRIPLE) e.g. T0.x conflicts with T0.xyz
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*
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* The q values for each register class [row] will never be greater
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* than the maximum number of writemask combinations for that class.
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*
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* For example:
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*
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* Class 2 (RC_REG_CLASS_TRIPLE) only has 1 writemask combination,
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* so no value in q_values[2][0..RC_REG_CLASS_COUNT] will be greater
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* Class 2 (RC_REG_CLASS_FP_TRIPLE) only has 1 writemask combination,
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* so no value in q_values[2][0..RC_REG_CLASS_FP_COUNT] will be greater
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* than 1.
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*/
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const unsigned q_values[RC_REG_CLASS_COUNT][RC_REG_CLASS_COUNT] = {
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const unsigned q_values[RC_REG_CLASS_FP_COUNT][RC_REG_CLASS_FP_COUNT] = {
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{1, 2, 3, 0, 1, 2, 3, 1, 1, 1, 2, 2, 2, 1, 1, 1, 2, 2, 2},
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{2, 3, 3, 0, 2, 3, 3, 2, 2, 2, 3, 3, 3, 2, 2, 2, 3, 3, 3},
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{1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1},
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@ -368,11 +368,11 @@ void rc_init_regalloc_state(struct rc_regalloc_state *s)
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s->regs = ra_alloc_reg_set(NULL, R500_PFS_NUM_TEMP_REGS * RC_MASK_XYZW,
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true);
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s->class_list = rc_class_list;
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s->class_list = rc_class_list_fp;
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/* Create the register classes */
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for (i = 0; i < RC_REG_CLASS_COUNT; i++) {
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const struct rc_class *class = &rc_class_list[i];
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for (i = 0; i < RC_REG_CLASS_FP_COUNT; i++) {
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const struct rc_class *class = &rc_class_list_fp[i];
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s->classes[class->ID] = ra_alloc_reg_class(s->regs);
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/* Assign registers to the classes */
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@ -386,15 +386,15 @@ void rc_init_regalloc_state(struct rc_regalloc_state *s)
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}
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/* Set the q values. The q_values array is indexed based on
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* the rc_reg_class ID (RC_REG_CLASS_*) which might be
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* the rc_reg_class ID (RC_REG_CLASS_FP_*) which might be
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* different than the ID assigned to that class by ra.
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* This why we need to manually construct this list.
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*/
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ra_q_values = MALLOC(RC_REG_CLASS_COUNT * sizeof(unsigned *));
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ra_q_values = MALLOC(RC_REG_CLASS_FP_COUNT * sizeof(unsigned *));
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for (i = 0; i < RC_REG_CLASS_COUNT; i++) {
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ra_q_values[i] = MALLOC(RC_REG_CLASS_COUNT * sizeof(unsigned));
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for (j = 0; j < RC_REG_CLASS_COUNT; j++) {
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for (i = 0; i < RC_REG_CLASS_FP_COUNT; i++) {
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ra_q_values[i] = MALLOC(RC_REG_CLASS_FP_COUNT * sizeof(unsigned));
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for (j = 0; j < RC_REG_CLASS_FP_COUNT; j++) {
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ra_q_values[i][j] = q_values[i][j];
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}
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}
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@ -404,7 +404,7 @@ void rc_init_regalloc_state(struct rc_regalloc_state *s)
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ra_set_finalize(s->regs, ra_q_values);
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for (i = 0; i < RC_REG_CLASS_COUNT; i++) {
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for (i = 0; i < RC_REG_CLASS_FP_COUNT; i++) {
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FREE(ra_q_values[i]);
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}
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FREE(ra_q_values);
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@ -37,31 +37,31 @@
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struct ra_regs;
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enum rc_reg_class {
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RC_REG_CLASS_SINGLE,
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RC_REG_CLASS_DOUBLE,
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RC_REG_CLASS_TRIPLE,
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RC_REG_CLASS_ALPHA,
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RC_REG_CLASS_SINGLE_PLUS_ALPHA,
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RC_REG_CLASS_DOUBLE_PLUS_ALPHA,
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RC_REG_CLASS_TRIPLE_PLUS_ALPHA,
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RC_REG_CLASS_X,
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RC_REG_CLASS_Y,
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RC_REG_CLASS_Z,
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RC_REG_CLASS_XY,
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RC_REG_CLASS_YZ,
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RC_REG_CLASS_XZ,
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RC_REG_CLASS_XW,
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RC_REG_CLASS_YW,
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RC_REG_CLASS_ZW,
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RC_REG_CLASS_XYW,
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RC_REG_CLASS_YZW,
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RC_REG_CLASS_XZW,
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RC_REG_CLASS_COUNT
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RC_REG_CLASS_FP_SINGLE,
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RC_REG_CLASS_FP_DOUBLE,
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RC_REG_CLASS_FP_TRIPLE,
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RC_REG_CLASS_FP_ALPHA,
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RC_REG_CLASS_FP_SINGLE_PLUS_ALPHA,
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RC_REG_CLASS_FP_DOUBLE_PLUS_ALPHA,
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RC_REG_CLASS_FP_TRIPLE_PLUS_ALPHA,
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RC_REG_CLASS_FP_X,
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RC_REG_CLASS_FP_Y,
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RC_REG_CLASS_FP_Z,
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RC_REG_CLASS_FP_XY,
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RC_REG_CLASS_FP_YZ,
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RC_REG_CLASS_FP_XZ,
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RC_REG_CLASS_FP_XW,
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RC_REG_CLASS_FP_YW,
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RC_REG_CLASS_FP_ZW,
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RC_REG_CLASS_FP_XYW,
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RC_REG_CLASS_FP_YZW,
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RC_REG_CLASS_FP_XZW,
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RC_REG_CLASS_FP_COUNT
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};
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struct rc_regalloc_state {
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struct ra_regs *regs;
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struct ra_class *classes[RC_REG_CLASS_COUNT];
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struct ra_class *classes[RC_REG_CLASS_FP_COUNT];
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const struct rc_class *class_list;
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};
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