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radeonsi: program VGT_SHADER_STAGES_EN for tessellation
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
This commit is contained in:
parent
d9d0de4d28
commit
59b3556f4c
4 changed files with 45 additions and 23 deletions
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@ -36,6 +36,7 @@
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static void si_destroy_context(struct pipe_context *context)
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{
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struct si_context *sctx = (struct si_context *)context;
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int i;
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si_release_all_descriptors(sctx);
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@ -48,8 +49,8 @@ static void si_destroy_context(struct pipe_context *context)
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si_pm4_free_state(sctx, sctx->init_config, ~0);
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si_pm4_delete_state(sctx, gs_rings, sctx->gs_rings);
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si_pm4_delete_state(sctx, gs_onoff, sctx->gs_on);
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si_pm4_delete_state(sctx, gs_onoff, sctx->gs_off);
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for (i = 0; i < Elements(sctx->vgt_shader_config); i++)
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si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
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if (sctx->pstipple_sampler_state)
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sctx->b.b.delete_sampler_state(&sctx->b.b, sctx->pstipple_sampler_state);
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@ -196,11 +196,12 @@ struct si_context {
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/* With rasterizer discard, there doesn't have to be a pixel shader.
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* In that case, we bind this one: */
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void *dummy_pixel_shader;
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struct si_pm4_state *gs_on;
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struct si_pm4_state *gs_off;
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struct si_pm4_state *gs_rings;
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struct r600_atom cache_flush;
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struct pipe_constant_buffer null_const_buf; /* used for set_constant_buffer(NULL) on CIK */
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/* VGT states. */
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struct si_pm4_state *vgt_shader_config[4];
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struct si_pm4_state *gs_rings;
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struct pipe_resource *esgs_ring;
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struct pipe_resource *gsvs_ring;
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@ -105,7 +105,7 @@ union si_state {
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struct si_pm4_state *es;
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struct si_pm4_state *gs;
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struct si_pm4_state *gs_rings;
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struct si_pm4_state *gs_onoff;
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struct si_pm4_state *vgt_shader_config;
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struct si_pm4_state *vs;
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struct si_pm4_state *ps;
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struct si_pm4_state *spi;
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@ -922,6 +922,41 @@ static void si_update_spi_tmpring_size(struct si_context *sctx)
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S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
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}
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static void si_update_vgt_shader_config(struct si_context *sctx)
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{
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/* Calculate the index of the config.
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* 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
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unsigned index = 2*!!sctx->tes_shader + !!sctx->gs_shader;
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struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
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if (!*pm4) {
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uint32_t stages = 0;
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*pm4 = CALLOC_STRUCT(si_pm4_state);
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if (sctx->tes_shader) {
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stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
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S_028B54_HS_EN(1);
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if (sctx->gs_shader)
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stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
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S_028B54_GS_EN(1) |
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S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
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else
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stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
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} else if (sctx->gs_shader) {
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stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
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S_028B54_GS_EN(1) |
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S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
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}
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si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
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if (!sctx->gs_shader)
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si_pm4_set_reg(*pm4, R_028A40_VGT_GS_MODE, 0);
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}
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si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
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}
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void si_update_shaders(struct si_context *sctx)
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{
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struct pipe_context *ctx = (struct pipe_context*)sctx;
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@ -948,34 +983,19 @@ void si_update_shaders(struct si_context *sctx)
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sctx->gs_shader->gs_max_out_vertices *
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sctx->gs_shader->info.num_outputs * 16,
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64, true, true, 4, 16);
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if (!sctx->gs_on) {
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sctx->gs_on = CALLOC_STRUCT(si_pm4_state);
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si_pm4_set_reg(sctx->gs_on, R_028B54_VGT_SHADER_STAGES_EN,
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S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
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S_028B54_GS_EN(1) |
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S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER));
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}
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si_pm4_bind_state(sctx, gs_onoff, sctx->gs_on);
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} else {
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si_shader_select(ctx, sctx->vs_shader);
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si_pm4_bind_state(sctx, vs, sctx->vs_shader->current->pm4);
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sctx->b.streamout.stride_in_dw = sctx->vs_shader->so.stride;
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if (!sctx->gs_off) {
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sctx->gs_off = CALLOC_STRUCT(si_pm4_state);
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si_pm4_set_reg(sctx->gs_off, R_028A40_VGT_GS_MODE, 0);
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si_pm4_set_reg(sctx->gs_off, R_028B54_VGT_SHADER_STAGES_EN, 0);
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}
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si_pm4_bind_state(sctx, gs_onoff, sctx->gs_off);
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si_pm4_bind_state(sctx, gs_rings, NULL);
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si_pm4_bind_state(sctx, gs, NULL);
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si_pm4_bind_state(sctx, es, NULL);
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}
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si_update_vgt_shader_config(sctx);
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si_shader_select(ctx, sctx->ps_shader);
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if (!sctx->ps_shader->current) {
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