From 59912cd4cfc60dcae340f2ff7c5cbf2c995e933f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Wed, 17 Mar 2021 17:03:07 -0400 Subject: [PATCH] amd/addrlib: add back the incorrect original DCC checking This reduces Mesa-specific changes. is_dcc_supported_by_CB() should protect against getting there. Acked-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/amd/addrlib/src/gfx10/gfx10addrlib.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/amd/addrlib/src/gfx10/gfx10addrlib.cpp b/src/amd/addrlib/src/gfx10/gfx10addrlib.cpp index c227a0260e3..841901524f4 100644 --- a/src/amd/addrlib/src/gfx10/gfx10addrlib.cpp +++ b/src/amd/addrlib/src/gfx10/gfx10addrlib.cpp @@ -384,9 +384,10 @@ ADDR_E_RETURNCODE Gfx10Lib::HwlComputeDccInfo( { ADDR_E_RETURNCODE ret = ADDR_OK; - if (pIn->swizzleMode != ADDR_SW_64KB_Z_X && pIn->swizzleMode != ADDR_SW_64KB_R_X) + if (IsLinear(pIn->swizzleMode) || IsBlock256b(pIn->swizzleMode)) { - // Hardware does not support DCC for this swizzle mode. + // Hardware support dcc for 256 swizzle mode, but address lib will not support it because we only + // select 256 swizzle mode for small surface, and it's not helpful to enable dcc for small surface. ret = ADDR_INVALIDPARAMS; } else if (m_settings.dccUnsup3DSwDis && IsTex3d(pIn->resourceType) && IsDisplaySwizzle(pIn->swizzleMode))