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aco,radv: add aco_is_nir_op_support_packed_math_16bit

Browse source 
To be shared by radeonsi and radv.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25990>
This commit is contained in:
Qiang Yu 2023-11-01 17:27:43 +08:00 • committed by Marge Bot
parent 10367618da
commit 5932990e08
3 changed files with 46 additions and 39 deletions
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41
src/amd/compiler/aco_interface.cpp
View file

@ -436,3 +436,44 @@ aco_is_gpu_supported(const struct radeon_info* info)
/* Does not support compute only cards yet. */
return info->gfx_level >= GFX6 && info->has_graphics;
}
bool
aco_nir_op_supports_packed_math_16bit(const nir_alu_instr* alu)
{
switch (alu->op) {
case nir_op_f2f16: {
nir_shader* shader = nir_cf_node_get_function(&alu->instr.block->cf_node)->function->shader;
unsigned execution_mode = shader->info.float_controls_execution_mode;
return nir_is_rounding_mode_rtz(execution_mode, 16);
}
case nir_op_fadd:
case nir_op_fsub:
case nir_op_fmul:
case nir_op_ffma:
case nir_op_fdiv:
case nir_op_flrp:
case nir_op_fabs:
case nir_op_fneg:
case nir_op_fsat:
case nir_op_fmin:
case nir_op_fmax:
case nir_op_f2f16_rtz:
case nir_op_iabs:
case nir_op_iadd:
case nir_op_iadd_sat:
case nir_op_uadd_sat:
case nir_op_isub:
case nir_op_isub_sat:
case nir_op_usub_sat:
case nir_op_ineg:
case nir_op_imul:
case nir_op_imin:
case nir_op_imax:
case nir_op_umin:
case nir_op_umax: return true;
case nir_op_ishl: /* TODO: in NIR, these have 32bit shift operands */
case nir_op_ishr: /* while Radeon needs 16bit operands when vectorized */
case nir_op_ushr:
default: return false;
}
}

5
src/amd/compiler/aco_interface.h
View file

@ -27,12 +27,13 @@
#include "aco_shader_info.h"
#include "nir.h"
#include "amd_family.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct nir_shader nir_shader;
struct ac_shader_config;
struct aco_shader_info;
struct aco_vs_prolog_info;
@ -100,6 +101,8 @@ uint64_t aco_get_codegen_flags();
bool aco_is_gpu_supported(const struct radeon_info* info);
bool aco_nir_op_supports_packed_math_16bit(const nir_alu_instr* alu);
#ifdef __cplusplus
}
#endif

39
src/amd/vulkan/radv_pipeline.c
View file

@ -489,44 +489,7 @@ opt_vectorize_callback(const nir_instr *instr, const void *_)
if (bit_size != 16)
return 1;
switch (alu->op) {
case nir_op_f2f16: {
nir_shader *shader = nir_cf_node_get_function(&instr->block->cf_node)->function->shader;
unsigned execution_mode = shader->info.float_controls_execution_mode;
return nir_is_rounding_mode_rtz(execution_mode, 16) ? 2 : 1;
}
case nir_op_fadd:
case nir_op_fsub:
case nir_op_fmul:
case nir_op_ffma:
case nir_op_fdiv:
case nir_op_flrp:
case nir_op_fabs:
case nir_op_fneg:
case nir_op_fsat:
case nir_op_fmin:
case nir_op_fmax:
case nir_op_f2f16_rtz:
case nir_op_iabs:
case nir_op_iadd:
case nir_op_iadd_sat:
case nir_op_uadd_sat:
case nir_op_isub:
case nir_op_isub_sat:
case nir_op_usub_sat:
case nir_op_ineg:
case nir_op_imul:
case nir_op_imin:
case nir_op_imax:
case nir_op_umin:
case nir_op_umax:
return 2;
case nir_op_ishl: /* TODO: in NIR, these have 32bit shift operands */
case nir_op_ishr: /* while Radeon needs 16bit operands when vectorized */
case nir_op_ushr:
default:
return 1;
}
return aco_nir_op_supports_packed_math_16bit(alu) ? 2 : 1;
}
static nir_component_mask_t