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radv: clarify why STAGE_2_CLEAR_BIT needs to wait for CP DMA to be idle

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To clarify that other clear operations like vkCmdFillBuffer() are
implicitly synchronized. So, STAGE_2_CLEAR_BIT is only needed for
vkCmdUpdateBuffer() in some rare cases (GFX10+ dGPUs with GTT BOs).

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15943>
This commit is contained in:
Samuel Pitoiset 2022-04-14 09:20:14 +02:00 • committed by Marge Bot
parent 107acf5a4a
commit 591e3296cd
1 changed files with 3 additions and 1 deletions
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4
src/amd/vulkan/radv_cmd_buffer.c
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@ -8461,7 +8461,9 @@ radv_barrier(struct radv_cmd_buffer *cmd_buffer, const VkDependencyInfo *dep_inf
}
/* Make sure CP DMA is idle because the driver might have performed a DMA operation for copying a
* buffer (or a MSAA image using FMASK) or updated a buffer which is a transfer operation.
* buffer (or a MSAA image using FMASK). Note that updating a buffer is considered a clear
* operation but it might also use a CP DMA copy in some rare situations. Other operations using
* a CP DMA clear are implicitly synchronized (see CP_DMA_SYNC).
*/
if (src_stage_mask &
(VK_PIPELINE_STAGE_2_COPY_BIT | VK_PIPELINE_STAGE_2_CLEAR_BIT |