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i965/gen6+: Invalidate constant cache on brw_emit_mi_flush().

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In order to make sure that the constant cache is coherent with
previous rendering when we start using it for pull constant loads.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Francisco Jerez 2016-12-08 18:00:17 -08:00
parent e0c1ec3b09
commit 591e14ec08
1 changed files with 1 additions and 0 deletions
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src/mesa/drivers/dri/i965/brw_pipe_control.c
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@ -351,6 +351,7 @@ brw_emit_mi_flush(struct brw_context *brw)
int flags = PIPE_CONTROL_NO_WRITE | PIPE_CONTROL_RENDER_TARGET_FLUSH;
if (brw->gen >= 6) {
flags |= PIPE_CONTROL_INSTRUCTION_INVALIDATE |
PIPE_CONTROL_CONST_CACHE_INVALIDATE |
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
PIPE_CONTROL_VF_CACHE_INVALIDATE |
PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |