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i965: support destination horiz strides in align1 access mode.

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This is required for scatter writes in destination regions to work.
This commit is contained in:
Gary Wong 2008-10-29 19:53:33 -04:00
parent 963071ffea
commit 58dc8b7db5
2 changed files with 3 additions and 3 deletions
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2
src/mesa/drivers/dri/i965/brw_eu.h
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@ -65,7 +65,7 @@ struct brw_reg
GLuint abs:1; /* source only */
GLuint vstride:4; /* source only */
GLuint width:3; /* src only, align1 only */
GLuint hstride:2; /* src only, align1 only */
GLuint hstride:2; /* align1 only */
GLuint address_mode:1; /* relative addressing, hopefully! */
GLuint pad0:1;

4
src/mesa/drivers/dri/i965/brw_eu_emit.c
View file

@ -64,7 +64,7 @@ static void brw_set_dest( struct brw_instruction *insn,
if (insn->header.access_mode == BRW_ALIGN_1) {
insn->bits1.da1.dest_subreg_nr = dest.subnr;
insn->bits1.da1.dest_horiz_stride = BRW_HORIZONTAL_STRIDE_1;
insn->bits1.da1.dest_horiz_stride = dest.hstride;
}
else {
insn->bits1.da16.dest_subreg_nr = dest.subnr / 16;
@ -78,7 +78,7 @@ static void brw_set_dest( struct brw_instruction *insn,
*/
if (insn->header.access_mode == BRW_ALIGN_1) {
insn->bits1.ia1.dest_indirect_offset = dest.dw1.bits.indirect_offset;
insn->bits1.ia1.dest_horiz_stride = BRW_HORIZONTAL_STRIDE_1;
insn->bits1.ia1.dest_horiz_stride = dest.hstride;
}
else {
insn->bits1.ia16.dest_indirect_offset = dest.dw1.bits.indirect_offset;