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radeonsi: de-atomize L2 prefetch

Browse source 
I'd like to be able to move the prefetch call site around.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák 2017-07-29 21:07:23 +02:00
parent 4e629ca7c7
commit 58d062b87d
7 changed files with 11 additions and 9 deletions
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7
src/gallium/drivers/radeonsi/si_cp_dma.c
View file

@ -450,7 +450,7 @@ static void cik_prefetch_shader_async(struct si_context *sctx,
}
}
static void cik_emit_prefetch_L2(struct si_context *sctx, struct r600_atom *atom)
void cik_emit_prefetch_L2(struct si_context *sctx)
{
/* Prefetch shaders and VBO descriptors to TC L2. */
if (si_pm4_state_changed(sctx, ls))
@ -473,12 +473,11 @@ static void cik_emit_prefetch_L2(struct si_context *sctx, struct r600_atom *atom
}
if (si_pm4_state_changed(sctx, ps))
cik_prefetch_shader_async(sctx, sctx->queued.named.ps);
sctx->prefetch_L2 = false;
}
void si_init_cp_dma_functions(struct si_context *sctx)
{
sctx->b.clear_buffer = si_clear_buffer;
si_init_atom(sctx, &sctx->prefetch_L2, &sctx->atoms.s.prefetch_L2,
cik_emit_prefetch_L2);
}

2
src/gallium/drivers/radeonsi/si_descriptors.c
View file

@ -1177,7 +1177,7 @@ bool si_upload_vertex_buffer_descriptors(struct si_context *sctx)
* cache is needed. */
si_mark_atom_dirty(sctx, &sctx->shader_userdata.atom);
if (sctx->b.chip_class >= CIK)
si_mark_atom_dirty(sctx, &sctx->prefetch_L2);
sctx->prefetch_L2 = true;
sctx->vertex_buffers_dirty = false;
sctx->vertex_buffer_pointer_dirty = true;
return true;

2
src/gallium/drivers/radeonsi/si_hw_context.c
View file

@ -217,7 +217,7 @@ void si_begin_new_cs(struct si_context *ctx)
si_ce_restore_all_descriptors_at_ib_start(ctx);
if (ctx->b.chip_class >= CIK)
si_mark_atom_dirty(ctx, &ctx->prefetch_L2);
ctx->prefetch_L2 = true;
/* CLEAR_STATE disables all colorbuffers, so only enable bound ones. */
ctx->framebuffer.dirty_cbufs =

3
src/gallium/drivers/radeonsi/si_pipe.h
View file

@ -283,6 +283,7 @@ struct si_context {
bool gfx_flush_in_progress:1;
bool compute_is_busy:1;
bool prefetch_L2:1;
/* Atoms (direct states). */
union si_state_atoms atoms;
@ -293,7 +294,6 @@ struct si_context {
union si_state emitted;
/* Atom declarations. */
struct r600_atom prefetch_L2;
struct si_framebuffer framebuffer;
struct si_sample_locs msaa_sample_locs;
struct r600_atom db_render_state;
@ -484,6 +484,7 @@ void si_copy_buffer(struct si_context *sctx,
unsigned user_flags);
void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
uint64_t offset, unsigned size);
void cik_emit_prefetch_L2(struct si_context *sctx);
void si_init_cp_dma_functions(struct si_context *sctx);
/* si_debug.c */

1
src/gallium/drivers/radeonsi/si_state.h
View file

@ -141,7 +141,6 @@ union si_state {
union si_state_atoms {
struct {
/* The order matters. */
struct r600_atom *prefetch_L2;
struct r600_atom *render_cond;
struct r600_atom *streamout_begin;
struct r600_atom *streamout_enable; /* must be after streamout_begin */

3
src/gallium/drivers/radeonsi/si_state_draw.c
View file

@ -1346,6 +1346,9 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
if (sctx->b.flags)
si_emit_cache_flush(sctx);
if (sctx->prefetch_L2)
cik_emit_prefetch_L2(sctx);
/* Emit state atoms. */
mask = sctx->dirty_atoms;
while (mask) {

2
src/gallium/drivers/radeonsi/si_state_shaders.c
View file

@ -3308,7 +3308,7 @@ bool si_update_shaders(struct si_context *sctx)
}
if (sctx->b.chip_class >= CIK)
si_mark_atom_dirty(sctx, &sctx->prefetch_L2);
sctx->prefetch_L2 = true;
sctx->do_update_shaders = false;
return true;