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agx/lower_address: Handle large shifts

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If we manage to fold in a left shift that's bigger than the hardware can do, we
should at least avoid generating a useless right shift to feed the hardware
rather bailing completely.

For motivation, this form of address arithmetic is encountered when indexing
into arrays with large power-of-two element sizes (array-of-structs).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21643>
This commit is contained in:
Alyssa Rosenzweig 2023-03-02 01:06:39 -05:00 • committed by Marge Bot
parent 6203503196
commit 5865e23a07
1 changed files with 11 additions and 0 deletions
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11
src/asahi/compiler/agx_nir_lower_address.c
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@ -143,6 +143,17 @@ match_address(nir_builder *b, nir_ssa_scalar base, int8_t format_shift)
if (new_shift <= 2) {
match.offset = shifted;
match.shift = new_shift;
} else if (new_shift > 0) {
/* For large shifts, we do need an ishl instruction but we can
* shrink the shift to avoid generating an ishr.
*/
assert(new_shift >= 3);
nir_ssa_def *rewrite =
nir_ishl_imm(b, nir_vec_scalars(b, &shifted, 1), new_shift);
match.offset = nir_get_ssa_scalar(rewrite, 0);
match.shift = 0;
}
}
} else {