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radv: stop passing a graphics pipeline to radv_pipeline_nir_to_asm()
Also rename the function. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24423>
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1 changed files with 21 additions and 20 deletions
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@ -2244,18 +2244,18 @@ radv_create_gs_copy_shader(struct radv_device *device, struct vk_pipeline_cache
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}
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static void
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radv_pipeline_nir_to_asm(struct radv_device *device, struct radv_graphics_pipeline *pipeline,
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struct vk_pipeline_cache *cache, struct radv_shader_stage *stages,
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const struct radv_pipeline_key *pipeline_key,
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const struct radv_pipeline_layout *pipeline_layout, bool keep_executable_info,
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bool keep_statistic_info, VkShaderStageFlagBits active_nir_stages,
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struct radv_shader_binary **binaries, struct radv_shader_binary **gs_copy_binary)
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radv_graphics_shaders_nir_to_asm(struct radv_device *device, struct vk_pipeline_cache *cache,
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struct radv_shader_stage *stages, const struct radv_pipeline_key *pipeline_key,
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const struct radv_pipeline_layout *pipeline_layout, bool keep_executable_info,
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bool keep_statistic_info, VkShaderStageFlagBits active_nir_stages,
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struct radv_shader **shaders, struct radv_shader_binary **binaries,
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struct radv_shader **gs_copy_shader, struct radv_shader_binary **gs_copy_binary)
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{
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for (int s = MESA_VULKAN_SHADER_STAGES - 1; s >= 0; s--) {
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if (!(active_nir_stages & (1 << s)))
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continue;
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nir_shader *shaders[2] = {stages[s].nir, NULL};
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nir_shader *nir_shaders[2] = {stages[s].nir, NULL};
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unsigned shader_count = 1;
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/* On GFX9+, TES is merged with GS and VS is merged with TCS or GS. */
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@ -2269,32 +2269,32 @@ radv_pipeline_nir_to_asm(struct radv_device *device, struct radv_graphics_pipeli
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pre_stage = MESA_SHADER_VERTEX;
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}
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shaders[0] = stages[pre_stage].nir;
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shaders[1] = stages[s].nir;
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nir_shaders[0] = stages[pre_stage].nir;
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nir_shaders[1] = stages[s].nir;
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shader_count = 2;
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}
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int64_t stage_start = os_time_get_nano();
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bool dump_shader = radv_can_dump_shader(device, shaders[0], false);
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bool dump_shader = radv_can_dump_shader(device, nir_shaders[0], false);
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binaries[s] = radv_shader_nir_to_asm(device, &stages[s], shaders, shader_count, pipeline_key,
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binaries[s] = radv_shader_nir_to_asm(device, &stages[s], nir_shaders, shader_count, pipeline_key,
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keep_executable_info, keep_statistic_info);
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pipeline->base.shaders[s] = radv_shader_create(device, cache, binaries[s], keep_executable_info || dump_shader);
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radv_shader_generate_debug_info(device, dump_shader, binaries[s], pipeline->base.shaders[s], shaders,
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shader_count, &stages[s].info);
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shaders[s] = radv_shader_create(device, cache, binaries[s], keep_executable_info || dump_shader);
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radv_shader_generate_debug_info(device, dump_shader, binaries[s], shaders[s], nir_shaders, shader_count,
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&stages[s].info);
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if (s == MESA_SHADER_GEOMETRY && !stages[s].info.is_ngg) {
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pipeline->base.gs_copy_shader =
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*gs_copy_shader =
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radv_create_gs_copy_shader(device, cache, &stages[MESA_SHADER_GEOMETRY], pipeline_key, pipeline_layout,
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keep_executable_info, keep_statistic_info, gs_copy_binary);
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}
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stages[s].feedback.duration += os_time_get_nano() - stage_start;
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active_nir_stages &= ~(1 << shaders[0]->info.stage);
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if (shaders[1])
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active_nir_stages &= ~(1 << shaders[1]->info.stage);
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active_nir_stages &= ~(1 << nir_shaders[0]->info.stage);
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if (nir_shaders[1])
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active_nir_stages &= ~(1 << nir_shaders[1]->info.stage);
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}
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}
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@ -2688,8 +2688,9 @@ radv_graphics_pipeline_compile(struct radv_graphics_pipeline *pipeline, const Vk
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}
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/* Compile NIR shaders to AMD assembly. */
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radv_pipeline_nir_to_asm(device, pipeline, cache, stages, pipeline_key, pipeline_layout, keep_executable_info,
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keep_statistic_info, active_nir_stages, binaries, &gs_copy_binary);
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radv_graphics_shaders_nir_to_asm(device, cache, stages, pipeline_key, pipeline_layout, keep_executable_info,
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keep_statistic_info, active_nir_stages, pipeline->base.shaders, binaries,
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&pipeline->base.gs_copy_shader, &gs_copy_binary);
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if (!radv_pipeline_create_ps_epilog(device, pipeline, pipeline_key, lib_flags, &ps_epilog_binary))
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return VK_ERROR_OUT_OF_DEVICE_MEMORY;
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