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radv: add missing HTILE support for fb mip tail workaround

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PAL also applies to depth/stencil images with HTILE.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26589>
This commit is contained in:
Samuel Pitoiset 2023-12-14 16:12:58 +01:00 • committed by Marge Bot
parent 82553774e2
commit 57efe44f43
2 changed files with 17 additions and 0 deletions
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16
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -3459,6 +3459,17 @@ radv_emit_fb_mip_change_flush(struct radv_cmd_buffer *cmd_buffer)
if (color_mip_changed) {
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
}
const struct radv_image_view *iview = render->ds_att.iview;
if (iview) {
if ((radv_htile_enabled(iview->image, iview->vk.base_mip_level) ||
radv_htile_enabled(iview->image, cmd_buffer->state.ds_mip)) &&
cmd_buffer->state.ds_mip != iview->vk.base_mip_level) {
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB | RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
}
cmd_buffer->state.ds_mip = iview->vk.base_mip_level;
}
}
/* This function does the flushes for mip changes if the levels are not zero for
@ -3484,7 +3495,12 @@ radv_emit_mip_change_flush_default(struct radv_cmd_buffer *cmd_buffer)
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
}
if (cmd_buffer->state.ds_mip) {
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB | RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
}
memset(cmd_buffer->state.cb_mip, 0, sizeof(cmd_buffer->state.cb_mip));
cmd_buffer->state.ds_mip = 0;
}
static void

1
src/amd/vulkan/radv_private.h
View file

@ -1691,6 +1691,7 @@ struct radv_cmd_state {
bool mesh_shading;
uint8_t cb_mip[MAX_RTS];
uint8_t ds_mip;
/* Whether DRAW_{INDEX}_INDIRECT_{MULTI} is emitted. */
bool uses_draw_indirect;