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https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-01-29 03:00:23 +01:00
v3dv: fix depth/stencil clears on hardware
There is a hw bug by which the only way to clear the depth/stencil tile buffers is to emit a clear of all tile buffers, so if we have to do any such clears, we just emit a single clear of all tile buffers and skip doing any per-buffer clears, even for color buffers, since they would be redundant. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6766>
This commit is contained in:
Iago Toral Quiroga
Marge Bot
parent
ce681aac70
commit
57d0ff8d48
1 changed files with 85 additions and 81 deletions
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@ -1259,6 +1259,86 @@ cmd_buffer_render_pass_emit_stores(struct v3dv_cmd_buffer *cmd_buffer,
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&state->pass->subpasses[state->subpass_idx];
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bool has_stores = false;
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bool use_per_buffer_clear = true;
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/* FIXME: separate stencil */
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uint32_t ds_attachment_idx = subpass->ds_attachment.attachment;
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if (ds_attachment_idx != VK_ATTACHMENT_UNUSED) {
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const struct v3dv_render_pass_attachment *ds_attachment =
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&state->pass->attachments[ds_attachment_idx];
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assert(state->job->first_subpass >= ds_attachment->first_subpass);
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assert(state->subpass_idx >= ds_attachment->first_subpass);
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assert(state->subpass_idx <= ds_attachment->last_subpass);
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/* From the Vulkan spec, VkImageSubresourceRange:
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*
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* "When an image view of a depth/stencil image is used as a
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* depth/stencil framebuffer attachment, the aspectMask is ignored
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* and both depth and stencil image subresources are used."
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*
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* So we ignore the aspects from the subresource range of the image view
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* for the depth/stencil attachment, but we still need to restrict this
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* to aspects that actually exist in the image.
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*/
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const VkImageAspectFlags aspects =
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vk_format_aspects(ds_attachment->desc.format);
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/* Only clear once on the first subpass that uses the attachment */
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bool needs_depth_clear =
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(aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
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state->tile_aligned_render_area &&
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state->job->first_subpass == ds_attachment->first_subpass &&
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ds_attachment->desc.loadOp == VK_ATTACHMENT_LOAD_OP_CLEAR &&
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!state->job->is_subpass_continue;
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bool needs_stencil_clear =
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(aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
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state->tile_aligned_render_area &&
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state->job->first_subpass == ds_attachment->first_subpass &&
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ds_attachment->desc.stencilLoadOp == VK_ATTACHMENT_LOAD_OP_CLEAR &&
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!state->job->is_subpass_continue;
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/* Skip the last store if it is not required */
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bool needs_depth_store =
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(aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
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(state->subpass_idx < ds_attachment->last_subpass ||
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ds_attachment->desc.storeOp == VK_ATTACHMENT_STORE_OP_STORE ||
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needs_depth_clear ||
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!state->job->is_subpass_finish);
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bool needs_stencil_store =
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(aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
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(state->subpass_idx < ds_attachment->last_subpass ||
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ds_attachment->desc.stencilStoreOp == VK_ATTACHMENT_STORE_OP_STORE ||
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needs_stencil_clear ||
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!state->job->is_subpass_finish);
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/* GFXH-1461/GFXH-1689: The per-buffer store command's clear
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* buffer bit is broken for depth/stencil. In addition, the
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* clear packet's Z/S bit is broken, but the RTs bit ends up
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* clearing Z/S.
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*
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* So if we have to emit a clear of depth or stencil we don't use
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* per-buffer clears, not even for color, since we will have to emit
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* a clear command for all tile buffers (including color) to handle
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* the depth/stencil clears.
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*
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* Note that this bug is not reproduced in the simulator, where
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* using the clear buffer bit in depth/stencil stores seems to work
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* correctly.
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*/
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use_per_buffer_clear = !needs_stencil_clear && !needs_depth_clear;
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bool needs_ds_store = needs_stencil_store || needs_depth_store;
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if (needs_ds_store) {
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uint32_t zs_buffer = v3dv_zs_buffer_from_aspect_bits(aspects);
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cmd_buffer_render_pass_emit_store(cmd_buffer, cl,
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ds_attachment_idx, layer,
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zs_buffer, false);
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has_stores = true;
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}
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}
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for (uint32_t i = 0; i < subpass->color_count; i++) {
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uint32_t attachment_idx = subpass->color_attachments[i].attachment;
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@ -1290,85 +1370,7 @@ cmd_buffer_render_pass_emit_stores(struct v3dv_cmd_buffer *cmd_buffer,
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cmd_buffer_render_pass_emit_store(cmd_buffer, cl,
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attachment_idx, layer,
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RENDER_TARGET_0 + i,
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needs_clear);
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has_stores = true;
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}
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}
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/* FIXME: separate stencil
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*
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* GFXH-1461/GFXH-1689: The per-buffer store command's clear
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* buffer bit is broken for depth/stencil. In addition, the
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* clear packet's Z/S bit is broken, but the RTs bit ends up
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* clearing Z/S.
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*
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* This means that when we implement depth/stencil clearing we
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* need to emit a separate clear before we start the render pass,
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* since the RTs bit is for clearing all render targets, and we might
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* not want to do that. We might want to consider emitting clears for
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* all RTs needing clearing just once ahead of the first subpass.
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*/
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bool needs_depth_clear = false;
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bool needs_stencil_clear = false;
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uint32_t ds_attachment_idx = subpass->ds_attachment.attachment;
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if (ds_attachment_idx != VK_ATTACHMENT_UNUSED) {
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const struct v3dv_render_pass_attachment *ds_attachment =
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&state->pass->attachments[ds_attachment_idx];
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assert(state->job->first_subpass >= ds_attachment->first_subpass);
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assert(state->subpass_idx >= ds_attachment->first_subpass);
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assert(state->subpass_idx <= ds_attachment->last_subpass);
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/* From the Vulkan spec, VkImageSubresourceRange:
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*
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* "When an image view of a depth/stencil image is used as a
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* depth/stencil framebuffer attachment, the aspectMask is ignored
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* and both depth and stencil image subresources are used."
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*
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* So we ignore the aspects from the subresource range of the image view
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* for the depth/stencil attachment, but we still need to restrict this
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* to aspects that actually exist in the image.
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*/
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const VkImageAspectFlags aspects =
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vk_format_aspects(ds_attachment->desc.format);
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/* Only clear once on the first subpass that uses the attachment */
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needs_depth_clear =
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(aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
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state->tile_aligned_render_area &&
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state->job->first_subpass == ds_attachment->first_subpass &&
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ds_attachment->desc.loadOp == VK_ATTACHMENT_LOAD_OP_CLEAR &&
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!state->job->is_subpass_continue;
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needs_stencil_clear =
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(aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
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state->tile_aligned_render_area &&
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state->job->first_subpass == ds_attachment->first_subpass &&
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ds_attachment->desc.stencilLoadOp == VK_ATTACHMENT_LOAD_OP_CLEAR &&
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!state->job->is_subpass_continue;
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/* Skip the last store if it is not required */
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bool needs_depth_store =
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(aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
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(state->subpass_idx < ds_attachment->last_subpass ||
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ds_attachment->desc.storeOp == VK_ATTACHMENT_STORE_OP_STORE ||
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needs_depth_clear ||
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!state->job->is_subpass_finish);
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bool needs_stencil_store =
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(aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
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(state->subpass_idx < ds_attachment->last_subpass ||
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ds_attachment->desc.stencilStoreOp == VK_ATTACHMENT_STORE_OP_STORE ||
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needs_stencil_clear ||
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!state->job->is_subpass_finish);
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bool needs_ds_clear = needs_stencil_clear || needs_depth_clear;
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bool needs_ds_store = needs_stencil_store || needs_depth_store;
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if (needs_ds_store) {
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uint32_t zs_buffer = v3dv_zs_buffer_from_aspect_bits(aspects);
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cmd_buffer_render_pass_emit_store(cmd_buffer, cl,
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ds_attachment_idx, layer,
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zs_buffer, needs_ds_clear);
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needs_clear && use_per_buffer_clear);
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has_stores = true;
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}
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}
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@ -1380,8 +1382,10 @@ cmd_buffer_render_pass_emit_stores(struct v3dv_cmd_buffer *cmd_buffer,
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}
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}
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/* FIXME: see fixme remark for depth/stencil above */
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if (needs_depth_clear && needs_stencil_clear) {
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/* If we have any depth/stencil clears we can't use the per-buffer clear
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* bit and instead we have to emit a single clear of all tile buffers.
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*/
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if (!use_per_buffer_clear) {
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cl_emit(cl, CLEAR_TILE_BUFFERS, clear) {
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clear.clear_z_stencil_buffer = true;
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clear.clear_all_render_targets = true;
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