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anv: add a drirc to control binding table block size

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Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39527>
This commit is contained in:
Lionel Landwerlin 2026-01-26 23:36:16 +02:00 • committed by Marge Bot
parent 8a5ac96a67
commit 57c90e86bf
4 changed files with 12 additions and 3 deletions
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4
src/intel/vulkan/anv_device.c
View file

@ -712,7 +712,7 @@ VkResult anv_CreateDevice(
&(struct anv_state_pool_params) {
.name = "binding table pool",
.base_address = device->physical->va.binding_table_pool.addr,
.block_size = BINDING_TABLE_POOL_BLOCK_SIZE,
.block_size = device->physical->instance->binding_table_block_size,
.max_size = device->physical->va.binding_table_pool.size,
});
} else {
@ -730,7 +730,7 @@ VkResult anv_CreateDevice(
.name = "binding table pool",
.base_address = device->physical->va.internal_surface_state_pool.addr,
.start_offset = bt_pool_offset,
.block_size = BINDING_TABLE_POOL_BLOCK_SIZE,
.block_size = 64 * 1024,
.max_size = device->physical->va.internal_surface_state_pool.size,
});
}

4
src/intel/vulkan/anv_instance.c
View file

@ -28,6 +28,8 @@ static const driOptionDescription anv_dri_options[] = {
DRI_CONF_ANV_GENERATED_INDIRECT_THRESHOLD(4)
DRI_CONF_ANV_GENERATED_INDIRECT_RING_THRESHOLD(100)
DRI_CONF_NO_16BIT(false)
DRI_CONF_INTEL_BINDING_TABLE_BLOCK_SIZE(BINDING_TABLE_POOL_DEFAULT_BLOCK_SIZE,
1024, 128 * 1024)
DRI_CONF_INTEL_ENABLE_WA_14018912822(false)
DRI_CONF_INTEL_ENABLE_WA_14024015672_MSAA(false)
DRI_CONF_INTEL_SAMPLER_ROUTE_TO_LSC(false)
@ -235,6 +237,8 @@ anv_init_dri_options(struct anv_instance *instance)
driQueryOptionb(&instance->dri_options, "vk_lower_terminate_to_discard");
instance->disable_xe2_drm_ccs_modifiers =
driQueryOptionb(&instance->dri_options, "anv_disable_drm_ccs_modifiers");
instance->binding_table_block_size = util_next_power_of_two(
driQueryOptioni(&instance->dri_options, "intel_binding_table_block_size"));
if (instance->vk.app_info.engine_name &&
!strcmp(instance->vk.app_info.engine_name, "DXVK")) {

3
src/intel/vulkan/anv_private.h
View file

@ -174,7 +174,7 @@ struct intel_perf_query_result;
/* 3DSTATE_BINDING_TABLE_POINTERS_*::PointertoBindingTable resolution */
#define BINDING_TABLE_VIEW_SIZE (1u << 20)
#define BINDING_TABLE_POOL_BLOCK_SIZE (65536)
#define BINDING_TABLE_POOL_DEFAULT_BLOCK_SIZE (4096)
#define HW_MAX_VBS 33
@ -1796,6 +1796,7 @@ struct anv_instance {
bool large_workgroup_non_coherent_image_workaround;
bool force_sampler_prefetch;
bool force_compute_surface_prefetch;
unsigned binding_table_block_size;
/* HW workarounds */
bool no_16bit;

4
src/util/driconf.h
View file

@ -350,6 +350,10 @@
DRI_CONF_OPT_B(fake_sparse, def, \
"Advertise support for sparse binding of textures regardless of real support")
#define DRI_CONF_INTEL_BINDING_TABLE_BLOCK_SIZE(def,min,max) \
DRI_CONF_OPT_I(intel_binding_table_block_size, def, min, max, \
"Intel binding table block allocation size (3DSTATE_BINDING_TABLE_POOL_ALLOC)")
#define DRI_CONFIG_INTEL_TBIMR(def) \
DRI_CONF_OPT_B(intel_tbimr, def, "Enable TBIMR tiled rendering")