fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-01-31 07:00:27 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 3

nir: model dynamic uniform layout on hk

Browse source 
add some new intrinsics so we can defer lowering until we have the information.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35658>
This commit is contained in:
Alyssa Rosenzweig 2025-05-30 12:31:43 -04:00 • committed by Marge Bot
parent 7b81c5bb78
commit 5795c8595f
2 changed files with 5 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/compiler/nir/nir_divergence_analysis.c
View file

@ -354,6 +354,7 @@ visit_intrinsic(nir_intrinsic_instr *instr, struct divergence_state *state)
case nir_intrinsic_load_core_id_agx:
case nir_intrinsic_load_samples_log2_agx:
case nir_intrinsic_load_active_subgroup_count_agx:
case nir_intrinsic_load_root_agx:
case nir_intrinsic_load_fs_msaa_intel:
case nir_intrinsic_load_constant_base_ptr:
case nir_intrinsic_load_const_buf_base_addr_lvp:
@ -716,6 +717,7 @@ visit_intrinsic(nir_intrinsic_instr *instr, struct divergence_state *state)
case nir_intrinsic_load_global_constant_offset:
case nir_intrinsic_load_reg:
case nir_intrinsic_load_constant_agx:
case nir_intrinsic_load_texture_handle_agx:
case nir_intrinsic_load_reg_indirect:
case nir_intrinsic_load_const_ir3:
case nir_intrinsic_load_frag_size_ir3:

3
src/compiler/nir/nir_intrinsics.py
View file

@ -2068,6 +2068,9 @@ system_value("is_first_fan_agx", 1, bit_sizes=[1])
# mesa_prim for the input topology (in a geometry shader)
system_value("input_topology_agx", 1)
# Root descriptor address
system_value("root_agx", 1, bit_sizes=[64])
# Load a bindless sampler handle mapping a binding table sampler.
intrinsic("load_sampler_handle_agx", [1], 1, [],
flags=[CAN_ELIMINATE, CAN_REORDER],