From 574404010a672c2c8aa4c041f4ef38cb6b2bfab2 Mon Sep 17 00:00:00 2001 From: Karol Herbst Date: Fri, 13 May 2022 17:36:14 +0200 Subject: [PATCH] nouveau: wrap nouveau_pushbuf_refn This makes it easier to insert locking code around libdrm. Signed-off-by: Karol Herbst Reviewed-by: M Henning Part-of: --- src/gallium/drivers/nouveau/nouveau_winsys.h | 13 +++++++++++++ src/gallium/drivers/nouveau/nv30/nv30_clear.c | 10 ++-------- src/gallium/drivers/nouveau/nv30/nv30_transfer.c | 10 +++++----- src/gallium/drivers/nouveau/nv30/nv30_winsys.h | 7 ------- src/gallium/drivers/nouveau/nv50/nv50_query.c | 2 +- src/gallium/drivers/nouveau/nv50/nv50_query_hw.c | 4 ++-- src/gallium/drivers/nouveau/nv50/nv50_surface.c | 6 +++--- src/gallium/drivers/nouveau/nv50/nv50_transfer.c | 2 +- src/gallium/drivers/nouveau/nv50/nv50_vbo.c | 2 +- src/gallium/drivers/nouveau/nv50/nv50_winsys.h | 8 -------- src/gallium/drivers/nouveau/nv50/nv84_video.c | 2 +- src/gallium/drivers/nouveau/nv50/nv84_video_bsp.c | 2 +- src/gallium/drivers/nouveau/nv50/nv84_video_vp.c | 6 +++--- src/gallium/drivers/nouveau/nv50/nv98_video.c | 6 +++--- src/gallium/drivers/nouveau/nv50/nv98_video_bsp.c | 2 +- src/gallium/drivers/nouveau/nv50/nv98_video_ppp.c | 2 +- src/gallium/drivers/nouveau/nv50/nv98_video_vp.c | 2 +- src/gallium/drivers/nouveau/nvc0/nvc0_compute.c | 6 +++--- src/gallium/drivers/nouveau/nvc0/nvc0_query.c | 2 +- src/gallium/drivers/nouveau/nvc0/nvc0_query_hw.c | 12 ++++++------ src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 6 +++--- src/gallium/drivers/nouveau/nvc0/nvc0_surface.c | 6 +++--- src/gallium/drivers/nouveau/nvc0/nvc0_transfer.c | 2 +- src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c | 4 ++-- src/gallium/drivers/nouveau/nvc0/nvc0_video.c | 6 +++--- src/gallium/drivers/nouveau/nvc0/nvc0_video_bsp.c | 2 +- src/gallium/drivers/nouveau/nvc0/nvc0_video_ppp.c | 2 +- src/gallium/drivers/nouveau/nvc0/nvc0_video_vp.c | 2 +- src/gallium/drivers/nouveau/nvc0/nvc0_winsys.h | 8 -------- src/gallium/drivers/nouveau/nvc0/nve4_compute.c | 6 +++--- 30 files changed, 67 insertions(+), 83 deletions(-) diff --git a/src/gallium/drivers/nouveau/nouveau_winsys.h b/src/gallium/drivers/nouveau/nouveau_winsys.h index 8365f3d8812..afff3ab6eef 100644 --- a/src/gallium/drivers/nouveau/nouveau_winsys.h +++ b/src/gallium/drivers/nouveau/nouveau_winsys.h @@ -69,6 +69,19 @@ PUSH_DATAf(struct nouveau_pushbuf *push, float f) PUSH_DATA(push, u.i); } +static inline int +PUSH_REFN(struct nouveau_pushbuf *push, struct nouveau_pushbuf_refn *refs, int nr) +{ + return nouveau_pushbuf_refn(push, refs, nr); +} + +static inline int +PUSH_REF1(struct nouveau_pushbuf *push, struct nouveau_bo *bo, uint32_t flags) +{ + struct nouveau_pushbuf_refn ref = { bo, flags }; + return PUSH_REFN(push, &ref, 1); +} + static inline void PUSH_KICK(struct nouveau_pushbuf *push) { diff --git a/src/gallium/drivers/nouveau/nv30/nv30_clear.c b/src/gallium/drivers/nouveau/nv30/nv30_clear.c index 9798639b88c..2b8ea9700cf 100644 --- a/src/gallium/drivers/nouveau/nv30/nv30_clear.c +++ b/src/gallium/drivers/nouveau/nv30/nv30_clear.c @@ -129,7 +129,6 @@ nv30_clear_render_target(struct pipe_context *pipe, struct pipe_surface *ps, struct nv30_miptree *mt = nv30_miptree(ps->texture); struct nouveau_pushbuf *push = nv30->base.pushbuf; struct nouveau_object *eng3d = nv30->screen->eng3d; - struct nouveau_pushbuf_refn refn; uint32_t rt_format; rt_format = nv30_format(pipe->screen, ps->format)->hw; @@ -146,10 +145,8 @@ nv30_clear_render_target(struct pipe_context *pipe, struct pipe_surface *ps, rt_format |= NV30_3D_RT_FORMAT_TYPE_LINEAR; } - refn.bo = mt->base.bo; - refn.flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_WR; if (!PUSH_SPACE_EX(push, 32, 1, 0) || - nouveau_pushbuf_refn (push, &refn, 1)) + PUSH_REF1(push, mt->base.bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR)) return; BEGIN_NV04(push, NV30_3D(RT_ENABLE), 1); @@ -190,7 +187,6 @@ nv30_clear_depth_stencil(struct pipe_context *pipe, struct pipe_surface *ps, struct nv30_miptree *mt = nv30_miptree(ps->texture); struct nouveau_pushbuf *push = nv30->base.pushbuf; struct nouveau_object *eng3d = nv30->screen->eng3d; - struct nouveau_pushbuf_refn refn; uint32_t rt_format, mode = 0; rt_format = nv30_format(pipe->screen, ps->format)->hw; @@ -212,10 +208,8 @@ nv30_clear_depth_stencil(struct pipe_context *pipe, struct pipe_surface *ps, if (buffers & PIPE_CLEAR_STENCIL) mode |= NV30_3D_CLEAR_BUFFERS_STENCIL; - refn.bo = mt->base.bo; - refn.flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_WR; if (!PUSH_SPACE_EX(push, 32, 1, 0) || - nouveau_pushbuf_refn (push, &refn, 1)) + PUSH_REF1(push, mt->base.bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR)) return; BEGIN_NV04(push, NV30_3D(RT_ENABLE), 1); diff --git a/src/gallium/drivers/nouveau/nv30/nv30_transfer.c b/src/gallium/drivers/nouveau/nv30/nv30_transfer.c index aaee998cfb5..c78b896a729 100644 --- a/src/gallium/drivers/nouveau/nv30/nv30_transfer.c +++ b/src/gallium/drivers/nouveau/nv30/nv30_transfer.c @@ -156,7 +156,7 @@ nv30_transfer_rect_blit(XFER_ARGS) u32 format, stride; if (!PUSH_SPACE_EX(push, 512, 8, 0) || - nouveau_pushbuf_refn (push, refs, ARRAY_SIZE(refs))) + PUSH_REFN(push, refs, ARRAY_SIZE(refs))) return; /* various switches depending on cpp of the transfer */ @@ -432,7 +432,7 @@ nv30_transfer_rect_sifm(XFER_ARGS) } if (!PUSH_SPACE_EX(push, 64, 6, 0) || - nouveau_pushbuf_refn (push, refs, 2)) + PUSH_REFN(push, refs, 2)) return; if (dst->pitch) { @@ -517,7 +517,7 @@ nv30_transfer_rect_m2mf(XFER_ARGS) unsigned lines = (h > 2047) ? 2047 : h; if (!PUSH_SPACE_EX(push, 32, 2, 0) || - nouveau_pushbuf_refn (push, refs, 2)) + PUSH_REFN(push, refs, 2)) return; BEGIN_NV04(push, NV03_M2MF(OFFSET_IN), 8); @@ -709,7 +709,7 @@ nv30_transfer_copy_data(struct nouveau_context *nv, pages -= lines; if (!PUSH_SPACE_EX(push, 32, 2, 0) || - nouveau_pushbuf_refn (push, refs, 2)) + PUSH_REFN(push, refs, 2)) return; BEGIN_NV04(push, NV03_M2MF(OFFSET_IN), 8); @@ -733,7 +733,7 @@ nv30_transfer_copy_data(struct nouveau_context *nv, if (size) { if (!PUSH_SPACE_EX(push, 32, 2, 0) || - nouveau_pushbuf_refn (push, refs, 2)) + PUSH_REFN(push, refs, 2)) return; BEGIN_NV04(push, NV03_M2MF(OFFSET_IN), 8); diff --git a/src/gallium/drivers/nouveau/nv30/nv30_winsys.h b/src/gallium/drivers/nouveau/nv30/nv30_winsys.h index 2324b517c44..25897ea9f6b 100644 --- a/src/gallium/drivers/nouveau/nv30/nv30_winsys.h +++ b/src/gallium/drivers/nouveau/nv30/nv30_winsys.h @@ -39,13 +39,6 @@ PUSH_RESET(struct nouveau_pushbuf *push, int bin) nouveau_bufctx_reset(bufctx(push), bin); } -static inline void -PUSH_REFN(struct nouveau_pushbuf *push, int bin, - struct nouveau_bo *bo, uint32_t access) -{ - nouveau_bufctx_refn(bufctx(push), bin, bo, access); -} - static inline void PUSH_MTHDl(struct nouveau_pushbuf *push, int subc, int mthd, int bin, struct nouveau_bo *bo, uint32_t offset, uint32_t access) diff --git a/src/gallium/drivers/nouveau/nv50/nv50_query.c b/src/gallium/drivers/nouveau/nv50/nv50_query.c index 08820b33672..4d012a14047 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_query.c +++ b/src/gallium/drivers/nouveau/nv50/nv50_query.c @@ -132,7 +132,7 @@ nv50_render_condition(struct pipe_context *pipe, PUSH_DATA (push, 0); } - PUSH_REFN (push, hq->bo, NOUVEAU_BO_GART | NOUVEAU_BO_RD); + PUSH_REF1 (push, hq->bo, NOUVEAU_BO_GART | NOUVEAU_BO_RD); BEGIN_NV04(push, NV50_3D(COND_ADDRESS_HIGH), 3); PUSH_DATAh(push, hq->bo->offset + hq->offset); PUSH_DATA (push, hq->bo->offset + hq->offset); diff --git a/src/gallium/drivers/nouveau/nv50/nv50_query_hw.c b/src/gallium/drivers/nouveau/nv50/nv50_query_hw.c index 5e079cf3307..7508470e982 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_query_hw.c +++ b/src/gallium/drivers/nouveau/nv50/nv50_query_hw.c @@ -82,7 +82,7 @@ nv50_hw_query_get(struct nouveau_pushbuf *push, struct nv50_query *q, offset += hq->offset; PUSH_SPACE(push, 5); - PUSH_REFN (push, hq->bo, NOUVEAU_BO_GART | NOUVEAU_BO_WR); + PUSH_REF1 (push, hq->bo, NOUVEAU_BO_GART | NOUVEAU_BO_WR); BEGIN_NV04(push, NV50_3D(QUERY_ADDRESS_HIGH), 4); PUSH_DATAh(push, hq->bo->offset + offset); PUSH_DATA (push, hq->bo->offset + offset); @@ -471,7 +471,7 @@ nv84_hw_query_fifo_wait(struct nouveau_pushbuf *push, struct nv50_query *q) assert(!hq->is64bit); PUSH_SPACE(push, 5); - PUSH_REFN (push, hq->bo, NOUVEAU_BO_GART | NOUVEAU_BO_RD); + PUSH_REF1 (push, hq->bo, NOUVEAU_BO_GART | NOUVEAU_BO_RD); BEGIN_NV04(push, SUBC_3D(NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH), 4); PUSH_DATAh(push, hq->bo->offset + offset); PUSH_DATA (push, hq->bo->offset + offset); diff --git a/src/gallium/drivers/nouveau/nv50/nv50_surface.c b/src/gallium/drivers/nouveau/nv50/nv50_surface.c index 84c9bac414d..72f185b224e 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_surface.c +++ b/src/gallium/drivers/nouveau/nv50/nv50_surface.c @@ -298,7 +298,7 @@ nv50_clear_render_target(struct pipe_context *pipe, if (!PUSH_SPACE_EX(push, 64 + sf->depth, 1, 0)) return; - PUSH_REFN(push, bo, mt->base.domain | NOUVEAU_BO_WR); + PUSH_REF1(push, bo, mt->base.domain | NOUVEAU_BO_WR); BEGIN_NV04(push, NV50_3D(SCREEN_SCISSOR_HORIZ), 2); PUSH_DATA (push, ( width << 16) | dstx); @@ -397,7 +397,7 @@ nv50_clear_depth_stencil(struct pipe_context *pipe, if (!PUSH_SPACE_EX(push, 64 + sf->depth, 1, 0)) return; - PUSH_REFN(push, bo, mt->base.domain | NOUVEAU_BO_WR); + PUSH_REF1(push, bo, mt->base.domain | NOUVEAU_BO_WR); BEGIN_NV04(push, NV50_3D(SCREEN_SCISSOR_HORIZ), 2); PUSH_DATA (push, ( width << 16) | dstx); @@ -774,7 +774,7 @@ nv50_clear_buffer(struct pipe_context *pipe, if (!PUSH_SPACE_EX(push, 64, 1, 0)) return; - PUSH_REFN(push, buf->bo, buf->domain | NOUVEAU_BO_WR); + PUSH_REF1(push, buf->bo, buf->domain | NOUVEAU_BO_WR); BEGIN_NV04(push, NV50_3D(SCREEN_SCISSOR_HORIZ), 2); PUSH_DATA (push, width << 16); diff --git a/src/gallium/drivers/nouveau/nv50/nv50_transfer.c b/src/gallium/drivers/nouveau/nv50/nv50_transfer.c index 143d920552f..6438510d028 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_transfer.c +++ b/src/gallium/drivers/nouveau/nv50/nv50_transfer.c @@ -511,7 +511,7 @@ nv50_cb_bo_push(struct nouveau_context *nv, unsigned nr = MIN2(words, NV04_PFIFO_MAX_PACKET_LEN); PUSH_SPACE(push, nr + 3); - PUSH_REFN (push, bo, NOUVEAU_BO_WR | domain); + PUSH_REF1 (push, bo, NOUVEAU_BO_WR | domain); BEGIN_NV04(push, NV50_3D(CB_ADDR), 1); PUSH_DATA (push, (offset << 6) | bufid); BEGIN_NI04(push, NV50_3D(CB_DATA(0)), nr); diff --git a/src/gallium/drivers/nouveau/nv50/nv50_vbo.c b/src/gallium/drivers/nouveau/nv50/nv50_vbo.c index 830c13beeda..100c71b8c2d 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_vbo.c +++ b/src/gallium/drivers/nouveau/nv50/nv50_vbo.c @@ -632,7 +632,7 @@ nv50_draw_elements(struct nv50_context *nv50, bool shorten, PUSH_DATA (push, prim); PUSH_SPACE_EX(push, 16, 0, 1); - PUSH_REFN(push, buf->bo, NOUVEAU_BO_RD | buf->domain); + PUSH_REF1(push, buf->bo, NOUVEAU_BO_RD | buf->domain); switch (index_size) { case 4: diff --git a/src/gallium/drivers/nouveau/nv50/nv50_winsys.h b/src/gallium/drivers/nouveau/nv50/nv50_winsys.h index 7056258d1bf..cda05cedee9 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_winsys.h +++ b/src/gallium/drivers/nouveau/nv50/nv50_winsys.h @@ -39,14 +39,6 @@ nv50_add_bufctx_resident(struct nouveau_bufctx *bufctx, int bin, #define BCTX_REFN(bctx, bin, res, acc) \ nv50_add_bufctx_resident(bctx, NV50_BIND_##bin, res, NOUVEAU_BO_##acc) -static inline void -PUSH_REFN(struct nouveau_pushbuf *push, struct nouveau_bo *bo, uint32_t flags) -{ - struct nouveau_pushbuf_refn ref = { bo, flags }; - nouveau_pushbuf_refn(push, &ref, 1); -} - - #define SUBC_3D(m) 3, (m) #define NV50_3D(n) SUBC_3D(NV50_3D_##n) #define NV84_3D(n) SUBC_3D(NV84_3D_##n) diff --git a/src/gallium/drivers/nouveau/nv50/nv84_video.c b/src/gallium/drivers/nouveau/nv50/nv84_video.c index c5e04bb7dfb..41f74a66770 100644 --- a/src/gallium/drivers/nouveau/nv50/nv84_video.c +++ b/src/gallium/drivers/nouveau/nv50/nv84_video.c @@ -496,7 +496,7 @@ nv84_create_decoder(struct pipe_context *context, context->clear_render_target(context, &surf.base, &color, 0, 0, 1024, 1, false); PUSH_SPACE(nv50->base.pushbuf, 5); - PUSH_REFN(nv50->base.pushbuf, dec->fence, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR); + PUSH_REF1(nv50->base.pushbuf, dec->fence, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR); /* The clear_render_target is done via 3D engine, so use it to write to a * sempahore to indicate that it's done. */ diff --git a/src/gallium/drivers/nouveau/nv50/nv84_video_bsp.c b/src/gallium/drivers/nouveau/nv50/nv84_video_bsp.c index 4bd96105bbb..f988d0af212 100644 --- a/src/gallium/drivers/nouveau/nv50/nv84_video_bsp.c +++ b/src/gallium/drivers/nouveau/nv50/nv84_video_bsp.c @@ -201,7 +201,7 @@ nv84_decoder_bsp(struct nv84_decoder *dec, memcpy(dec->bitstream->map + 0x600, more_params, sizeof(more_params)); PUSH_SPACE(push, 5 + 21 + 3 + 2 + 4 + 2); - nouveau_pushbuf_refn(push, bo_refs, ARRAY_SIZE(bo_refs)); + PUSH_REFN(push, bo_refs, ARRAY_SIZE(bo_refs)); /* Wait for the fence = 1 */ BEGIN_NV04(push, SUBC_BSP(0x10), 4); diff --git a/src/gallium/drivers/nouveau/nv50/nv84_video_vp.c b/src/gallium/drivers/nouveau/nv50/nv84_video_vp.c index 811e0c60f83..a5d4d18fb82 100644 --- a/src/gallium/drivers/nouveau/nv50/nv84_video_vp.c +++ b/src/gallium/drivers/nouveau/nv50/nv84_video_vp.c @@ -141,13 +141,13 @@ nv84_decoder_vp_h264(struct nv84_decoder *dec, { bo1, NOUVEAU_BO_RDWR | NOUVEAU_BO_VRAM }, { bo2, NOUVEAU_BO_RDWR | NOUVEAU_BO_VRAM }, }; - nouveau_pushbuf_refn(push, bo_refs, ARRAY_SIZE(bo_refs)); + PUSH_REFN(push, bo_refs, ARRAY_SIZE(bo_refs)); } memcpy(dec->vp_params->map, ¶m1, sizeof(param1)); memcpy(dec->vp_params->map + 0x400, ¶m2, sizeof(param2)); - nouveau_pushbuf_refn(push, bo_refs, num_refs); + PUSH_REFN(push, bo_refs, num_refs); /* Wait for BSP to have completed */ BEGIN_NV04(push, SUBC_VP(0x10), 4); @@ -522,7 +522,7 @@ nv84_decoder_vp_mpeg12(struct nv84_decoder *dec, PUSH_SPACE(push, 10 + 3 + 2); - nouveau_pushbuf_refn(push, bo_refs, num_refs); + PUSH_REFN(push, bo_refs, num_refs); BEGIN_NV04(push, SUBC_VP(0x400), 9); PUSH_DATA (push, 0x543210); /* each nibble possibly a dma index */ diff --git a/src/gallium/drivers/nouveau/nv50/nv98_video.c b/src/gallium/drivers/nouveau/nv50/nv98_video.c index 1a5685c0a3f..07cb05550b1 100644 --- a/src/gallium/drivers/nouveau/nv50/nv98_video.c +++ b/src/gallium/drivers/nouveau/nv50/nv98_video.c @@ -276,7 +276,7 @@ nv98_create_decoder(struct pipe_context *context, /* So lets test if the fence is working? */ PUSH_SPACE_EX(push[0], 16, 1, 0); - PUSH_REFN (push[0], dec->fence_bo, NOUVEAU_BO_GART|NOUVEAU_BO_RDWR); + PUSH_REF1 (push[0], dec->fence_bo, NOUVEAU_BO_GART|NOUVEAU_BO_RDWR); BEGIN_NV04(push[0], SUBC_BSP(0x240), 3); PUSH_DATAh(push[0], dec->fence_bo->offset); PUSH_DATA (push[0], dec->fence_bo->offset); @@ -287,7 +287,7 @@ nv98_create_decoder(struct pipe_context *context, PUSH_KICK (push[0]); PUSH_SPACE_EX(push[1], 16, 1, 0); - PUSH_REFN (push[1], dec->fence_bo, NOUVEAU_BO_GART|NOUVEAU_BO_RDWR); + PUSH_REF1 (push[1], dec->fence_bo, NOUVEAU_BO_GART|NOUVEAU_BO_RDWR); BEGIN_NV04(push[1], SUBC_VP(0x240), 3); PUSH_DATAh(push[1], (dec->fence_bo->offset + 0x10)); PUSH_DATA (push[1], (dec->fence_bo->offset + 0x10)); @@ -298,7 +298,7 @@ nv98_create_decoder(struct pipe_context *context, PUSH_KICK (push[1]); PUSH_SPACE_EX(push[2], 16, 1, 0); - PUSH_REFN (push[2], dec->fence_bo, NOUVEAU_BO_GART|NOUVEAU_BO_RDWR); + PUSH_REF1 (push[2], dec->fence_bo, NOUVEAU_BO_GART|NOUVEAU_BO_RDWR); BEGIN_NV04(push[2], SUBC_PPP(0x240), 3); PUSH_DATAh(push[2], (dec->fence_bo->offset + 0x20)); PUSH_DATA (push[2], (dec->fence_bo->offset + 0x20)); diff --git a/src/gallium/drivers/nouveau/nv50/nv98_video_bsp.c b/src/gallium/drivers/nouveau/nv50/nv98_video_bsp.c index 7a87ad70064..2e8bf3b8af6 100644 --- a/src/gallium/drivers/nouveau/nv50/nv98_video_bsp.c +++ b/src/gallium/drivers/nouveau/nv50/nv98_video_bsp.c @@ -109,7 +109,7 @@ nv98_decoder_bsp(struct nouveau_vp3_decoder *dec, union pipe_desc desc, nouveau_vp3_vp_caps(dec, desc, target, comm_seq, vp_caps, is_ref, refs); PUSH_SPACE_EX(push, 32, num_refs, 0); - nouveau_pushbuf_refn(push, bo_refs, num_refs); + PUSH_REFN(push, bo_refs, num_refs); bsp_addr = bsp_bo->offset >> 8; inter_addr = inter_bo->offset >> 8; diff --git a/src/gallium/drivers/nouveau/nv50/nv98_video_ppp.c b/src/gallium/drivers/nouveau/nv50/nv98_video_ppp.c index a207291a07f..bbca2f99105 100644 --- a/src/gallium/drivers/nouveau/nv50/nv98_video_ppp.c +++ b/src/gallium/drivers/nouveau/nv50/nv98_video_ppp.c @@ -47,7 +47,7 @@ nv98_decoder_setup_ppp(struct nouveau_vp3_decoder *dec, struct nouveau_vp3_video bo_refs[i].bo = mt->base.bo; } - nouveau_pushbuf_refn(push, bo_refs, num_refs); + PUSH_REFN(push, bo_refs, num_refs); nouveau_vp3_ycbcr_offsets(dec, &y2, &cbcr, &cbcr2); BEGIN_NV04(push, SUBC_PPP(0x700), 10); diff --git a/src/gallium/drivers/nouveau/nv50/nv98_video_vp.c b/src/gallium/drivers/nouveau/nv50/nv98_video_vp.c index 96ed9a6cb1a..33f6f758a41 100644 --- a/src/gallium/drivers/nouveau/nv50/nv98_video_vp.c +++ b/src/gallium/drivers/nouveau/nv50/nv98_video_vp.c @@ -114,7 +114,7 @@ nv98_decoder_vp(struct nouveau_vp3_decoder *dec, union pipe_desc desc, PUSH_SPACE_EX(push, 32 + codec_extra, num_refs, 0); - nouveau_pushbuf_refn(push, bo_refs, num_refs); + PUSH_REFN(push, bo_refs, num_refs); bsp_addr = bsp_bo->offset >> 8; #if NOUVEAU_VP3_DEBUG_FENCE diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c b/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c index f61f9cd424f..24ee9bfff6c 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c @@ -465,14 +465,14 @@ nvc0_launch_grid(struct pipe_context *pipe, const struct pipe_grid_info *info) PUSH_DATA (push, info->block[2]); PUSH_SPACE_EX(push, 32, 2, 1); - PUSH_REFN(push, screen->text, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD); + PUSH_REF1(push, screen->text, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD); if (unlikely(info->indirect)) { struct nv04_resource *res = nv04_resource(info->indirect); uint32_t offset = res->offset + info->indirect_offset; unsigned macro = NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT; - PUSH_REFN(push, res->bo, NOUVEAU_BO_RD | res->domain); + PUSH_REF1(push, res->bo, NOUVEAU_BO_RD | res->domain); PUSH_DATA(push, NVC0_FIFO_PKHDR_1I(1, macro, 3)); nouveau_pushbuf_data(push, res->bo, offset, NVC0_IB_ENTRY_1_NO_PREFETCH | 3 * 4); @@ -512,7 +512,7 @@ nvc0_compute_update_indirect_invocations(struct nvc0_context *nvc0, uint32_t offset = res->offset + info->indirect_offset; PUSH_SPACE_EX(push, 16, 0, 8); - PUSH_REFN(push, res->bo, NOUVEAU_BO_RD | res->domain); + PUSH_REF1(push, res->bo, NOUVEAU_BO_RD | res->domain); BEGIN_1IC0(push, NVC0_3D(MACRO_COMPUTE_COUNTER), 7); PUSH_DATA(push, 6); PUSH_DATA(push, info->block[0]); diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_query.c b/src/gallium/drivers/nouveau/nvc0/nvc0_query.c index 0deb667a02e..085f9712d35 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_query.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_query.c @@ -153,7 +153,7 @@ nvc0_render_condition(struct pipe_context *pipe, nvc0_hw_query_fifo_wait(nvc0, q); PUSH_SPACE(push, 10); - PUSH_REFN (push, hq->bo, NOUVEAU_BO_GART | NOUVEAU_BO_RD); + PUSH_REF1 (push, hq->bo, NOUVEAU_BO_GART | NOUVEAU_BO_RD); BEGIN_NVC0(push, NVC0_3D(COND_ADDRESS_HIGH), 3); PUSH_DATAh(push, hq->bo->offset + hq->offset); PUSH_DATA (push, hq->bo->offset + hq->offset); diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw.c b/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw.c index c2f8344a3d6..a18fdf2e5ac 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw.c @@ -74,7 +74,7 @@ nvc0_hw_query_get(struct nouveau_pushbuf *push, struct nvc0_query *q, offset += hq->offset; PUSH_SPACE(push, 5); - PUSH_REFN (push, hq->bo, NOUVEAU_BO_GART | NOUVEAU_BO_WR); + PUSH_REF1 (push, hq->bo, NOUVEAU_BO_GART | NOUVEAU_BO_WR); BEGIN_NVC0(push, NVC0_3D(QUERY_ADDRESS_HIGH), 4); PUSH_DATAh(push, hq->bo->offset + offset); PUSH_DATA (push, hq->bo->offset + offset); @@ -130,7 +130,7 @@ nvc0_hw_query_write_compute_invocations(struct nvc0_context *nvc0, struct nouveau_pushbuf *push = nvc0->base.pushbuf; PUSH_SPACE_EX(push, 16, 0, 8); - PUSH_REFN(push, hq->bo, NOUVEAU_BO_GART | NOUVEAU_BO_WR); + PUSH_REF1(push, hq->bo, NOUVEAU_BO_GART | NOUVEAU_BO_WR); BEGIN_1IC0(push, NVC0_3D(MACRO_COMPUTE_COUNTER_TO_QUERY), 4); PUSH_DATA (push, nvc0->compute_invocations); PUSH_DATAh(push, nvc0->compute_invocations); @@ -436,8 +436,8 @@ nvc0_hw_get_query_result_resource(struct nvc0_context *nvc0, nvc0_hw_query_fifo_wait(nvc0, q); PUSH_SPACE_EX(push, 32, 2, 3); - PUSH_REFN (push, hq->bo, NOUVEAU_BO_GART | NOUVEAU_BO_RD); - PUSH_REFN (push, buf->bo, buf->domain | NOUVEAU_BO_WR); + PUSH_REF1 (push, hq->bo, NOUVEAU_BO_GART | NOUVEAU_BO_RD); + PUSH_REF1 (push, buf->bo, buf->domain | NOUVEAU_BO_WR); BEGIN_1IC0(push, NVC0_3D(MACRO_QUERY_BUFFER_WRITE), 9); switch (q->type) { case PIPE_QUERY_OCCLUSION_PREDICATE: @@ -629,7 +629,7 @@ nvc0_hw_query_pushbuf_submit(struct nouveau_pushbuf *push, { struct nvc0_hw_query *hq = nvc0_hw_query(q); - PUSH_REFN(push, hq->bo, NOUVEAU_BO_RD | NOUVEAU_BO_GART); + PUSH_REF1(push, hq->bo, NOUVEAU_BO_RD | NOUVEAU_BO_GART); nouveau_pushbuf_data(push, hq->bo, hq->offset + result_offset, 4 | NVC0_IB_ENTRY_1_NO_PREFETCH); } @@ -646,7 +646,7 @@ nvc0_hw_query_fifo_wait(struct nvc0_context *nvc0, struct nvc0_query *q) nouveau_fence_emit(hq->fence); PUSH_SPACE(push, 5); - PUSH_REFN (push, hq->bo, NOUVEAU_BO_GART | NOUVEAU_BO_RD); + PUSH_REF1 (push, hq->bo, NOUVEAU_BO_GART | NOUVEAU_BO_RD); BEGIN_NVC0(push, SUBC_3D(NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH), 4); if (hq->is64bit) { PUSH_DATAh(push, nvc0->screen->fence.bo->offset); diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c index c7736d25335..e12519ceb3a 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c @@ -936,7 +936,7 @@ nvc0_screen_resize_tls_area(struct nvc0_screen *screen, * segment, as it may have commands that will reference it. */ if (screen->tls) - PUSH_REFN(screen->base.pushbuf, screen->tls, + PUSH_REF1(screen->base.pushbuf, screen->tls, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RDWR); nouveau_bo_ref(NULL, &screen->tls); screen->tls = bo; @@ -959,7 +959,7 @@ nvc0_screen_resize_text_area(struct nvc0_screen *screen, uint64_t size) * segment, as it may have commands that will reference it. */ if (screen->text) - PUSH_REFN(push, screen->text, + PUSH_REF1(push, screen->text, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD); nouveau_bo_ref(NULL, &screen->text); screen->text = bo; @@ -1322,7 +1322,7 @@ nvc0_screen_create(struct nouveau_device *dev) if (ret) FAIL_SCREEN_INIT("Error allocating uniform BO: %d\n", ret); - PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR); + PUSH_REF1 (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR); /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */ BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3); diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c b/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c index 24e2a2963d4..5f95c709dec 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c @@ -301,7 +301,7 @@ nvc0_clear_render_target(struct pipe_context *pipe, if (!PUSH_SPACE(push, 32 + sf->depth)) return; - PUSH_REFN (push, res->bo, res->domain | NOUVEAU_BO_WR); + PUSH_REF1 (push, res->bo, res->domain | NOUVEAU_BO_WR); BEGIN_NVC0(push, NVC0_3D(CLEAR_COLOR(0)), 4); PUSH_DATAf(push, color->f[0]); @@ -571,7 +571,7 @@ nvc0_clear_buffer(struct pipe_context *pipe, if (!PUSH_SPACE(push, 40)) return; - PUSH_REFN (push, buf->bo, buf->domain | NOUVEAU_BO_WR); + PUSH_REF1 (push, buf->bo, buf->domain | NOUVEAU_BO_WR); BEGIN_NVC0(push, NVC0_3D(CLEAR_COLOR(0)), 4); PUSH_DATA (push, color.ui[0]); @@ -639,7 +639,7 @@ nvc0_clear_depth_stencil(struct pipe_context *pipe, if (!PUSH_SPACE(push, 32 + sf->depth)) return; - PUSH_REFN (push, mt->base.bo, mt->base.domain | NOUVEAU_BO_WR); + PUSH_REF1 (push, mt->base.bo, mt->base.domain | NOUVEAU_BO_WR); if (clear_flags & PIPE_CLEAR_DEPTH) { BEGIN_NVC0(push, NVC0_3D(CLEAR_DEPTH), 1); diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_transfer.c b/src/gallium/drivers/nouveau/nvc0/nvc0_transfer.c index 1da61c0370a..c5aab3075df 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_transfer.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_transfer.c @@ -598,7 +598,7 @@ nvc0_cb_bo_push(struct nouveau_context *nv, unsigned nr = MIN2(words, NV04_PFIFO_MAX_PACKET_LEN - 1); PUSH_SPACE(push, nr + 2); - PUSH_REFN (push, bo, NOUVEAU_BO_WR | domain); + PUSH_REF1 (push, bo, NOUVEAU_BO_WR | domain); BEGIN_1IC0(push, NVC0_3D(CB_POS), nr + 1); PUSH_DATA (push, offset); PUSH_DATAp(push, data, nr); diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c b/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c index fe51ed3ee15..b9ca992ffcb 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c @@ -870,9 +870,9 @@ nvc0_draw_indirect(struct nvc0_context *nvc0, const struct pipe_draw_info *info, } PUSH_SPACE_EX(push, 16, 0, pushes + !!buf_count); - PUSH_REFN(push, buf->bo, NOUVEAU_BO_RD | buf->domain); + PUSH_REF1(push, buf->bo, NOUVEAU_BO_RD | buf->domain); if (buf_count) - PUSH_REFN(push, buf_count->bo, NOUVEAU_BO_RD | buf_count->domain); + PUSH_REF1(push, buf_count->bo, NOUVEAU_BO_RD | buf_count->domain); PUSH_DATA(push, NVC0_FIFO_PKHDR_1I(0, macro, 3 + !!buf_count + draws * size)); PUSH_DATA(push, nvc0_prim_gl(info->mode)); diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_video.c b/src/gallium/drivers/nouveau/nvc0/nvc0_video.c index 3df13e26557..3ffc4204b81 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_video.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_video.c @@ -300,7 +300,7 @@ nvc0_create_decoder(struct pipe_context *context, /* So lets test if the fence is working? */ PUSH_SPACE_EX(push[0], 16, 1, 0); - PUSH_REFN (push[0], dec->fence_bo, NOUVEAU_BO_GART|NOUVEAU_BO_RDWR); + PUSH_REF1 (push[0], dec->fence_bo, NOUVEAU_BO_GART|NOUVEAU_BO_RDWR); BEGIN_NVC0(push[0], SUBC_BSP(0x240), 3); PUSH_DATAh(push[0], dec->fence_bo->offset); PUSH_DATA (push[0], dec->fence_bo->offset); @@ -311,7 +311,7 @@ nvc0_create_decoder(struct pipe_context *context, PUSH_KICK (push[0]); PUSH_SPACE_EX(push[1], 16, 1, 0); - PUSH_REFN (push[1], dec->fence_bo, NOUVEAU_BO_GART|NOUVEAU_BO_RDWR); + PUSH_REF1 (push[1], dec->fence_bo, NOUVEAU_BO_GART|NOUVEAU_BO_RDWR); BEGIN_NVC0(push[1], SUBC_VP(0x240), 3); PUSH_DATAh(push[1], (dec->fence_bo->offset + 0x10)); PUSH_DATA (push[1], (dec->fence_bo->offset + 0x10)); @@ -322,7 +322,7 @@ nvc0_create_decoder(struct pipe_context *context, PUSH_KICK (push[1]); PUSH_SPACE_EX(push[2], 16, 1, 0); - PUSH_REFN (push[2], dec->fence_bo, NOUVEAU_BO_GART|NOUVEAU_BO_RDWR); + PUSH_REF1 (push[2], dec->fence_bo, NOUVEAU_BO_GART|NOUVEAU_BO_RDWR); BEGIN_NVC0(push[2], SUBC_PPP(0x240), 3); PUSH_DATAh(push[2], (dec->fence_bo->offset + 0x20)); PUSH_DATA (push[2], (dec->fence_bo->offset + 0x20)); diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_video_bsp.c b/src/gallium/drivers/nouveau/nvc0/nvc0_video_bsp.c index 96eb1015374..df0b5286b33 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_video_bsp.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_video_bsp.c @@ -163,7 +163,7 @@ nvc0_decoder_bsp_end(struct nouveau_vp3_decoder *dec, union pipe_desc desc, nouveau_vp3_vp_caps(dec, desc, target, comm_seq, vp_caps, is_ref, refs); PUSH_SPACE_EX(push, 32, num_refs, 0); - nouveau_pushbuf_refn(push, bo_refs, num_refs); + PUSH_REFN(push, bo_refs, num_refs); bsp_addr = bsp_bo->offset >> 8; inter_addr = inter_bo->offset >> 8; diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_video_ppp.c b/src/gallium/drivers/nouveau/nvc0/nvc0_video_ppp.c index d36d172f2d0..6e633237023 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_video_ppp.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_video_ppp.c @@ -47,7 +47,7 @@ nvc0_decoder_setup_ppp(struct nouveau_vp3_decoder *dec, struct nouveau_vp3_video bo_refs[i].bo = mt->base.bo; } - nouveau_pushbuf_refn(push, bo_refs, num_refs); + PUSH_REFN(push, bo_refs, num_refs); nouveau_vp3_ycbcr_offsets(dec, &y2, &cbcr, &cbcr2); BEGIN_NVC0(push, SUBC_PPP(0x700), 10); diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_video_vp.c b/src/gallium/drivers/nouveau/nvc0/nvc0_video_vp.c index 6975783a73c..98dc1c937fc 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_video_vp.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_video_vp.c @@ -114,7 +114,7 @@ nvc0_decoder_vp(struct nouveau_vp3_decoder *dec, union pipe_desc desc, PUSH_SPACE_EX(push, 32 + codec_extra, num_refs, 0); - nouveau_pushbuf_refn(push, bo_refs, num_refs); + PUSH_REFN(push, bo_refs, num_refs); bsp_addr = bsp_bo->offset >> 8; #if NOUVEAU_VP3_DEBUG_FENCE diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_winsys.h b/src/gallium/drivers/nouveau/nvc0/nvc0_winsys.h index 81110493231..c9f4cf57162 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_winsys.h +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_winsys.h @@ -38,14 +38,6 @@ nvc0_add_resident(struct nouveau_bufctx *bufctx, int bin, #define BCTX_REFN(bctx, bin, res, acc) \ nvc0_add_resident(bctx, NVC0_BIND_##bin, res, NOUVEAU_BO_##acc) -static inline void -PUSH_REFN(struct nouveau_pushbuf *push, struct nouveau_bo *bo, uint32_t flags) -{ - struct nouveau_pushbuf_refn ref = { bo, flags }; - nouveau_pushbuf_refn(push, &ref, 1); -} - - #define SUBC_3D(m) 0, (m) #define NVC0_3D(n) SUBC_3D(NVC0_3D_##n) #define NVE4_3D(n) SUBC_3D(NVE4_3D_##n) diff --git a/src/gallium/drivers/nouveau/nvc0/nve4_compute.c b/src/gallium/drivers/nouveau/nvc0/nve4_compute.c index f07bc208377..dccbce91ef7 100644 --- a/src/gallium/drivers/nouveau/nvc0/nve4_compute.c +++ b/src/gallium/drivers/nouveau/nvc0/nve4_compute.c @@ -546,7 +546,7 @@ nve4_compute_upload_input(struct nvc0_context *nvc0, uint32_t offset = res->offset + info->indirect_offset; PUSH_SPACE_EX(push, 32, 0, 1); - PUSH_REFN(push, res->bo, NOUVEAU_BO_RD | res->domain); + PUSH_REF1(push, res->bo, NOUVEAU_BO_RD | res->domain); BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + 8); PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1)); @@ -830,7 +830,7 @@ nve4_upload_indirect_desc(struct nouveau_pushbuf *push, PUSH_DATA (push, 1); PUSH_SPACE_EX(push, 32, 0, 1); - PUSH_REFN(push, res->bo, NOUVEAU_BO_RD | res->domain); + PUSH_REF1(push, res->bo, NOUVEAU_BO_RD | res->domain); BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + (length / 4)); PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x08 << 1)); @@ -924,7 +924,7 @@ nve4_launch_grid(struct pipe_context *pipe, const struct pipe_grid_info *info) /* upload descriptor and flush */ PUSH_SPACE_EX(push, 32, 1, 0); - PUSH_REFN(push, screen->text, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD); + PUSH_REF1(push, screen->text, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD); BEGIN_NVC0(push, NVE4_CP(LAUNCH_DESC_ADDRESS), 1); PUSH_DATA (push, desc_gpuaddr >> 8); BEGIN_NVC0(push, NVE4_CP(LAUNCH), 1);